JP2006245226A - 半導体装置及びその製造方法 - Google Patents
半導体装置及びその製造方法 Download PDFInfo
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- JP2006245226A JP2006245226A JP2005057799A JP2005057799A JP2006245226A JP 2006245226 A JP2006245226 A JP 2006245226A JP 2005057799 A JP2005057799 A JP 2005057799A JP 2005057799 A JP2005057799 A JP 2005057799A JP 2006245226 A JP2006245226 A JP 2006245226A
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- opening
- insulating film
- wiring
- forming
- electrode
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Abstract
【解決手段】枠状半導体チップ10は、開口部10aが形成されていて、当該開口部の周囲を画成する枠部10bを有する半導体基板1と、枠部に設けられていて、電極端子12を有する1個又は2個以上の電子素子11と、電極端子の一部分を、複数の第1電極パッド12aとして露出させて、枠部上に設けられている第1絶縁膜14とを具えている。
【選択図】図1
Description
図1を参照して、この発明の第1の実施の形態につき説明する。この第1の実施の形態は、枠状半導体チップに関する。
図1(A)は、枠状半導体チップの構成を説明するための上面からみた概略的な平面図であり、(B)図は、(A)図中に示すA−A’一点鎖線と同じ位置で切断した切断面を示す概略的な図である。
図2及び図3を参照して、上述した構成を有する枠状半導体チップの製造方法につき説明する。
図4から図7を参照して、この発明の第2の実施の形態につき説明する。この第2の実施の形態は、上述した枠状半導体チップを用いる半導体装置、すなわちSIPに関する。
図4(A)は、SIPの構成を説明するための上面からみた概略的な平面図である。なお、電極パッド及び配線層の配置関係の説明を容易にするため、実際には存在する封止部の図示は省略してある。(B)図は、図4(A)中、A−A’一点鎖線で示す位置で切断した切断面を示す概略的な図である。
ここで、この発明のSIPの動作の一例につき、図4(A)及び(B)を参照して、簡単に説明する。なお、半導体装置100は、外部端子50を、図示しない実装基板の電極パッドに接続する形態で実装されるものとする。
図5〜図7を参照して、第2の実施の形態のSIPの製造方法につき説明する。
図8を参照して、この発明の第3の実施の形態につき説明する。この第3の実施の形態は、第2の実施の形態で説明した構成を有するSIPの変形例であって、パッケージの下面側に、機能性の下地を具える構成例に関する。
図8は、図4(A)における、A−A’一点鎖線により示した位置と同じ位置で半導体装置を切断した切断面を示す概略的な図である。
図9を参照して、第3の実施の形態のSIPの製造方法につき説明する。
図10及び11を参照して、この発明の第4の実施の形態につき説明する。この第4の実施の形態のSIPは、埋め込み部にスルーホール及びこのスルーホールを埋め込む埋込み配線部を具える構成例に関する。
図12及び図13を参照して、第4の実施の形態のSIPの製造方法につき説明する。図12(A)、(B)及び(C)は、製造途中の半導体装置を、図10(A)及び図11(A)中に示すB−B’一点鎖線により示した位置で切断した切断面を示す概略的な図である。
図14を参照して、この発明の第5の実施の形態につき説明する。この第5の実施の形態は、第4の実施の形態のSIPを複数個積層した構造体に関する。この例では2個のSIPを積層した例につき説明する。
1a:表面
1b:裏面
2:チップ領域
2a:開口部形成領域
10:枠状半導体チップ
10a:開口部
10aa:底面部
10ab:側壁部
10b:枠部
10ba:上面
10bb:下面
11:電子素子(受動素子)
12:電極端子
12a:第1電極パッド
14:第1絶縁膜
14a:表面
20:搭載半導体チップ
20a:第1搭載半導体チップ
20b:第2搭載半導体チップ
21a:第1の主表面
21b:第2の主表面
21c:側面
22:第2電極パッド
32:第2絶縁膜
32a:埋め込み部
32aa:上面
32ab:下面
34:第1配線層
34a:第1配線部
36:第3電極パッド
40:第1封止部
50:外部端子(第1外部端子)
52:柱状電極
52a:頂面
54:半田ボール
56:導電性バンプ
60:下地(薄板状部材)
60a:表面
60b:裏面
72:スルーホール
74:埋込み配線部
74a:上端部(一端)
74b:下端部(他端)
76:第3絶縁膜
78:第2配線層
78a:第2配線部
79:第3電極パッド(第2外部端子)
80:第2封止部
100:半導体装置
100a:第1半導体装置
100b:第2半導体装置
200:積層構造体
Claims (26)
- 開口部が形成されていて、当該開口部の周囲を画成する枠部を有する半導体基板と、
前記枠部に設けられていて、電極端子を有する1個又は2個以上の電子素子と、
前記電極端子の一部分を、複数の第1電極パッドとして露出させて、前記枠部上に設けられている第1絶縁膜と
を具えていることを特徴とする枠状半導体チップ。 - 前記開口部は、前記半導体基板の表面から当該半導体基板の内部に至って形成されていて、底面部及び側壁部を有する凹部であることを特徴とする請求項1に記載の枠状半導体チップ。
- 前記電子素子は、受動素子であることを特徴とする請求項1又は2に記載の枠状半導体チップ。
- 請求項1〜3のいずれか一項に記載の枠状半導体チップが、複数個作り込まれて設けられている半導体基板。
- 開口部が形成されていて、当該開口部の周囲を画成する枠部を有する半導体基板、当該枠部に設けられていて、電極端子を有する複数個の電子素子、当該枠部の上面に設けられ、前記電極端子の一部分を複数の第1電極パッドとして露出させる第1絶縁膜を有する枠状半導体チップと、
第2電極パッドを有する第1の主表面と、該第1の主表面と対向する第2の主表面とを有し、前記開口部内に、当該開口部の側壁部から離間して配置されている、1個又は2個以上の搭載半導体チップと、
前記第1及び第2電極パッドを露出させて、かつ前記開口部を埋め込んで埋め込み部を形成して、前記第1絶縁膜上及び前記第1の主表面上に設けられている第2絶縁膜と、
前記第1及び第2電極パッドのいずれか一方又は両方に電気的に接続され、かつ前記第2絶縁膜上に延在している、複数の第1配線部を含む第1配線層と、
複数の前記第1配線部に、電気的に接続されている複数の第1外部端子と、
前記第1配線層及び前記第2絶縁膜上に設けられていて、複数の前記第1外部端子を露出させる第1封止部と
を具えていることを特徴とする半導体装置。 - 前記電子素子は、受動素子であることを特徴とする請求項5に記載の半導体装置。
- 前記第1外部端子は、前記第1封止部からその頂面が露出する柱状電極であることを特徴とする請求項5又は6に記載の半導体装置。
- 前記第1外部端子は、前記柱状電極及び当該柱状電極の頂面に接続された半田ボールであることを特徴とする請求項7に記載の半導体装置。
- 前記開口部は、前記半導体基板の表面から当該半導体基板の内部に至って形成されていて、底面部及び側壁部を有する凹部であることを特徴とする請求項5〜8のいずれか一項に記載の半導体装置。
- 前記開口部は、貫通孔であることを特徴とする請求項5〜8のいずれか一項に記載の半導体装置。
- 1個又は2個以上の前記搭載半導体チップの前記第2の主表面及び前記枠部の下面を支持する下地を具えていることを特徴とする請求項10に記載の半導体装置。
- 前記下地は、遮光性を有する薄板状部材であることを特徴とする請求項11に記載の半導体装置。
- 前記下地は、放熱性を有する薄板状部材であることを特徴とする請求項11に記載の半導体装置。
- 前記下地は、放射ノイズを遮蔽する薄板状部材であることを特徴とする請求項11に記載の半導体装置。
- 前記開口部内の前記埋込み部を貫通するスルーホールと、当該スルーホールを埋め込み、一端が前記第1配線部に電気的に接続されている埋込み配線部と、
前記埋込み配線部の他端を露出させ、前記搭載半導体チップの第2の主表面及び前記枠部の下面を覆う第3絶縁膜と、
前記埋込み配線部の前記他端に電気的に接続され、前記第3絶縁膜上に延在する複数の第2配線部を含む第2配線層と、
前記第2配線部の一部分を露出させて第3電極パッドとする第2封止部と
を具えることを特徴とする請求項10に記載の半導体装置。 - 前記搭載半導体チップは、複数個が前記開口部内に納められていて、複数個の前記搭載半導体チップ同士は、互いに離間して前記開口部内に設けられていることを特徴とする請求項5〜15のいずれか一項に記載の半導体装置。
- 複数個の前記搭載半導体チップ同士の間隙を埋め込む前記埋め込み部には、前記スルーホール及び前記埋込み配線部が設けられていることを特徴とする請求項16に記載の半導体装置。
- 貫通孔である開口部が形成されていて、当該開口部の周囲を画成する枠部を有する半導体基板と、当該枠部に設けられていて、電極端子を有する複数の電子素子、前記枠部の上面に設けられている第1絶縁膜、前記電極端子の一部分を、複数の第1電極パッドとして露出させて、前記枠部上に設けられている第1絶縁膜を有する、同一形状の複数の枠状半導体チップ、複数の第2電極パッドを露出する第1の主表面、該第1の主表面と対向する第2の主表面を有し、前記開口部内に当該開口部の側壁部から離間して配置されている、1個又は2個以上の搭載半導体チップ、前記第1及び第2電極パッドを露出させて、かつ前記開口部を埋め込んで埋め込み部を形成して、前記第1絶縁膜上及び前記第1の主表面上に設けられている第2絶縁膜、前記第1及び第2電極パッドのいずれか一方又は両方に電気的に接続されていて、前記第2絶縁膜上に延在している複数の第1配線部を含む第1配線層、複数の前記第1配線部に、電気的に接続されている複数の第1外部端子、前記第1配線層及び前記第2絶縁膜上に設けられていて、複数の前記第1外部端子を露出させる第1封止部、前記開口部内の前記埋込み部を貫通するスルーホール、当該スルーホールを埋め込み、上端部が前記第1配線部に電気的に接続されている埋込み配線部、前記埋込み配線部の下端部を露出させ、前記搭載半導体チップの第2の主表面及び前記枠部の下面を覆う第3絶縁膜、前記埋込み配線部の前記他端に電気的に接続され、前記第3絶縁膜上に延在する第2配線部を含む第2配線層、前記第2配線部の一部分を露出させて第3電極パッドとする第2封止部を具えている複数の半導体装置を積層してある積層構造体であって、
複数個の前記半導体装置を、下側に位置する前記半導体装置の前記第1外部端子及び上側に位置する前記半導体装置の前記第3電極パッドを互いに対向させ、これらを電気的に接続して、順次に積層してあることを特徴とする積層構造体。 - 前記電子素子は、受動素子であることを特徴とする請求項18に記載の積層構造体。
- 表面及び裏面を有し、開口部形成領域を各々に含む複数のチップ領域が区画されている半導体基板を準備する工程と、
複数の前記チップ領域内であって、前記開口部形成領域を囲む領域内に、電極端子を有する1個又は2個以上の電子素子を作り込む工程と、
前記電極端子の一部分を露出させて第1電極パッドとする、第1絶縁膜を形成する工程と、
複数の前記開口部形成領域に、前記半導体基板の表面から当該半導体基板の内部に至って形成されていて、底面部及び側壁部を有する複数の開口部を形成する工程と、
複数の第2電極パッドが露出している第1の主表面、及び該第1の主表面に対向する第2の主表面を有する複数の搭載半導体チップを準備する工程と、
複数の前記開口部内に、前記第2の主表面が前記底面部と対向するように、かつ前記開口部の側壁部から離間させて、1個又は2個以上の前記搭載半導体チップを納めて搭載する工程と、
前記第1及び第2電極パッドの一部分を露出させて、かつ前記開口部を埋め込んで埋め込み部を形成し、かつ前記第1絶縁膜上及び前記第1の主表面上にわたる第2絶縁膜を形成する工程と、
前記第1及び第2電極パッドのいずれか一方又は両方に電気的に接続されていて、かつ前記第2絶縁膜上に延在する複数の第1配線部を含む第1配線層を形成する工程と、
複数の前記第1配線部に、電気的に接続されている複数の第1外部端子を形成する工程と、
前記第1配線層及び前記第2絶縁膜上に設けられていて、複数の前記第1外部端子を露出させる第1封止部を形成する工程と、
複数の前記チップ領域各々を切り出して、個片化を行う工程と
を含むことを特徴とする半導体装置の製造方法。 - 表面及び裏面を有し、当該表面に複数のチップ領域が区画されている半導体基板を準備する工程と、
複数の前記チップ領域であって、前記開口部形成領域を囲む領域内に、電極端子を有する1個又は2個以上の電子素子を作り込む工程と、
前記電極端子の一部分を露出させて第1電極パッドとする、第1絶縁膜を形成する工程と、
複数の前記開口部形成領域各々に、前記半導体基板の表面から当該半導体基板の内部に至って形成されていて、底面部及び側壁部を有する開口部を形成する工程と、
複数の第2電極パッドが露出している第1の主表面、該第1の主表面に対向する第2の主表面を有する複数の搭載半導体チップを準備する工程と、
複数の前記開口部内に、前記第2の主表面が前記底面部と対向するように、かつ前記開口部の側壁部から離間させて、1個又は2個以上の前記搭載半導体チップを納めて搭載する工程と、
前記開口部を埋め込んで埋め込み部を形成し、かつ前記第1及び第2電極パッドの一部分を露出させて、前記第1絶縁膜上及び前記第1の主表面上にわたる第2絶縁膜を形成する工程と、
前記埋め込み部の表面から前記開口部の前記底面部に至るスルーホールを形成する工程と、
前記スルーホールを導電性材料で埋め込んで埋込み配線部を形成する工程と、
前記埋込み配線部の上端部、前記第1及び第2電極パッドのいずれか又はこれらの任意の組み合わせに電気的に接続されていて、かつ前記第2絶縁膜上に延在する複数の第1配線部を含む第1配線層を形成する工程と、
複数の前記第1配線部に電気的に接続されている、複数の第1外部端子を形成する工程と、
前記第1配線層及び前記第2絶縁膜上に設けられていて、複数の前記第1外部端子を露出させる第1封止部を形成する工程と、
前記半導体基板の裏面を削って、前記搭載半導体チップの第2の主表面及び前記埋込み配線部の下端部を露出させる工程と、
前記埋込み配線部の下端部を露出させ、前記搭載半導体チップの第2の主表面及び前記枠部の下面を覆う第3絶縁膜を形成する工程と、
前記埋込み配線部の前記下端部に電気的に接続され、前記第3絶縁膜上に延在する第2配線部を含む第2配線層を形成する工程と、
複数の前記第2配線部の一部分を露出して、複数の第2外部端子とする第2封止部を形成する工程と、
複数の前記チップ領域各々を切り出して、個片化を行う工程と
を含むことを特徴とする半導体装置の製造方法。 - 前記電子素子を作り込む工程は、受動素子を作り込む工程であることを特徴とする請求項20又は21に記載の半導体装置の製造方法。
- 複数の前記搭載半導体チップを前記開口部内に搭載する工程は、複数の前記搭載半導体チップ同士を、互いに離間して前記開口部内に搭載する工程であることを特徴とする請求項20〜22のいずれか一項に記載の半導体装置の製造方法。
- 複数の前記搭載半導体チップを前記開口部内に搭載する工程は、複数の前記搭載半導体チップ同士を、互いに離間して前記開口部内に搭載する工程であり、
前記スルーホールを形成する工程は、複数の前記搭載半導体チップ同士の間隙を埋め込む前記埋め込み部に、前記スルーホールを形成する工程であることを特徴とする請求項21に記載の半導体装置の製造方法。 - 前記第1外部端子を形成する工程は、前記第1配線層を形成した後に、複数の前記第1配線部上に、複数の柱状電極を形成する工程であり、
前記第1封止部を形成する工程は、前記第1配線層及び前記第2絶縁膜上に、前記柱状電極の頂面を露出させて第1封止部を形成する工程であることを特徴とする請求項20〜24のいずれか一項に記載の半導体装置の製造方法。 - 前記第1封止部を形成する工程の後に、露出した前記柱状電極の頂面上に半田ボールを搭載する工程をさらに含むことを特徴とする請求項25に記載の半導体装置の製造方法。
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US20060214288A1 (en) | 2006-09-28 |
US7667315B2 (en) | 2010-02-23 |
JP4659488B2 (ja) | 2011-03-30 |
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