JP5568467B2 - 半導体装置 - Google Patents
半導体装置 Download PDFInfo
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- JP5568467B2 JP5568467B2 JP2010508142A JP2010508142A JP5568467B2 JP 5568467 B2 JP5568467 B2 JP 5568467B2 JP 2010508142 A JP2010508142 A JP 2010508142A JP 2010508142 A JP2010508142 A JP 2010508142A JP 5568467 B2 JP5568467 B2 JP 5568467B2
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Description
図1(a)及び(b)は、本発明の第1の実施形態に係る半導体装置100を示しており、図1(a)には半導体装置100の断面図を、図1(b)には半導体装置100の平面図を示している。尚、図1(b)におけるB−B’面での断面図が図1(a)であり、図1(a)におけるA−A’面での平面図が図1(b)である。
図3(a)及び(b)は、本発明の第2の実施形態に係る半導体装置における電極群の平面構成を示す図である。尚、本実施形態は、図1(a)及び(b)に示す第1の実施形態を変形したものであって、以下に記載する事項以外については基本的に第1の実施形態と同じである。
図4(a)は、本発明の第3の実施形態に係る半導体装置における電極群の平面構成を示す図である。尚、本実施形態は、図1(a)及び(b)に示す第1の実施形態を変形したものであって、以下に記載する事項以外については基本的に第1の実施形態と同じである。
図6(a)は、本発明の第4の実施形態に係る半導体装置の平面図を示している。尚、本実施形態は、図1(a)及び(b)に示す第1の実施形態の変形したものであって、以下に記載する事項以外については基本的に第1の実施形態と同じである。また、図6(a)において、図1(a)及び(b)に示す第1の実施形態と同一の構成要素には同一の符号を付している。
図7(a)は、本発明の第5の実施形態に係る半導体装置における電極群の平面構成を示す図である。尚、本実施形態は、図1(a)及び(b)に示す第1の実施形態を変形したものであって、以下に記載する事項以外については基本的に第1の実施形態と同じである。
図8(a)は、本発明の第6の実施形態に係る積層型半導体装置の断面図を示している。尚、本実施形態は、図1(a)及び(b)に示す第1の実施形態に係る半導体装置を少なくとも1つ含む複数の半導体装置を積層させた積層型半導体装置に関し、第1の実施形態と重複する記載については省略する。また、図8(a)において、説明を簡単にするために、図1(a)及び(b)に示す第1の実施形態に係る半導体装置の構成要素の一部を省略している。
図9(a)及び(b)は、本発明の第7の実施形態に係る積層型半導体装置の断面図及び平面図を示している。但し、図9(b)に示す平面図は、本実施形態の積層型半導体装置300を上面から見たときの貫通電極(電極群)の配置のみを抽出して示した図である。尚、本実施形態は、図1(a)及び(b)に示す第1の実施形態に係る半導体装置を少なくとも2つ含む複数の半導体装置を積層させた積層型半導体装置に関し、第1の実施形態と重複する記載については省略する。また、図9(a)及び(b)に示す本実施形態の積層型半導体装置300は、図8(b)に示す第6の実施形態の変形例に係る積層型半導体装置201をさらに変形させたものであり、図9(a)及び(b)において、図8(b)に示す第6の実施形態の変形例に係る積層型半導体装置201と同一の構成要素には同一の符号を付すことにより、重複する説明を省略する。
2a 第1主表面
2b 第2主表面
3 活性素子領域
4A、4B、4C 配線
5 貫通電極
6 緩衝領域
7、7A、7B、7C 電極群
8 不純物層
9 素子分離
10A、10B、10C、10D 絶縁層
11 電極パッド
12 プラグ
13 ゲート電極
14 ゲート絶縁膜
15A、15B、15C アンダーフィル
16A、16B、16C ハンダバンプ
17 ベース基板
18 活性素子形成領域
19A、19B、19C 配線層
20 ワイヤーボンディング
21A、21B、21C ビア
30、30a、30b、30c 信号貫通電極
31、31a、31b 電源貫通電極
32、32a、32b グランド貫通電極
60 真正貫通電極
61 擬似貫通電極(補助貫通電極)
100、100A、100B、100C 半導体装置(貫通電極を有する半導体装置)
101 貫通電極を有しない半導体装置
200 貫通電極を有する積層型半導体装置
201 貫通電極を有する積層型半導体装置
202 貫通電極を有する積層型半導体装置
300 貫通電極を有した積層型半導体装置
Claims (19)
- 基板を貫通する複数の貫通電極を有する半導体装置であって、
前記複数の貫通電極は、3つ以上の電極群に分けて配置されており、
前記各電極群は、二次元的に配列された3つ以上の貫通電極から構成されており、
前記基板上に形成された活性素子と前記複数の貫通電極のそれぞれとの距離のうちの最小距離と比較して、前記各電極群内における貫通電極間最小距離の方が小さいことを特徴とする半導体装置。 - 請求項1に記載の半導体装置において、
前記基板の上面及び下面の少なくとも一方の上には配線層が形成されており、
前記複数の貫通電極のうちの少なくとも1つと前記配線層とは電気的に接続されていることを特徴とする半導体装置。 - 請求項1に記載の半導体装置において、
前記基板における前記各電極群の配置領域には活性素子が形成されていないことを特徴とする半導体装置。 - 請求項1に記載の半導体装置において、
前記各電極群のうち配置面積が最小の電極群内における貫通電極間最大距離と比較して、前記各電極群間の距離のうちの最小距離の方が大きいことを特徴とする半導体装置。 - 請求項1に記載の半導体装置において、
前記各電極群のうちの少なくとも1つの電極群は、互いに異なる電位を持つ2つ以上の貫通電極を含むことを特徴とする半導体装置。 - 請求項1に記載の半導体装置において、
前記各電極群のうちの少なくとも1つの電極群は、同じ電位を持つ2つ以上の貫通電極を含むことを特徴とする半導体装置。 - 請求項6に記載の半導体装置において、
前記同じ電位を持つ2つ以上の貫通電極には同一の信号が入力されることを特徴とする半導体装置。 - 請求項6に記載の半導体装置において、
前記同じ電位を持つ2つ以上の貫通電極は同一の電源線を構成していることを特徴とする半導体装置。 - 請求項6に記載の半導体装置において、
前記同じ電位を持つ2つ以上の貫通電極のうちの1つは、当該電極群の周縁部に配置されていることを特徴とする半導体装置。 - 請求項1に記載の半導体装置において、
前記各電極群のうちの少なくとも1つの電極群は、第1の電位を持つ第1の貫通電極と、前記第1の電位に対して相補な第2の電位を持ち且つ前記第1の貫通電極と隣り合う第2の貫通電極とを含むことを特徴とする半導体装置。 - 請求項10に記載の半導体装置において、
前記第1の貫通電極は電源線を構成し、前記第2の貫通電極はグランド線を構成することを特徴とする半導体装置。 - 請求項10に記載の半導体装置において、
当該電極群は、信号が入力される第3の貫通電極をさらに含み、
前記第3の貫通電極を取り囲むように前記第1の貫通電極と前記第2の貫通電極とが交互に配置されていることを特徴とする半導体装置。 - 請求項1に記載の半導体装置において、
前記各電極群は等間隔で配置されていることを特徴とする半導体装置。 - 請求項1に記載の半導体装置において、
前記各電極群のうちの少なくとも1つの電極群は、電気的接続に用いられない疑似貫通電極を含むことを特徴とする半導体装置。 - 請求項14に記載の半導体装置において、
前記疑似貫通電極は、当該電極群の周縁部に配置されていることを特徴とする半導体装置。 - 請求項1に記載の半導体装置において、
前記各電極群のうちの少なくとも1つの電極群は、他の貫通電極の電気的接続を補助する補助貫通電極を含むことを特徴とする半導体装置。 - 請求項16に記載の半導体装置において、
前記補助貫通電極は、当該電極群の周縁部に配置されていることを特徴とする半導体装置。 - 複数の半導体装置を積層させた積層型半導体装置であって、
前記複数の半導体装置のうち少なくとも1つは、請求項1〜17のいずれか1項に記載の半導体装置であることを特徴とする積層型半導体装置。 - 複数の半導体装置を積層させた積層型半導体装置であって、
前記複数の半導体装置のうち2つ以上は、請求項1〜17のいずれか1項に記載の半導体装置であり、当該各半導体装置における前記各電極群は互いにオーバーラップしないように配置されていることを特徴とする積層型半導体装置。
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