DE602007013281D1 - Verfahren zur herstellung von öffnungen in einem substrat, insbesondere von durchgangslöchern durch ein substrat - Google Patents

Verfahren zur herstellung von öffnungen in einem substrat, insbesondere von durchgangslöchern durch ein substrat

Info

Publication number
DE602007013281D1
DE602007013281D1 DE602007013281T DE602007013281T DE602007013281D1 DE 602007013281 D1 DE602007013281 D1 DE 602007013281D1 DE 602007013281 T DE602007013281 T DE 602007013281T DE 602007013281 T DE602007013281 T DE 602007013281T DE 602007013281 D1 DE602007013281 D1 DE 602007013281D1
Authority
DE
Germany
Prior art keywords
opening
substrate
channel
masking layer
forming
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active
Application number
DE602007013281T
Other languages
English (en)
Inventor
Hoang Viet Nguyen
Martinus T Bennebroek
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NXP BV
Original Assignee
NXP BV
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NXP BV filed Critical NXP BV
Publication of DE602007013281D1 publication Critical patent/DE602007013281D1/de
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76898—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics formed through a semiconductor substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
    • H01L21/308—Chemical or electrical treatment, e.g. electrolytic etching using masks
    • H01L21/3083—Chemical or electrical treatment, e.g. electrolytic etching using masks characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/481—Internal lead connections, e.g. via connections, feedthrough structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/095—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00 with a principal constituent of the material being a combination of two or more materials provided in the groups H01L2924/013 - H01L2924/0715
    • H01L2924/097—Glass-ceramics, e.g. devitrified glass
    • H01L2924/09701—Low temperature co-fired ceramic [LTCC]
DE602007013281T 2006-12-12 2007-12-10 Verfahren zur herstellung von öffnungen in einem substrat, insbesondere von durchgangslöchern durch ein substrat Active DE602007013281D1 (de)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
EP06125914 2006-12-12
PCT/IB2007/054992 WO2008072165A1 (en) 2006-12-12 2007-12-10 Method of manufacturing openings in a substrate, a via in a substrate, and a semiconductor device comprising such a via

Publications (1)

Publication Number Publication Date
DE602007013281D1 true DE602007013281D1 (de) 2011-04-28

Family

ID=39301809

Family Applications (1)

Application Number Title Priority Date Filing Date
DE602007013281T Active DE602007013281D1 (de) 2006-12-12 2007-12-10 Verfahren zur herstellung von öffnungen in einem substrat, insbesondere von durchgangslöchern durch ein substrat

Country Status (6)

Country Link
US (1) US7927966B2 (de)
EP (1) EP2095416B1 (de)
CN (1) CN101553914B (de)
AT (1) ATE502396T1 (de)
DE (1) DE602007013281D1 (de)
WO (1) WO2008072165A1 (de)

Families Citing this family (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP4731456B2 (ja) * 2006-12-19 2011-07-27 富士通セミコンダクター株式会社 半導体装置
US8476530B2 (en) * 2009-06-22 2013-07-02 International Business Machines Corporation Self-aligned nano-scale device with parallel plate electrodes
CN102169552A (zh) * 2011-01-28 2011-08-31 上海集成电路研发中心有限公司 射频识别标签及其制造方法
KR101949981B1 (ko) * 2012-08-31 2019-02-20 에스케이하이닉스 주식회사 반도체 장치 및 그 제조 방법
US10475808B2 (en) 2017-08-30 2019-11-12 Macronix International Co., Ltd. Three dimensional memory device and method for fabricating the same
CN111405443B (zh) * 2020-03-03 2021-02-09 宁波华远电子科技有限公司 一种mems麦克风封装基板的开盖方法

Family Cites Families (18)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5352324A (en) * 1992-11-05 1994-10-04 Hitachi, Ltd. Etching method and etching apparatus therefor
TW383462B (en) 1998-05-29 2000-03-01 United Semiconductor Corp Manufacturing method for via
US6563079B1 (en) 1999-02-25 2003-05-13 Seiko Epson Corporation Method for machining work by laser beam
US6191043B1 (en) 1999-04-20 2001-02-20 Lam Research Corporation Mechanism for etching a silicon layer in a plasma processing chamber to form deep openings
US6074908A (en) 1999-05-26 2000-06-13 Taiwan Semiconductor Manufacturing Company Process for making merged integrated circuits having salicide FETS and embedded DRAM circuits
US6372634B1 (en) * 1999-06-15 2002-04-16 Cypress Semiconductor Corp. Plasma etch chemistry and method of improving etch control
US6635335B1 (en) * 1999-06-29 2003-10-21 Micron Technology, Inc. Etching methods and apparatus and substrate assemblies produced therewith
DE19946715C1 (de) * 1999-09-29 2001-05-03 Infineon Technologies Ag Verfahren zur dreidimensionalen Integration mikroelektronischer Systeme
US6737740B2 (en) 2001-02-08 2004-05-18 Micron Technology, Inc. High performance silicon contact for flip chip
NZ520369A (en) * 2002-07-22 2005-03-24 Titanox Dev Ltd A separation process for producing titanium rich powder from metal matrix composite
JP2004063556A (ja) * 2002-07-25 2004-02-26 Matsushita Electric Ind Co Ltd 半導体装置の製造方法
JP3972846B2 (ja) 2003-03-25 2007-09-05 セイコーエプソン株式会社 半導体装置の製造方法
US7361991B2 (en) 2003-09-19 2008-04-22 International Business Machines Corporation Closed air gap interconnect structure
JP2005235860A (ja) * 2004-02-17 2005-09-02 Sanyo Electric Co Ltd 半導体装置及びその製造方法
JP4688526B2 (ja) 2005-03-03 2011-05-25 Ｏｋｉセミコンダクタ株式会社 半導体装置及びその製造方法
KR20070060924A (ko) * 2005-12-09 2007-06-13 삼성전자주식회사 패럴린 마스크를 이용한 실리콘 습식 식각 방법 및 이방법을 이용한 잉크젯 프린트헤드의 노즐 플레이트 제조방법
JP2007311771A (ja) * 2006-04-21 2007-11-29 Sanyo Electric Co Ltd 半導体装置及びその製造方法
JP5371381B2 (ja) * 2008-11-05 2013-12-18 ラピスセミコンダクタ株式会社 半導体装置および半導体装置の製造方法

Also Published As

Publication number Publication date
ATE502396T1 (de) 2011-04-15
EP2095416A1 (de) 2009-09-02
EP2095416B1 (de) 2011-03-16
CN101553914B (zh) 2011-02-23
US20100059894A1 (en) 2010-03-11
WO2008072165A1 (en) 2008-06-19
US7927966B2 (en) 2011-04-19
CN101553914A (zh) 2009-10-07

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