JP5371381B2 - 半導体装置および半導体装置の製造方法 - Google Patents
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Description
D≒(Wa−Wb)/√2・・・(1)
が成立する。上記式(1)は、エッチング深さDはトレンチの開口面における径(以下開口径と称する)Waによって決まることを意味している。従って、図9に示すように、裏面コンタクト50を構成するトレンチ51の開口径Wa2と、貫通電極30を構成するトレンチ34の開口径Wa1とを異ならせることにより、互いに異なる深さのトレンチを同時に形成することが可能となる。すなわち、Wa1>Wa2となるようにマスク60の開口寸法を調節することにより、貫通電極30の形成部分においては、SOI基板10を貫通し電極パッド16に達する深さでトレンチ34を形成することができ、裏面コンタクト50の形成部分においては、シリコン基板層11内で終端する浅いトレンチ51を形成することが可能となる。
10 SOI基板
11 シリコン基板層
12 BOX層
13 SOI層
16 電極パッド
19 絶縁膜
20 センサ回路
30 貫通電極
33 めっき膜
34 トレンチ(第1のトレンチ)
40 裏面配線
41 裏面電極パッド
43 外部端子
43a 電位固定用外部端子
50 裏面コンタクト
51 トレンチ(第2のトレンチ)
Claims (15)
- 半導体基板層と表面に半導体素子および電極パッドが形成された半導体層との間に絶縁膜を有するSOI基板と、前記SOI基板を貫通し前記電極パッドに電気的に接続された貫通電極と、前記半導体基板層の表面上に絶縁膜を介して設けられて前記貫通電極に電気的に接続された外部電極と、を含む半導体装置の製造方法であって、
前記半導体基板層の表面から前記SOI基板をエッチングし、前記SOI基板を貫通し前記電極パッドに達する第1のトレンチ及び、前記半導体基板層内部で終端している第2のトレンチを形成する工程と、
前記半導体基板層の表面および前記第1および第2のトレンチの側壁および底面を覆うように絶縁膜を形成する工程と、
前記第1および第2のトレンチの底面の前記絶縁膜を除去して前記第1のトレンチの底面において前記電極パッドを露出させるとともに、前記第2のトレンチの底面において前記半導体基板層を露出させる工程と、
前記半導体基板層の表面上と前記第1および第2のトレンチの側壁および底面を覆うように導電膜を形成して前記第1のトレンチの底面において前記電極パッドに電気的に接続された前記貫通電極を形成するとともに、前記第2のトレンチの底面において前記半導体基板層に電気的に接続されたコンタクト部を形成する工程と、
前記半導体基板層の表面上の前記導電膜にパターニングを施して前記外部電極を形成するとともに前記コンタクト部に電気的に接続された電位固定用の外部電極を形成する工程と、を含むことを特徴とする半導体装置の製造方法。 - 前記第1および第2のトレンチの深さは、その開口面の径の大きさによって調整されていることを特徴とする請求項1に記載の半導体装置の製造方法。
- 前記第1のトレンチの開口面の径は、前記第2のトレンチの開口面の径よりも大きいことを特徴とする請求項2に記載の半導体装置の製造方法。
- 前記第1および第2のトレンチを形成する工程は、異方性ウェットエッチング工程を含むことを特徴とする請求項3に記載の半導体装置の製造方法。
- 前記第1および第2のトレンチを形成する工程はドライエッチング工程を含むことを特徴とする請求項3に記載の半導体装置の製造方法。
- 半導体層と半導体基板層と、前記半導体層と半導体基板層との間に形成された絶縁層とを有し、前記半導体層の表面に半導体素子及び電極パッドが形成されたSOI基板を準備する工程と、
前記半導体基板層側の表面から前記SOI基板を開口して、前記電極パッドを露出する第1のトレンチ、及び前記半導体基板層の内部で終端する第2のトレンチを形成する工程と、
前記半導体基板層の表面と、前記第1並びに第2のトレンチの底面及び側壁とを覆うように絶縁膜を形成する工程と、
前記第1及び第2のトレンチの底面に形成された前記絶縁膜を除去して、前記第1のトレンチの底面で前記電極パッドを露出させ、前記第2のトレンチの底面で前記半導体基板層を露出させる工程と、
前記第1のトレンチの内部に前記電極パッドに電気的に接続される第1の配線を形成し、前記第2のトレンチの内部に前記半導体基板層に電気的に接続される第2の配線を形成する工程と、
前記半導体基板層の表面上に前記第1の配線と電気的に接続される外部端子を形成し、前記第2の配線と電気的に接続される電位固定用外部端子を形成する工程と、
を有することを特徴とする半導体装置の製造方法。 - 半導体層と半導体基板層と、前記半導体層と半導体基板層との間に形成された絶縁層とを有し、前記半導体層の表面に半導体素子が形成されたSOI基板と、
前記半導体基板層の表面上に形成され、前記半導体基板層を貫通する第1のトレンチ内に構成された貫通電極を介して前記半導体基板層と絶縁されかつ前記半導体素子と電気的に接続された外部端子と、
前記半導体基板層の表面上に形成され、前記半導体基板層に設けられた第2のトレンチを介して前記半導体基板層と電気的に接続された電位固定用外部端子と、
を有し、
前記第1のトレンチ及び前記第2のトレンチの内壁面が平滑面であることを特徴とする半導体装置。 - 半導体基板層と表面に半導体素子および電極パッドが形成された半導体層との間に絶縁膜を有するSOI基板と、前記半導体基板層表面から前記SOI基板を貫通した第1のトレンチ内に構成されて前記電極パッドに電気的に接続された貫通電極と、前記半導体基板層の表面上に絶縁膜を介して設けられて前記貫通電極に電気的に接続された外部端子と、を含む半導体装置であって、
前記半導体基板層の表面に開口面を有し且つ前記半導体基板層の内部で終端している第2のトレンチの底面において前記半導体基板層に電気的に接続された導電膜を含むコンタクト部と、
前記半導体基板層の表面上に前記絶縁膜を介して設けられて前記コンタクト部に電気的に接続された電位固定用電極と、を含み、
前記第1のトレンチ及び前記第2のトレンチの内壁面が平滑面であることを特徴とする半導体装置。 - 前記半導体基板層と前記コンタクト部との間の電気的接続はショットキーコンタクトであることを特徴とする請求項8に記載の半導体装置。
- 前記半導体基板層はシリコン単結晶からなり、前記トレンチは前記半導体基板層をウェットエッチングにより表出したシリコン単結晶の(111)結晶面からなる側壁を有することを特徴とする請求項8に記載の半導体装置。
- 前記コンタクト部は、前記貫通電極に電気的に接続されていることを特徴とする請求項8乃至10のいずれか1つに記載の半導体装置。
- 前記半導体基板層の表面には前記絶縁膜を介して前記貫通電極と前記外部端子とを繋ぐ裏面配線が設けられ、前記コンタクト部は前記裏面配線上に設けられていることを特徴とする請求項8乃至10のいずれか1つに記載の半導体装置。
- 前記コンタクト部は前記電位固定用電極の直下に設けられていることを特徴とする請求項8乃至10のいずれか1つに記載の半導体装置。
- 前記半導体素子は受光素子を含み、
前記SOI基板の上に、前記受光素子を覆うように設けられた光透過性の支持基板を更に有することを特徴とする請求項8乃至13のいずれか1つに記載の半導体装置。 - 複数の前記SOI基板の各々はその厚み方向に積層され、前記外部端子を介して積層方向に互いに電気的に接続されていることを特徴とする請求項8に記載の半導体装置。
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