CN108417541B - 半导体封装 - Google Patents

半导体封装 Download PDF

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Publication number
CN108417541B
CN108417541B CN201710692396.4A CN201710692396A CN108417541B CN 108417541 B CN108417541 B CN 108417541B CN 201710692396 A CN201710692396 A CN 201710692396A CN 108417541 B CN108417541 B CN 108417541B
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heat dissipation
dissipation structure
substrate
semiconductor chip
semiconductor package
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CN108417541A (zh
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胡逸群
何佳容
杨金凤
洪志斌
杨秉丰
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Advanced Semiconductor Engineering Inc
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Advanced Semiconductor Engineering Inc
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Abstract

一种半导体封装包含衬底、半导体芯片和散热结构。所述半导体芯片包含第一表面、与所述第一表面相对的第二表面，以及安置为邻近于所述第一表面的至少一个芯片垫。所述芯片垫电连接到所述衬底。所述散热结构安置为邻近于所述半导体芯片的所述第二表面以及所述衬底的一部分。所述散热结构的面积大于所述半导体芯片的面积。

Description

半导体封装
技术领域
本发明涉及一种半导体封装，且更明确地说，涉及一种包含散热结构的半导体封装。
背景技术
半导体封装的设计包含高速数据传输、高容量和小尺寸。散热也是此类半导体封装的一个问题。在操作期间，高速数据传输可导致产生大量的热量，且可使半导体封装的温度升高。归因于半导体封装的小尺寸，可能难以耗散所述热量。如果热量未被高效地耗散，那么半导体封装的性能可能降低，或半导体封装可能损坏或变得不工作。
发明内容
在根据一些实施例的方面中，一种半导体封装包含衬底、半导体芯片和散热结构。所述半导体芯片包含第一表面、与所述第一表面相对的第二表面，以及安置为邻近于所述第一表面的至少一个芯片垫。所述芯片垫电连接到所述衬底。所述散热结构安置为邻近于所述半导体芯片的所述第二表面以及所述衬底的一部分。所述散热结构具有第一面积，且所述半导体芯片具有第二面积，且所述第一面积与所述第二面积的比率大于约1.17。
在根据一些实施例的另一方面中，一种半导体封装包含衬底、半导体芯片和散热结构。所述半导体芯片包含第一表面、与所述第一表面相对的第二表面、在所述第一表面与所述第二表面之间延伸的至少一个侧表面，以及安置为邻近于所述第一表面的至少一个芯片垫。所述芯片垫电连接到所述衬底。所述散热结构覆盖所述半导体芯片的所述第二表面和所述侧表面，以及所述衬底的一部分。所述散热结构的面积大于所述半导体芯片的面积。
在根据一些实施例的另一方面中，一种半导体封装包含衬底、半导体芯片和散热结构。所述半导体芯片包含第一表面、与所述第一表面相对的第二表面，以及安置为邻近于所述第一表面的至少一个芯片垫。所述芯片垫电连接到所述衬底。所述散热结构安置于所述半导体芯片的所述第二表面与所述衬底之间。所述散热结构的面积大于所述半导体芯片的面积。
附图说明
图1说明根据本发明的一些实施例的半导体封装的横截面视图的实例。
图2说明根据本发明的一些实施例的图1中所示的半导体封装的俯视图。
图3说明根据本发明的一些实施例的图1中所示的半导体封装的散热结构的横截面视图的实例。
图4说明根据本发明的一些实施例的半导体封装的热性能评估。
图5说明根据本发明的一些实施例的半导体封装的俯视图的实例。
图6说明根据本发明的一些实施例的半导体封装的俯视图的实例。
图7说明根据本发明的一些实施例的半导体封装的横截面视图的实例。
图8说明根据本发明的一些实施例的半导体封装的横截面视图的实例。
图9说明根据本发明的一些实施例的半导体封装的横截面视图的实例。
图10说明根据本发明的一些实施例的半导体封装的横截面视图的实例。
图11说明根据本发明的一些实施例的半导体封装的横截面视图的实例。
图12说明根据本发明的一些实施例的半导体封装的横截面视图的实例。
图13说明根据本发明的一些实施例的半导体封装的横截面视图的实例。
图14说明根据本发明的一些实施例的半导体封装的横截面视图的实例。
图15说明根据本发明的一些实施例的图14中所示的半导体封装的俯视图。
图16说明根据本发明的一些实施例的半导体封装的横截面视图的实例。
图17说明根据本发明的一些实施例的半导体封装的横截面视图的实例。
图18说明根据本发明的一些实施例的半导体封装的横截面视图的实例。
图19说明根据本发明的一些实施例的半导体封装的横截面视图的实例。
图20说明根据本发明的一些实施例的半导体封装的横截面视图的实例。
图21说明根据本发明的一些实施例的半导体封装的横截面视图的实例。
图22说明根据本发明的一些实施例的半导体封装的横截面视图的实例。
图23说明根据本发明的一些实施例的半导体制造工艺。
图24和图25说明根据本发明的一些实施例的半导体制造工艺。
具体实施方式
本发明描述根据一些实施例的一种改进的半导体封装，以及用于制造所述半导体封装的改进的技术。在一些实施例中，所述半导体封装包含散热结构。根据一些实施例的本发明的半导体封装和技术例如适合有效地耗散半导体封装中的半导体芯片所产生的热量。
一般来说，通常通过附接到半导体封装的模制化合物(molding compound)的金属板或其它散热片(例如不锈钢板或铝合金板)来实现散热。所述半导体封装中的半导体芯片所产生的热量通过所述金属板的传导性来耗散。所述金属板与所述模制化合物共形，因此，此类散热的效率较差。为了解决这些问题，可使用多鳍片型散热片。多鳍片型散热片被设计成具有多个表面来耗散热量。然而，鳍片型散热片的散热效率仍然较差。另外，难以减小鳍片型散热片的大小。另外，可使用包含多热通孔(multi-thermal vias)的另一解决方案。然而，应设计新的耗散路径，且包含热通孔的耗散路径将占用较大的布局面积(areas oflayout)。另外，包含高热化合物(high thermal compound)的其它解决方案可用于所述模制化合物。然而，此类散热技术的效率受到限制，且高热化合物中过多的添加剂将导致对半导体芯片的较差保护。
为了解决至少上述问题，本发明描述一种根据一些实施例的改进的半导体封装。所述半导体封装包含安置为邻近于半导体芯片的表面和衬底的一部分的散热结构。所述散热结构具有第一面积，且所述半导体芯片具有第二面积，且所述第一面积与所述第二面积的比率可大于约1.17。因此，散热面积得以增加。此外，所述散热结构可包含具有高导热性的石墨层。因此，可实现高效率的散热。此外，所述半导体封装的大小可有效地减小。
在根据一些实施例的倒装芯片封装中，散热结构覆盖半导体芯片的背表面(backside surface)和一侧表面，以及衬底的一部分。在根据一些实施例的线接合封装中，散热结构安置于半导体芯片的背表面与衬底之间。此类配置可显著增加散热面积，且可将半导体芯片所产生的热量快速地耗散到所述衬底。
图1说明根据本发明的一些实施例的半导体封装1的横截面视图的实例。半导体封装1是倒装芯片封装的实例。半导体封装1包含衬底12、半导体芯片14、散热结构16和底填充料18。
衬底12可为封装衬底，且包含第一表面121、与第一表面121相对的第二表面122、至少一个衬底垫123，以及在第一表面121与第二表面122之间延伸的至少一个侧表面124。衬底12的材料可为有机材料、硅或玻璃。应注意，衬底12可为内插件(interposer)。第一经图案化的电路层可安置为邻近于第一表面121，且包含衬底垫123的第二经图案化的电路层可安置为邻近于第二表面122，且电连接到所述第一经图案化的电路层。多个外部连接件可安置于第一表面121上，且电连接到所述第一经图案化的电路层。
半导体芯片14包含第一表面141、与第一表面141相对的第二表面142、安置为邻近于第一表面141的至少一个芯片垫143、在第一表面141与第二表面142之间延伸的侧表面144，以及电连接到芯片垫143的至少一个传导元件145。第一表面141是半导体芯片14的作用表面(active surface)，且面向衬底12的第二表面122。第二表面142是半导体芯片14的背表面。传导元件145(例如金属柱、微凸块或焊球)附接到并电连接到衬底12的第二表面122上的第二经图案化的电路层的衬底垫123。因此，半导体芯片14的芯片垫143借助于倒装芯片接合，通过传导元件145电连接到衬底12。就是说，半导体封装1是倒装芯片封装。应注意，仅说明单个半导体芯片14；然而，本发明不限于单芯片封装。就是说，半导体封装1可包含多个半导体芯片14。
底填充料18安置于衬底12的第二表面122与半导体芯片14的第一表面141之间，以环绕并保护传导元件145。
散热结构16安置为邻近于半导体芯片14的第二表面142以及衬底12的一部分。如图1中所示，散热结构16覆盖并接触半导体芯片14的第二表面142和四个侧表面144、底填充料18的四个侧表面184，以及衬底12的第二表面122的一部分。因此，散热结构16的一部分与半导体芯片14共形。在一或多个实施例中，散热结构16的一侧表面164可与衬底12的侧表面124共面。散热结构16的拐点线(corner line)165位于安置于衬底12的第二表面122上的散热结构16的一部分与安置于半导体芯片14的侧表面144和底填充料18的侧表面184上的散热结构16的一部分之间。
图2说明根据本发明的一些实施例的图1中所示的半导体封装1的俯视图。散热结构16的面积大于半导体芯片14的面积。在一或多个实施例中，整个散热结构16从俯视图看具有第一面积，且整个半导体芯片14从俯视图看具有第二面积。第一面积与第二面积的比率可大于约1.17。在一或多个实施例中，第一面积与第二面积的比率可在约1.17到约7的范围内，例如第一面积与第二面积的比率可在约1.4到约6的范围内，或在约2到约5的范围内。
另外，安置于衬底12的第二表面122上的散热结构16的一部分包含四个分部部分166和四个界面167。分部部分166彼此分离，且所述分部部分166中的每一者对应于半导体芯片14的相应侧表面144。分部部分166中的每一者具有两个内侧表面1661。因此，分部部分166中的每一者由两个内侧表面1661、一个侧表面164和一个拐点线165所界定，且形状可为梯形。如图2中所示，两个相邻分部部分166的两个内侧表面1661可彼此接触，从而形成界面167。界面167中的每一者从半导体芯片14的拐点(corner)大体上向外延伸到散热结构16的拐点(或衬底12的拐点)。
在一些实施例中(例如如图1和2中所示)，散热结构16的面积大于半导体芯片14的面积，因此，散热结构16的一部分延伸到衬底12的第二表面122。此类配置可显著增加散热面积，且可将半导体芯片14产生的热量快速地耗散到衬底12。因此，可实现高效率的散热。此外，可高效地减小半导体封装1的大小。
图3说明根据本发明的一些实施例的半导体封装1的散热结构16的横截面视图的实例。散热结构16可包含粘附层161、石墨层162和保护层163。使用粘附层161来粘附散热结构16，以接触半导体芯片14的第二表面142和侧表面144、底填充料18的侧表面184，以及衬底12的第二表面122的一部分。粘附层161的材料可为具有低热阻的胶带，且粘附层161的厚度可为约10微米(μm)。
石墨层162安置于保护层163与粘附层161之间。石墨层162的材料可为热解石墨(pyrolytic graphite)(例如通过热解(pyrolysis)形成)以作为热散播器(heatspreader)，其具有在水平方向上在约1400瓦每米开尔文(W/mK)到约2000W/mK的范围内的导热性，且在垂直方向上在约5W/mK到约20W/mK的范围内的导热性。石墨层162的厚度可为约10μm到约40μm。保护层163安置于石墨层162上，用于保护和绝缘。保护层163的材料可为聚合物例如聚酰亚胺(PI)，且保护层163的厚度可为约10μm。由于散热结构16可包含具有高导热性的石墨层162，因此可实现高效率的散热。另外，粘附层161是柔性的，使得石墨层162可平顺且均匀地附接到半导体芯片14的第二表面142和侧表面144、底填充料18的侧表面184，以及衬底12的第二表面122的一部分。另一具有高导热性的含碳材料(carbonaceousmaterial)可代替或结合石墨层162中的石墨。
图4说明根据本发明的一些实施例的半导体封装的热性能评估。在一些实施例中，半导体封装的条件是：功率为3.5瓦(W)；衬底12的大小是13毫米(mm)乘13mm乘0.36mm；且半导体芯片14的大小是5.08mm乘5.08mm乘0.36mm。图4的水平轴是从俯视图看的散热结构16的第一面积与从俯视图看的半导体芯片14的第二面积的面积比。图4的垂直轴线是降低温度百分比(reduced temperature percentage)(％)，其由(Tr-T0)/T0定义，其中T0是在不使用任何散热结构16的情况下，半导体芯片14的第二表面142的温度，且Tr是当将散热结构16覆盖在半导体芯片14上时，半导体芯片14的第二表面142的温度。如图4中所展示，在一些实施例中，当面积比是1时，散热结构16的面积等于半导体芯片14的面积(例如散热结构16仅覆盖半导体芯片14)，且降低温度百分比(％)为零。举例来说，散热结构16并不展现任何散热效应。
此外，在一些实施例中，当面积比为1.17时，散热结构16的面积大于半导体芯片14的面积(例如散热结构16覆盖半导体芯片14，并且还延伸到衬底12的第二表面122)，降低温度百分比(％)约为3％。举例来说，散热结构16展现显著的耗散效应，其产生显著的温差(例如3.19摄氏度(℃))。此外，在一些实施例中，当面积比在约1.4到约6的范围内时，散热结构16可精确地覆盖半导体芯片14，且降低温度百分比(％)在约8％到约21％的范围内。然而，如图4中所示，当面积比大于约4或约5时，降低温度百分比(％)的增加速率不是那么突出，例如，曲线趋向于水平。因此，在一些实施例中，可采用在约2到约5的范围内的面积比，使得散热结构16可高效地使用。
图5说明根据本发明的一些实施例的半导体封装1a的俯视图的实例。图5的半导体封装1a类似于如图2中示出的半导体封装1，不同之处在于散热结构16a的结构。散热结构16a是条带类型，且散热结构16a的宽度大体上等于半导体芯片14的宽度。因此，散热结构16a覆盖并接触半导体芯片14的第二表面142和侧表面144、底填充料18的侧表面184，以及衬底12的第二表面122的一部分。如图5中所示，散热结构16a从衬底12的左侧表面124延伸到衬底12的右侧表面124，使得衬底12的第二表面122的上部1221和下部1222(例如在图5中所示的定向中)未被覆盖并暴露。
图6说明根据本发明的一些实施例的半导体封装1b的俯视图的实例。图6的半导体封装1b类似于如图5中所示的半导体封装1a，不同之处在于散热结构16b的结构。散热结构16b是跨越类型，且延伸衬底12的四个侧表面124，使得衬底12的第二表面122的四个拐点部分1223(例如在图6中所示的定向中)未被覆盖并暴露。
图7说明根据本发明的一些实施例的半导体封装1c的横截面视图的实例。图7的半导体封装1c类似于如图1中所示的半导体封装1，不同之处在于衬底12进一步包含多个热通孔125。热通孔125的材料可为导电材料，例如金属。热通孔125中的每一者延伸贯穿(extends through)衬底12，并接触散热结构16，以便将散热结构16中的热量耗散到衬底12的第一表面121中。
图8说明根据本发明的一些实施例的半导体封装1d的横截面视图的实例。图8的半导体封装1d类似于如图1中所示的半导体封装1，不同之处在于进一步包含包封物(encapsulant)20(例如模制化合物(molding compound))。包封物20接触并覆盖散热结构16，以便保护半导体芯片14和散热结构16。此外，如图8中示出，散热结构16并不覆盖衬底12的整个第二表面122，因此，包封物20进一步覆盖衬底12的第二表面122的一部分。应注意，在一些实施例中(例如如图8中所示)，散热结构16的保护层163可省略，即，散热结构16可包含粘附层161和石墨层162。
图9说明根据本发明的一些实施例的半导体封装1e的横截面视图的实例。图9的半导体封装1e类似于如图1中所示的半导体封装1，不同之处在于进一步包含封盖(lid)22。封盖22覆盖散热结构16。举例来说，半导体芯片14和散热结构16容纳在由封盖22的壁所界定的空间中，使得半导体芯片14和散热结构16受到保护。此外，如图9中所示，散热结构16并不覆盖衬底12的整个第二表面122，因此，封盖22的底部可附接到衬底12的第二表面122。应注意，在一些实施例中(例如如图9中所示)，散热结构16的保护层163可省略，即，散热结构16可包含粘附层161和石墨层162。
图10说明根据本发明的一些实施例的半导体封装1f的横截面视图的实例。图10的半导体封装1f类似于如图8中示出的半导体封装1d，不同之处在于散热结构16的位置。包封物20a覆盖并接触半导体芯片14的四个侧表面144、底填充料18的四个侧表面184，以及衬底12的第二表面122的一部分。包封物20a包含第一表面201和第二表面202。包封物20a的第一表面201接触衬底12的第二表面122。包封物20a的第二表面202与半导体芯片14的第二表面142共面。举例来说，半导体芯片14的第二表面142从包封物20a暴露。散热结构16c是平坦板，且安置于包封物20a的第二表面202和半导体芯片14的第二表面142上并覆盖所述表面。应注意，在一些实施例中(例如如图10中所示)，散热结构16c的粘附层161可省略，即，散热结构16c可包含保护层163和石墨层162。石墨层162可直接附接到包封物20a的第二表面202。
图11说明根据本发明的一些实施例的半导体封装1g的横截面视图的实例。图11的半导体封装1g类似于如图10中所示的半导体封装1f，不同之处在于进一步包含中间散热结构(intermediate heat dissipation structure)17。中间散热结构17位于包封物20a的第一表面201与衬底12的第二表面122之间。中间散热结构17界定至少一个开口171，其在半导体芯片14下方或与之对准，且从俯视图看，开口171的大小小于半导体芯片14的大小。半导体芯片14的芯片垫143和衬底12的衬底垫123安置在对应于中间散热结构17的开口171或与之对准的位置处，使得传导元件145可安置在中间散热结构17的开口171中。应注意，在一些实施例中(例如如图11中所示)，中间散热结构17类似于散热结构16c，且两者均用于散热。然而，中间散热结构17可包含粘附层和石墨层。举例来说，保护层可省略。
图12说明根据本发明的一些实施例的半导体封装1h的横截面视图的实例。图12的半导体封装1h类似于如图11中示出的半导体封装1g，不同之处在于散热结构16c，且包封物20a省略。应注意，在一些实施例中(例如如图12中所示)，中间散热结构17可包含三个层(例如粘附层、石墨层和保护层)。
图13说明根据本发明的一些实施例的半导体封装1j的横截面视图的实例。图13的半导体封装1j类似于如图1中所示的半导体封装1，不同之处在于进一步包含中间散热结构17。中间散热结构17位于散热结构16与衬底12的第二表面122之间。举例来说，散热结构16覆盖并接触中间散热结构17。中间散热结构17界定至少一个开口171，其在半导体芯片14下方或与之对准，且从俯视图看，开口171的大小小于半导体芯片14的大小。半导体芯片14的芯片垫143和衬底12的衬底垫123安置在对应于中间散热结构17的开口171或与之对准的位置处，使得传导元件145可安置在中间散热结构17的开口171中。应注意，在一些实施例中(例如如图13中所示)，中间散热结构17类似于散热结构16，且两者均用于散热。然而，中间散热结构17可包含粘附层和石墨层。举例来说，保护层可省略。
图14说明根据本发明的一些实施例的半导体封装1k的横截面视图的实例。半导体封装1k是线接合封装的实例。半导体封装1k包含衬底12、半导体芯片14、散热结构16d和至少一个接合线24。
图14的衬底12类似于图1的衬底12，不同之处在于衬底垫123的位置。图14的半导体芯片14类似于图1的半导体芯片14，不同之处在于芯片垫143的位置，且传导元件145省略。第一表面141是半导体芯片14的作用表面。第二表面142是半导体芯片14的背表面，且面向衬底12的第二表面122。接合线24将半导体芯片14的芯片垫143与衬底12的衬底垫123电连接。因此，半导体芯片14的芯片垫143通过接合线24电连接到衬底12。
散热结构16d安置于半导体芯片14的第二表面142与衬底12的第二表面122之间。散热结构16d类似于散热结构16，且可包含粘附层161、石墨层162和保护层163(例如如图3中示出)，其中石墨层162安置于保护层163与粘附层161之间，且粘附层161接触衬底12。然而，在一些实施例中，散热结构16d可包含粘附层161和石墨层162。如图14中所示，半导体芯片14的第二表面142通过粘附层19粘附到散热结构16d。此外，散热结构16d界定至少一个开口168，以暴露衬底12的一部分(例如衬底垫123)，且接合线24穿过散热结构16d的开口168。
图15说明根据本发明的一些实施例的图14中所示的半导体封装1k的俯视图。散热结构16d的面积大于半导体芯片14的面积。散热结构16d界定至少两个开口168，且两个相邻开口168之间的间隙G大于约1mm，约2mm或约3mm。另外，开口168中的每一者可暴露衬底12的至少两行衬底垫123。
图16说明根据本发明的一些实施例的半导体封装1m的横截面视图的实例。图16的半导体封装1m类似于如图14中所示的半导体封装1k，不同之处在于进一步包含包封物20b(例如模制化合物)。包封物20b接触并覆盖半导体芯片14、接合线24和散热结构16d，以便保护半导体芯片14、接合线24和散热结构16d。此外，如图16中所示，散热结构16d并不覆盖衬底12的整个第二表面122，因此，包封物20b进一步覆盖衬底12的第二表面122的一部分。应注意，在一些实施例中(例如如图16中所示)，散热结构16d的保护层可省略，即，散热结构16d可包含粘附层和石墨层。
图17说明根据本发明的一些实施例的半导体封装1n的横截面视图的实例。图17的半导体封装1n类似于如图14中所示的半导体封装1k，不同之处在于衬底12进一步包含多个热通孔125。热通孔125的材料可为导电材料，例如金属。热通孔125中的每一者延伸穿过衬底12，并接触散热结构16d，以便将散热结构16d中的热量耗散到衬底12的第一表面121。
图18说明根据本发明的一些实施例的半导体封装1p的横截面视图的实例。图18的半导体封装1p类似于如图14中所示的半导体封装1k，不同之处在于进一步包含包封物20c和第二包封物20d。第一包封物20c覆盖并接触接合线24、在接合线24下面的散热结构16d的一部分，以及在接合线24下面的半导体芯片14的一部分，以用于绝缘。第一包封物20c可为具有约0.9W/mK的导热性的模制化合物，且可通过转移模制(transfer molding)或施配(dispensing)来形成。第二包封物20d覆盖并接触第一包封物20c、半导体芯片14和散热结构16d以用于散热。第二包封物20d可为具有约10.0W/mK的导热性的模制化合物，且可通过转移模制形成。举例来说，第二包封物20d的导热性可为第一包封物20c的导热性的约5倍或约10倍。
图19说明根据本发明的一些实施例的半导体封装1q的横截面视图的实例。图19的半导体封装1q类似于如图18中所示的半导体封装1p，不同之处在于包封物20e覆盖并接触接合线24。举例来说，第一包封物20e并不接触散热结构16d和半导体芯片14。第一包封物20e可为具有约0.9W/mK的导热性的模制化合物，且通过喷射(jetting)或浸渍(steep)形成。接合线24上的第一包封物20e的厚度可大体上一致或均匀。第二包封物20d覆盖并接触第一包封物20e、半导体芯片14和散热结构16d，以用于散热。第二包封物20d的导热性可为第一包封物20e的导热性约5倍或约10倍。
图20说明根据本发明的一些实施例的半导体封装1r的横截面视图的实例。半导体封装1r是腔向下(cavity down)球栅阵列(BGA)封装的实例。半导体封装1r包含衬底12a、半导体芯片14、散热结构16e、至少一个接合线24、包封物20f和载体26。
图20的衬底12a类似于图14的衬底12，不同之处在于衬底12a进一步界定延伸贯穿衬底12a的穿透孔126，且衬底垫123可安置通孔126周围。散热结构16e安置于衬底12a的第一表面121上。散热结构16e是平坦板，且可包含粘附层和石墨层，其中所述石墨层安置于所述粘附层上。
载体26(例如玻璃)附接到散热结构16e的粘附层。图20的半导体芯片14类似于图14的半导体芯片14。半导体芯片14安置在由衬底12a的通孔126和散热结构16e所界定的腔中。第一表面141是半导体芯片14的作用表面。第二表面142是半导体芯片14的背表面，且粘附到散热结构16e(例如散热结构16e的石墨层)。接合线24将半导体芯片14的芯片垫143与衬底12a的衬底垫123电连接。因此，半导体芯片14的芯片垫143通过接合线24电连接到衬底12a。
包封物20f(例如模制化合物)填充由衬底12a的通孔126和散热结构16e所界定的腔，并延伸到衬底12a的第二表面122。如图20中所示，包封物20f接触并覆盖半导体芯片14、接合线24以及散热结构16e的一部分，以便保护半导体芯片14、接合线24和散热结构16e。另外，多个外部连接件28可安置于衬底12a的第二表面122上，以用于外部连接。
图21说明根据本发明的一些实施例的半导体封装1s的横截面视图的实例。图21的半导体封装1s类似于如图1中所示的半导体封装1，不同之处在于衬底12进一步包含腔127。衬底垫123暴露在腔127中，且半导体芯片14安置在腔127中。半导体芯片14的芯片垫143借助于倒装芯片接合，通过传导元件145电连接到衬底12。底填充料18安置于腔127的底表面与半导体芯片14的第一表面141之间，以环绕并保护传导元件145。半导体芯片14的第二表面142与衬底12的第二表面122大体上共面。散热结构16覆盖并接触半导体芯片14的第二表面142以及衬底12的第二表面122。
图22说明根据本发明的一些实施例的半导体封装1t的横截面视图的实例。图22的半导体封装1t类似于如图21中所示的半导体封装1s，不同之处在于衬底12并不包含腔127，且半导体芯片14和传导元件145嵌入于衬底12中。
图23说明根据本发明的一些实施例的半导体制造工艺。在一些实施例中，所述半导体制造工艺用以制造半导体封装，例如如图1和2中示出的半导体封装1。参看图23，提供衬底12、半导体芯片14和散热结构16。衬底12可为封装衬底，且包含第一表面121、与第一表面121相对的第二表面122、至少一个衬底垫123，以及在第一表面121与第二表面122之间延伸的至少一个侧表面124，如图1中所示。衬底12的材料可为有机材料、硅或玻璃。应注意，衬底12可为内插件。
半导体芯片14包含第一表面141、与第一表面141相对的第二表面142、安置为邻近于第一表面141的至少一个芯片垫143、在第一表面141与第二表面142之间延伸的侧表面144，以及电连接到芯片垫143的至少一个传导元件145，如图1中所示。第一表面141是半导体芯片14的作用表面，且面向衬底12的第二表面122。第二表面142是半导体芯片14的背表面。传导元件145(例如金属柱、微凸块或焊球)附接到和电连接到衬底12的衬底垫123。因此，半导体芯片14借助于倒装芯片接合，通过传导元件145电连接到衬底12。底填充料18可安置于衬底12的第二表面122与半导体芯片14的第一表面141之间，以环绕并保护传导元件145。
散热结构16是平坦板，包含主要部分160、四个分部部分166，且界定四个凹口169。散热结构16的面积大于半导体芯片14的面积。主要部分160对应于半导体芯片14的第二表面142，或与之对准。分部部分166彼此分离，并连接到主要部分160。分部部分166中的每一者具有两个内侧表面1661。因此，分部部分166中的每一者由两个内侧表面1661、主要部分160和一个侧表面164所界定，且形状可为梯形。如图23中所示，两个相邻分部部分166的两个内侧表面1661可界定凹口169。凹口169中的每一者从主要部分160的拐点大体上向外延伸到散热结构16的拐点。
接着，将散热结构16附接到半导体芯片14的第二表面142和衬底12的一部分，以便获得如图1和2中示出的半导体封装1。散热结构16覆盖并接触半导体芯片14的第二表面142和四个侧表面144、底填充料18的四个侧表面184，以及衬底12的第二表面122的一部分。因此，散热结构16的一部分与半导体芯片14共形。在一或多个实施例中，散热结构16的灵活性(flexibility)以及凹口169的设计可促进散热结构16的附接过程。因此，散热结构16可平顺且均匀地附接到半导体芯片14的第二表面142和侧表面144、底填充料18的侧表面184，以及衬底12的第二表面122的一部分。在附接之后，如图2中示出，两个相邻分部部分166的两个内侧表面1661可彼此接触，从而形成界面167。因此，凹口169可消失。
图24和25说明根据本发明的一些实施例的半导体制造工艺。在一些实施例中，所述半导体制造工艺用以制造半导体封装，例如如图14和15中示出的半导体封装1k。参看图24，提供衬底12和散热结构16d。衬底12可为封装衬底，且包含第一表面121、与第一表面121相对的第二表面122、至少一个衬底垫123，以及在第一表面121与第二表面122之间延伸的至少一个侧表面124，如图14中示出。散热结构16d是平坦板，包含主要部分160，且界定四个开口168。主要部分160对应于半导体芯片14的第二表面142，或与之对准。开口168环绕主要部分160，且彼此不连通。
参看图25，散热结构16d附接到衬底12的第二表面122。衬底12的一部分(例如衬底垫123)从开口168暴露。接着，如图14中示出的半导体芯片14的第二表面142附接到散热结构16d的主要部分160。接着，至少一个接合线24将半导体芯片14的芯片垫143与衬底12的衬底垫123电连接。因此，半导体芯片14的芯片垫143通过接合线24电连接到衬底12，且接合线24穿过散热结构16d的开口168。因此，获得如图14和15中示出的半导体封装1k。
除非另外规定，否则例如“上方”、“下方”、“向上”、“左”、“右”、“向下”、“顶部”、“底部”、“垂直”、“水平”、“侧”、“较高”、“下部”、“上部”、“上面”、“下面”等空间描述是相对于图中所示的定向加以指示。应理解，本文中所使用的空间描述仅是出于说明的目的，且本文中所描述的结构的实际实施方案可以任何定向或方式在空间上布置，前提是不会因为此布置而偏离本发明的实施例的优点。
如本文所用，除非上下文另外明确规定，否则单数术语“一(a/an)”和“所述(the)”包括多个参考物。
如本文中所使用，术语“大致”、“大体上”、“实质”和“约”用以描述和考虑小的变化。当与事件或情形结合使用时，所述术语可指其中事件或情形明确发生的情况以及其中事件或情形极接近于发生的情况。举例来说，当结合数值使用时，术语可指代小于或等于所述数值的±10％的变化范围，例如小于或等于±5％、小于或等于±4％、小于或等于±3％、小于或等于±2％、小于或等于±1％、小于或等于±0.5％、小于或等于±0.1％、或小于或等于±0.05％。对于另一实例，如果数值之间的差小于或等于所述值的平均值的±10％(例如小于或等于±5％、小于或等于±4％、小于或等于±3％、小于或等于±2％、小于或等于±1％、小于或等于±0.5％、小于或等于±0.1％、或小于或等于±0.05％)，那么可认为所述两个数值“大体上”相同。术语“大体上共面”可指两个表面在数微米内处于沿同一平面，例如在40μm内、30μm内、20μm内、10μm内或1μm内处于沿同一平面。
另外，有时在本文中按范围格式呈现量、比率和其它数值。应理解，此类范围格式是用于便利和简洁起见，且应灵活地理解，不仅包含明确地指定为范围限制的数值，而且包含涵盖于所述范围内的所有个别数值或子范围，如同明确地指定每一数值和子范围一般。
虽然已参考本发明的特定实施例描述并说明了本发明，但这些描述和说明并不限制本发明。所属领域的技术人员应理解，可在不脱离如由所附权利要求书界定的本发明的真实精神和范围的情况下，作出各种改变且取代等效物。所述说明可能未必按比例绘制。归因于制造工艺和容差，本发明中的艺术再现与实际设备之间可存在区别。可存在并未特定说明的本发明的其它实施例。应将本说明书和图式视为说明性的而非限制性的。可做出修改，以使具体情况、材料、物质组成、方法或工艺适应于本发明的目标、精神和范围。所有所述修改都既定在所附权利要求书的范围内。虽然本文中所揭示的方法已参考按特定次序执行的特定操作加以描述，但应理解，可在不脱离本发明的教示的情况下组合、细分或重新排序这些操作以形成等效方法。因此，除非本文中特别指示，否则操作的次序和分组并非本发明的限制。

Claims (7)

1.一种半导体封装，其包括：
衬底；
半导体芯片，其包含第一表面、与所述第一表面相对的第二表面、安置于所述第一表面的至少一个芯片垫、在所述第一表面与所述第二表面之间延伸的侧表面，以及电连接到所述芯片垫的至少一个传导元件，其中所述芯片垫通过所述传导元件电连接到所述衬底；
第一散热结构，位于所述半导体芯片的所述第一表面的与衬底之间，其中所述第一散热结构界定至少一个开口，所述开口在所述半导体芯片下方，所述开口的大小小于所述半导体芯片的大小，且所述传导元件安置在所述开口中；以及
第二散热结构，其安置于所述半导体芯片的所述第二表面以及所述第一散热结构上，其中所述第二散热结构接触所述半导体芯片的所述第二表面及所述侧表面，以及接触所述第一散热结构，所述第二散热结构具有第一面积，所述半导体芯片具有第二面积，且所述第一面积与所述第二面积的比率大于1.17。
2.根据权利要求1所述的半导体封装，其中所述第二散热结构包含石墨层。
3.根据权利要求1所述的半导体封装，其中所述第一面积与所述第二面积的所述比率在1.17到7的范围内。
4.根据权利要求3所述的半导体封装，其中所述第一面积与所述第二面积的所述比率在1.4到6的范围内。
5.根据权利要求3所述的半导体封装，其中所述第一面积与所述第二面积的所述比率在2到5的范围内。
6.根据权利要求2所述的半导体封装，其中所述石墨层具有在水平方向上在1400瓦每米开尔文(W/mK)到2000W/mK的范围内的导热性，且在垂直方向上在5W/mK到20W/mK的范围内的导热性。
7.根据权利要求2所述的半导体封装，其中所述第二散热结构进一步包含保护层，所述保护层安置于所述石墨层上。
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