CN111081649A - 半导体封装 - Google Patents

半导体封装 Download PDF

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CN111081649A
CN111081649A CN201910770237.0A CN201910770237A CN111081649A CN 111081649 A CN111081649 A CN 111081649A CN 201910770237 A CN201910770237 A CN 201910770237A CN 111081649 A CN111081649 A CN 111081649A
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chip
semiconductor package
heat spreader
logic chip
memory chip
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张爱妮
白承德
金泰宪
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Samsung Electronics Co Ltd
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Samsung Electronics Co Ltd
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Abstract

一种半导体封装可包括封装衬底、中间层、逻辑芯片、至少一个存储器芯片及散热器。所述中间层可位于所述封装衬底的上表面之上。所述中间层可与所述封装衬底电连接。所述逻辑芯片可位于所述中间层的上表面之上。所述逻辑芯片可与所述中间层电连接。所述存储器芯片可位于所述中间层的上表面之上。所述存储器芯片可与所述中间层及所述逻辑芯片电连接。所述散热器可与所述逻辑芯片的上表面进行热接触，以耗散所述逻辑芯片中的热量。

Description

半导体封装
[相关申请的交叉参考]
本申请主张2018年10月22日在韩国知识产权局(Korean Intellectual PropertyOffice，KIPO)提出申请的韩国专利申请第10-2018-0125678号的优先权，所述韩国专利申请的公开内容全部并入本文中供参考。
技术领域
各示例性实施例涉及一种半导体封装。更具体来说，各示例性实施例涉及一种包括存储器芯片及逻辑芯片的系统级封装。
背景技术
系统级封装(system in package或system-in-a-package，SiP)通常包括被包含于同一芯片载体封装中的多个集成电路。举例来说，所述系统级封装可包括安装在同一芯片载体封装内的多个存储器芯片及逻辑芯片。在此种情形中，存储器芯片及逻辑芯片可通过位于所述芯片与系统级封装的系统衬底之间的中间层(interposer)而彼此电连接。分别地，系统级封装的各芯片可具有不同的厚度。举例来说，一个或多个存储器芯片可具有由经堆叠存储器芯片形成的多芯片式结构。因此，这些多芯片式存储器芯片可具有可比逻辑芯片的厚度大的厚度。
发明内容
根据示例性实施例，一种半导体封装可包括：封装衬底；中间层，位于所述封装衬底的上表面之上且电连接到所述封装衬底；逻辑芯片，位于所述中间层的上表面之上且电连接到所述中间层；存储器芯片，位于所述中间层的所述上表面之上且电连接到所述中间层及所述逻辑芯片；以及散热器，与所述逻辑芯片的上表面进行热接触，以耗散所述逻辑芯片中的热量。
根据示例性实施例，一种半导体封装可包括：封装衬底；中间层，位于所述封装衬底的上表面之上且与所述封装衬底电连接；逻辑芯片，位于所述中间层的上表面之上且与所述中间层电连接；以及存储器芯片，位于所述中间层的所述上表面之上且与所述中间层及所述逻辑芯片电连接，其中所述存储器芯片具有比所述逻辑芯片的上表面高的上表面。所述半导体封装可进一步包括：散热器，与所述逻辑芯片的所述上表面进行热接触，以耗散所述逻辑芯片中的热量，所述散热器具有与所述存储器芯片的所述上表面共面的上表面；以及主散热器，与所述存储器芯片的及所述散热器的所述上表面进行接触，以耗散所述存储器芯片及所述散热器中的热量。
根据示例性实施例，一种半导体封装可包括：封装衬底；中间层，位于所述封装衬底的上表面之上且与所述封装衬底电连接；逻辑芯片，位于所述中间层的上表面之上且与所述中间层电连接；存储器芯片，位于所述中间层的所述上表面之上且与所述中间层及所述逻辑芯片电连接，其中所述存储器芯片具有可比所述逻辑芯片的上表面高的上表面。所述半导体封装可进一步包括主散热器，所述主散热器包括与所述存储器芯片的所述上表面进行热接触的第一下表面以及属于从所述下表面延伸出的热传递部分且与所述逻辑芯片的所述上表面进行热接触的第二下表面，以耗散所述存储器芯片及所述逻辑芯片中的热量。
附图说明
结合附图阅读以下详细说明，将会更清楚地理解各示例性实施例。图1至图5表示本文中所述的非限制性示例性实施例。
图1是示出根据示例性实施例的半导体封装的剖视图。
图2是示出图1所示半导体封装的示意性平面图。
图3是示出图1所示半导体封装的上面安装有芯片的中间层的示意性平面图。
图4是示出根据其他示例性实施例的半导体封装的剖视图。
图5是示出根据又一些示例性实施例的半导体封装的剖视图。
[符号的说明]
110：封装衬底
120：中间层
122：连接通孔
124：导电图案
130：逻辑芯片
140：存储器芯片
150：散热器
155：主散热器
160、164：外部端子
162：导电凸块
170、172：热传递粘合剂
180：包封部件
190：集成式散热器
192：热传递部分
具体实施方式
在下文中，将参照附图详细地解释各示例性实施例。
图1是示出根据示例性实施例的半导体封装的剖视图，图2是图1所示半导体封装的示意性平面图，且图3是图1所示半导体封装的上面安装有芯片的中间层的示意性平面图。应注意，各图仅为示意图，且图1所示的相对尺寸不同于图2及图3所示的相对尺寸。
在图1所示实施例的实例中，半导体封装包括封装衬底110、中间层120、逻辑芯片130、多个存储器芯片140、散热器150及包封部件180。所述半导体封装可例如为系统级封装(SiP)。
封装衬底110可包括导电线(图中未示出)。所述导电线中的每一者可包括沿着封装衬底110的上表面及/或下表面延伸的导电迹线、及/或在封装衬底110的上表面与下表面之间延伸的导通孔。然而，各实施例可不仅限于封装衬底110的导电线的任何特定配置。此外，所述导电线中的每一者可具有端接在外部端子160及164处的相对两端。外部端子160可例如为位于中间层120与封装衬底110之间的焊料球或凸块。外部端子164可例如为位于封装衬底110的下表面上的焊料球或凸块。然而，再次，各实施例可不仅限于外部端子160及164的任何特定配置。
在图1至图3所示的实例中，中间层120可布置在封装衬底110的上表面之上。
中间层120可包括绝缘衬底、多个连接通孔122(仅图1中示出)及多个导电图案124(仅图3中示出)。连接通孔122可垂直延伸穿过绝缘衬底，使得上端部可在中间层120的上表面处暴露出且下端部可在中间层120的下表面处暴露出。连接通孔122的下端部可通过外部端子160与封装衬底110中的导电线电连接。这样一来，封装衬底110及中间层120可通过外部端子160彼此电连接。如图3中所示，导电图案124可布置在中间层120的上表面上。
逻辑芯片130可布置在中间层120的上表面上。在示例性实施例中，逻辑芯片130可布置在中间层120的上表面的中心部分上。在逻辑芯片130的下表面上可布置有接垫。因此，逻辑芯片130的下表面可对应于逻辑芯片130的有源面。逻辑芯片130可通过导电凸块162与中间层120电连接。也就是说，逻辑芯片130的接垫可通过导电凸块162与中间层120中的连接通孔122的上端部电连接。
参照图1及图3，存储器芯片140可布置在中间层120的上表面上。存储器芯片140中的每一者可包括接垫。所述接垫可布置在存储器芯片140中的每一者的下表面上。因此，存储器芯片140的下表面可对应于存储器芯片140的有源面。存储器芯片140可通过导电凸块162与中间层120电连接。也就是说，存储器芯片140的接垫可通过导电凸块162与中间层120中的连接通孔122的上端部电连接。在示例性实施例中，存储器芯片140中的至少一者可包括高带宽存储器(high bandwidth memory，HBM)芯片。
在示例性实施例中，各存储器芯片140可被布置成环绕逻辑芯片130。存储器芯片140可通过中间层120的上表面上的导电图案124与逻辑芯片130电连接。
此外，存储器芯片140中的一者或多者可具有其中相对于封装衬底110的水平表面垂直堆叠两个或更多个存储器芯片的多芯片式结构。存储器芯片140中的每一者的经堆叠芯片的数目可不受限且可为四个、八个、十二个、十六个等。存储器芯片140的多芯片式结构可具有可比逻辑芯片130的厚度大的厚度。因此，逻辑芯片130的上表面可被定位于的平面低于存储器芯片140的上表面可被定位于的平面。
散热器150可布置在逻辑芯片130的上表面上。散热器150可与逻辑芯片130的上表面进行热接触，以耗散从逻辑芯片130产生的热量。散热器150可具有可与逻辑芯片130的宽度实质上相同的宽度。散热器150可具有可与逻辑芯片130的长度实质上相同的长度。因此，散热器150可具有与逻辑芯片130的侧表面共面的侧表面。
在示例性实施例中，散热器150可具有与存储器芯片140的上表面共面的上表面。由于散热器150的上表面可与存储器芯片140的上表面共面，因此可通过以下工艺在存储器芯片140之上容易地形成结构。举例来说，如在下一实施例中所述，可在存储器芯片140的上表面上轻易地布置用于耗散存储器芯片140中的热量的主散热器。可根据经堆叠存储器芯片140的厚度来确定散热器150的厚度。作为另一选择，散热器150的上表面可高于或低于存储器芯片140的上表面。
散热器150可为虚设芯片。举例来说，可使用在半导体制作工艺中被确定为有缺陷的虚设芯片作为散热器150。因此，散热器150可包括虚设芯片的硅。
散热器150可使用热传递粘合剂170附着到逻辑芯片130的上表面。热传递粘合剂170可用以将逻辑芯片130中的热量传递到散热器150。在示例性实施例中，热传递粘合剂170可包含热界面材料(thermal interface material，TIM)。
可例如通过将包封剂供应到容纳半导体封装的模具中来形成包封部件180。包封部件180可布置在中间层120的上表面与存储器芯片140的下表面之间的空间、存储器芯片140的内侧表面与逻辑芯片130的外侧表面及散热器150的外侧表面之间的空间中、以及存储器芯片140的外侧表面上。包封部件180可具有与存储器芯片140的及散热器150的上表面共面的上表面。
图4是示出根据示例性实施例的半导体封装的剖视图。
在图4所示实施例的实例中，半导体封装可包括封装衬底110、中间层120、逻辑芯片130、多个存储器芯片140、散热器150、主散热器155及包封部件180。
图4所示封装衬底110、中间层120、逻辑芯片130、存储器芯片140、散热器150及包封部件180可与前面所述的图1至图3所示者相同或实质上相同。因此，此处不再对此类元件予以赘述，以避免冗余。
图4所示实例与图1至图3所示实例的不同在于另外设置了主散热器155。
参照图4，主散热器155可布置在存储器芯片140的及散热器150的上表面上。主散热器155可耗散存储器芯片140中的热量及散热器150中的热量。也就是说，主散热器155可直接耗散存储器芯片140中的热量。此外，主散热器155可通过散热器150间接耗散逻辑芯片130中的热量。
在示例性实施例中，主散热器155可具有平坦下表面。如以上所提及，由于散热器150的上表面及存储器芯片140的上表面可彼此共面，因此主散热器155的平坦下表面与散热器150的上表面及存储器芯片140的上表面之间的接触面积可扩展。因此，从散热器150及存储器芯片140到主散热器155的热传递比率可提高。
主散热器155可使用热传递粘合剂172附着到存储器芯片140的及散热器150的上表面。热传递粘合剂172可将存储器芯片140及散热器150中的热量传递到主散热器155。在示例性实施例中，热传递粘合剂172可包含热界面材料(TIM)。
在示例性实施例中，主散热器155可具有与包封部件180的外侧表面共面的外侧表面。作为另一选择，如同在图4所示的实例中，主散热器155的外侧表面可相对于包封部件180的外侧表面水平突出。此外，主散热器155可包含金属。作为另一选择，主散热器155可包含硅。
图5是示出根据示例性实施例的半导体封装的剖视图。
在图5所示实施例的实例中，半导体封装可包括封装衬底110、中间层120、逻辑芯片130、多个存储器芯片140、集成式散热器190及包封部件180。
图5所示封装衬底110、中间层120、逻辑芯片130、存储器芯片140及包封部件180可与前面所述的图1至图3所示者相同或实质上相同。因此，此处不再对此类元件予以赘述，以避免冗余。
图5所示实例与图4所示实例的不同在于，图4所示散热器150及主散热器155被替换成图5所示集成式散热器190。如图5中所示，集成式散热器190可为位于存储器芯片140的上表面之上的单件式散热器，其具有位于中心且在逻辑芯片130的上表面之上向下突出的热传递部分192。也就是说，如同在图5所示实例中，集成式散热器190可具有：第一下表面，被配置成使用热传递粘合剂172与存储器芯片140的上表面进行热接触；以及属于热传递部分192的第二下表面，由所述第一下表面环绕并低于所述第一下表面且被配置成使用热传递粘合剂170与逻辑芯片130的上表面进行热接触。作为实例，集成式散热器190可由金属或硅形成。
在图5所示实例中，在逻辑芯片130中产生的热量可通过集成式散热器190的中心下平坦表面(即，热传递部分192的下表面)而耗散，且在存储器芯片140中产生的热量可通过集成式散热器190的外下平坦表面而耗散。
根据示例性实施例，散热器可与逻辑芯片的上表面进行接触，以通过散热器有效地耗散逻辑芯片中的热量。此外，散热器的上表面可与存储器芯片的上表面共面，以扩展主散热器与存储器芯片之间以及主散热器与散热器的上表面之间的接触面积。因此，逻辑芯片及存储器芯片中的热量可通过主散热器而有效地耗散。
以上内容是对示例性实施例的说明，而不应被解释为限制各实施例。虽然已阐述了几个示例性实施例，然而所属领域中的技术人员应易于了解，在不本质上背离本发明概念的新颖教示内容及优点的条件下，可对示例性实施例作出许多修改。因此，所有此种修改均旨在被包含于在权利要求书中所界定的本发明概念的范围内。在权利要求书中，构件加功能(means-plus-function)条款旨在涵盖本文中阐述为执行所述功能的结构，且不仅涵盖结构性等效物而且也涵盖等效结构。因此，应理解，以上内容是对各种示例性实施例的说明，而不应被解释为仅限于所公开的具体示例性实施例，且对所公开示例性实施例的修改以及其他示例性实施例均旨在被包含于所附权利要求书的范围内。

Claims (25)

1.一种半导体封装，包括：
封装衬底；
中间层，位于所述封装衬底的上表面之上且电连接到所述封装衬底；
逻辑芯片，位于所述中间层的上表面之上且电连接到所述中间层；
存储器芯片，位于所述中间层的所述上表面之上且电连接到所述中间层及所述逻辑芯片；以及
散热器，与所述逻辑芯片的上表面进行热接触，以耗散所述逻辑芯片中的热量。
2.根据权利要求1所述的半导体封装，其中所述散热器包括虚设芯片。
3.根据权利要求2所述的半导体封装，其中所述虚设芯片包含硅。
4.根据权利要求1所述的半导体封装，其中所述散热器具有与所述存储器芯片的上表面共面的上表面。
5.根据权利要求1所述的半导体封装，进一步包括夹置在所述逻辑芯片与所述散热器之间的热传递粘合剂。
6.根据权利要求5所述的半导体封装，其中所述热传递粘合剂包含热界面材料。
7.根据权利要求1所述的半导体封装，进一步包括与所述存储器芯片的上表面及所述散热器的上表面进行热接触的主散热器，以耗散所述存储器芯片及所述散热器中的热量。
8.根据权利要求7所述的半导体封装，其中所述主散热器包含金属。
9.根据权利要求7所述的半导体封装，进一步包括夹置在所述主散热器与所述存储器芯片的所述上表面之间以及所述主散热器与所述散热器的所述上表面之间的热传递粘合剂。
10.根据权利要求9所述的半导体封装，其中所述热传递粘合剂包含热界面材料。
11.根据权利要求1所述的半导体封装，其中所述存储器芯片具有比所述逻辑芯片的厚度大的厚度、以及比所述逻辑芯片的所述上表面高的上表面。
12.根据权利要求1所述的半导体封装，其中所述存储器芯片包括环绕所述逻辑芯片的多个存储器芯片。
13.根据权利要求12所述的半导体封装，其中所述存储器芯片中的至少一者具有包括经垂直堆叠存储器芯片的多芯片式结构。
14.根据权利要求1所述的半导体封装，其中所述中间层包括：
绝缘衬底；
多个连接通孔，垂直布置在所述绝缘衬底中且与所述封装衬底电连接；以及
多个导电图案，布置在所述绝缘衬底的上表面上，以将所述存储器芯片与所述逻辑芯片电连接。
15.根据权利要求14所述的半导体封装，进一步包括导电凸块，所述导电凸块位于所述连接通孔与所述存储器芯片之间以及所述连接通孔与所述逻辑芯片之间。
16.根据权利要求14所述的半导体封装，进一步包括位于所述连接通孔与所述封装衬底之间的导电凸块。
17.根据权利要求1所述的半导体封装，进一步包括包封部件，所述包封部件布置在所述中间层与所述存储器芯片之间的空间、所述存储器芯片与所述逻辑芯片之间的空间、所述存储器芯片与所述散热器之间的空间中、以及所述存储器芯片的外侧表面上。
18.根据权利要求17所述的半导体封装，其中所述包封部件具有与所述存储器芯片的上表面及所述散热器的上表面共面的上表面。
19.根据权利要求1所述的半导体封装，进一步包括安装在所述封装衬底的下表面上的外部端子。
20.一种半导体封装，包括：
封装衬底；
中间层，位于所述封装衬底的上表面之上且与所述封装衬底电连接；
逻辑芯片，位于所述中间层的上表面之上且与所述中间层电连接；
存储器芯片，位于所述中间层的所述上表面之上且与所述中间层及所述逻辑芯片电连接，所述存储器芯片具有比所述逻辑芯片的上表面高的上表面；
散热器，与所述逻辑芯片的所述上表面进行热接触，以耗散所述逻辑芯片中的热量，所述散热器具有与所述存储器芯片的所述上表面共面的上表面；以及
主散热器，与所述存储器芯片的所述上表面及所述散热器的所述上表面进行热接触，以耗散所述存储器芯片及所述散热器中的热量。
21.根据权利要求20所述的半导体封装，其中所述散热器包括虚设芯片。
22.根据权利要求21所述的半导体封装，其中所述虚设芯片包含硅。
23.根据权利要求20所述的半导体封装，进一步包括夹置在所述逻辑芯片与所述散热器之间的热传递粘合剂。
24.根据权利要求20所述的半导体封装，进一步包括夹置在所述主散热器与所述存储器芯片之间以及所述主散热器与所述散热器之间的热传递粘合剂。
25.根据权利要求20所述的半导体封装，其中所述存储器芯片包括环绕所述逻辑芯片的多个存储器芯片。
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