CN116487343A - 用于多个模具封装的可研磨散热器 - Google Patents
用于多个模具封装的可研磨散热器 Download PDFInfo
- Publication number
- CN116487343A CN116487343A CN202310092288.9A CN202310092288A CN116487343A CN 116487343 A CN116487343 A CN 116487343A CN 202310092288 A CN202310092288 A CN 202310092288A CN 116487343 A CN116487343 A CN 116487343A
- Authority
- CN
- China
- Prior art keywords
- semiconductor
- die
- metal layer
- semiconductor device
- metal heat
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 claims abstract description 175
- 229910052751 metal Inorganic materials 0.000 claims abstract description 76
- 239000002184 metal Substances 0.000 claims abstract description 76
- 238000000465 moulding Methods 0.000 claims abstract description 32
- 238000000034 method Methods 0.000 claims description 22
- 239000000758 substrate Substances 0.000 claims description 22
- 238000001465 metallisation Methods 0.000 claims description 7
- 238000009713 electroplating Methods 0.000 claims description 6
- 238000004519 manufacturing process Methods 0.000 claims description 6
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 claims description 5
- 229910052802 copper Inorganic materials 0.000 claims description 5
- 239000010949 copper Substances 0.000 claims description 5
- 238000007747 plating Methods 0.000 claims description 5
- 238000012545 processing Methods 0.000 claims description 4
- 238000000151 deposition Methods 0.000 claims description 3
- 238000004806 packaging method and process Methods 0.000 claims 1
- 238000005299 abrasion Methods 0.000 abstract description 3
- 235000012431 wafers Nutrition 0.000 description 54
- 239000000463 material Substances 0.000 description 8
- 238000005240 physical vapour deposition Methods 0.000 description 3
- 125000006850 spacer group Chemical group 0.000 description 3
- 239000004593 Epoxy Substances 0.000 description 2
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 2
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 description 2
- 239000000853 adhesive Substances 0.000 description 2
- 230000001070 adhesive effect Effects 0.000 description 2
- 229910052782 aluminium Inorganic materials 0.000 description 2
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 2
- 238000005229 chemical vapour deposition Methods 0.000 description 2
- 238000007906 compression Methods 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 238000005516 engineering process Methods 0.000 description 2
- 230000006870 function Effects 0.000 description 2
- 238000002161 passivation Methods 0.000 description 2
- 238000005498 polishing Methods 0.000 description 2
- 229910052710 silicon Inorganic materials 0.000 description 2
- 239000010703 silicon Substances 0.000 description 2
- 239000010936 titanium Substances 0.000 description 2
- 229910052719 titanium Inorganic materials 0.000 description 2
- 229910052581 Si3N4 Inorganic materials 0.000 description 1
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 1
- PNEYBMLMFCGWSK-UHFFFAOYSA-N aluminium oxide Inorganic materials [O-2].[O-2].[O-2].[Al+3].[Al+3] PNEYBMLMFCGWSK-UHFFFAOYSA-N 0.000 description 1
- JRACIMOSEUMYIP-UHFFFAOYSA-N bis($l^{2}-silanylidene)iron Chemical compound [Si]=[Fe]=[Si] JRACIMOSEUMYIP-UHFFFAOYSA-N 0.000 description 1
- 238000004364 calculation method Methods 0.000 description 1
- 239000000969 carrier Substances 0.000 description 1
- 230000001413 cellular effect Effects 0.000 description 1
- 239000000919 ceramic Substances 0.000 description 1
- 238000004891 communication Methods 0.000 description 1
- 150000001875 compounds Chemical class 0.000 description 1
- 230000006835 compression Effects 0.000 description 1
- 238000000748 compression moulding Methods 0.000 description 1
- 238000011109 contamination Methods 0.000 description 1
- PMHQVHHXPFUNSP-UHFFFAOYSA-M copper(1+);methylsulfanylmethane;bromide Chemical compound Br[Cu].CSC PMHQVHHXPFUNSP-UHFFFAOYSA-M 0.000 description 1
- 230000000593 degrading effect Effects 0.000 description 1
- 239000011521 glass Substances 0.000 description 1
- 238000010438 heat treatment Methods 0.000 description 1
- 238000003384 imaging method Methods 0.000 description 1
- 238000001746 injection moulding Methods 0.000 description 1
- 230000005055 memory storage Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000013021 overheating Methods 0.000 description 1
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 1
- 229910052814 silicon oxide Inorganic materials 0.000 description 1
- 239000007787 solid Substances 0.000 description 1
- 238000004544 sputter deposition Methods 0.000 description 1
- 238000003860 storage Methods 0.000 description 1
- 238000012546 transfer Methods 0.000 description 1
- 238000001721 transfer moulding Methods 0.000 description 1
- 238000007740 vapor deposition Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
- H01L23/36—Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks
- H01L23/373—Cooling facilitated by selection of materials for the device or materials for thermal expansion adaptation, e.g. carbon
- H01L23/3736—Metallic materials
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
- H01L23/42—Fillings or auxiliary members in containers or encapsulations selected or arranged to facilitate heating or cooling
- H01L23/433—Auxiliary members in containers characterised by their shape, e.g. pistons
- H01L23/4334—Auxiliary members in encapsulations
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
- H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
- H01L21/561—Batch processing
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
- H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
- H01L21/568—Temporary substrate used as encapsulation process aid
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
- H01L21/60—Attaching or detaching leads or other conductive members, to be used for carrying current to or from the device in operation
- H01L21/603—Attaching or detaching leads or other conductive members, to be used for carrying current to or from the device in operation involving the application of pressure, e.g. thermo-compression bonding
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
- H01L21/683—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping
- H01L21/6835—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
- H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
- H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
- H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
- H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
- H01L23/3121—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation
- H01L23/3128—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation the substrate having spherical bumps for external connection
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
- H01L23/36—Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks
- H01L23/367—Cooling facilitated by shape of device
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/544—Marks applied to semiconductor devices or parts, e.g. registration marks, alignment structures, wafer maps
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
- H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
- H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
- H01L25/065—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00
- H01L25/0657—Stacked arrangements of devices
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
- H01L25/16—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof the devices being of types provided for in two or more different main groups of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. forming hybrid circuits
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
- H01L25/50—Multistep manufacturing processes of assemblies consisting of devices, each device being of a type provided for in group H01L27/00 or H01L29/00
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2221/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof covered by H01L21/00
- H01L2221/67—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere
- H01L2221/683—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping
- H01L2221/68304—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
- H01L2221/68327—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support used during dicing or grinding
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
- H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
- H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
- H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
- H01L2225/06503—Stacked arrangements of devices
- H01L2225/06513—Bump or bump-like direct electrical connections between devices, e.g. flip-chip connection, solder bumps
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
- H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
- H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
- H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
- H01L2225/06503—Stacked arrangements of devices
- H01L2225/06555—Geometry of the stack, e.g. form of the devices, geometry to facilitate stacking
- H01L2225/06565—Geometry of the stack, e.g. form of the devices, geometry to facilitate stacking the devices having the same size and there being no auxiliary carrier between the devices
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
- H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
- H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
- H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
- H01L2225/06503—Stacked arrangements of devices
- H01L2225/06582—Housing for the assembly, e.g. chip scale package [CSP]
- H01L2225/06586—Housing with external bump or bump-like connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
- H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
- H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
- H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
- H01L2225/06503—Stacked arrangements of devices
- H01L2225/06589—Thermal management, e.g. cooling
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49811—Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads
- H01L23/49816—Spherical bumps on the substrate for external connection, e.g. ball grid arrays [BGA]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
- H01L23/5385—Assembly of a plurality of insulating substrates
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
- H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
- H01L25/10—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices having separate containers
- H01L25/105—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices having separate containers the devices being of a type provided for in group H01L27/00
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
- H01L25/18—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof the devices being of types provided for in two or more different subgroups of the same main group of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Manufacturing & Machinery (AREA)
- Chemical & Material Sciences (AREA)
- Materials Engineering (AREA)
- Mechanical Treatment Of Semiconductor (AREA)
Abstract
一种半导体封装可包括一种半导体模具堆栈,包括一个顶部模具和在顶部模具下方的一个或多个核心模具。所述半导体包还可以包括一种金属散热器,它镀在所述顶部模具的顶表面,且具有多个侧面与所述半导体模堆的多个侧壁的相应侧面共面。一种可能围绕半导体模具堆栈和金属散热器的模塑件,其中模塑件包括与所述金属散热器的外露上表面共面的上表面,模塑件的上表面和金属散热器的暴露上表面都经过机械改变。例如,金属散热器和模具可以同时用研磨盘研磨,并可以显示研磨痕迹的结果。
Description
技术领域
本发明一般涉及半导体器件封装,特别是具有可研磨散热器的半导体器件封装。
背景
半导体器件制造商不断寻求制造更小、更快、更强大的器件,并为各种各样的产品(如计算机、手机、手表、相机等)提供更高密度的组件。在不大幅增加器件占用空间的情况下提高半导体器件的速度和功率的一种方法是在单个封装中垂直堆栈多个半导体芯片。然而,功率的增加会导致器件产生更多的热量。由于堆栈式模具的较高密度和减小的表面积,发热问题被进一步放大。
图纸的简要描述
参考下面的图纸,可以更好地理解目前技术的许多方面。图纸中的部件不一定按比例显示。它们的重点放在清楚地说明目前技术的原理。
图1是根据本发明的实施例,半导体器件封装的横断面视图。
图2A是根据本发明的实施例,安装在载体上的半导体晶圆的横断面视图。
图2B是根据本发明的实施例,减薄后安装在载体上的半导体晶圆的横断面视图。
图2C是根据本发明的实施例,具有种子层的半导体晶圆的横断面视图。
图2D是根据本发明的实施例,具有镀金属层的半导体晶圆的横断面视图。
图2E是根据本发明的实施例,具有镀金属层的多个半导体模具的横断面视图。
图2F是根据本发明的实施例,包括多个半导体模具堆栈的中间半导体结构的横断面视图。
图2G是根据本发明的实施例,进行研磨后包括多个半导体模具堆栈的中间半导体结构的横断面视图。
图2H是根据本发明的实施例,多个切单的半导体模封装的横断面视图。
图3是根据本发明的实施例,包括镀有可研磨金属散热器的半导体器件组件的半导体器件的横断面视图。
图4是示出根据本发明的实施例,制造半导体器件封装的方法的流程图。
图5是包括根据本发明的实施例,半导体器件的系统的示意图。
详细描述
在本发明中,讨论了许多具体细节,以提供本发明的实施例的彻底和使能的描述。本领域普通技术人员将认识到,可以在没有一个或多个具体细节的情况下实施本发明。可以不显示和/或不详细描述通常与半导体器件相关的知名结构和/或操作,以避免模糊本发明的其他方面。一般来说,应该理解为,在本发明的这些具体实施例之外的各种其他设备、系统和/或方法可能在本发明的范围内。
术语“半导体器件”一般是指包括半导体材料的固态器件。半导体器件可以包括(例如)半导体基板、晶圆、面板或来自晶圆或基板的单个晶圆。半导体器件还可以包括沉积在基板上的一个或多个器件层。
术语“半导体器件封装”可以指把一个或多个半导体器件集成到一个公共封装中的一种安排。半导体封装可包括部分或完全封装至少一个半导体器件的外壳、模塑件或外壳。半导体封装还可以包括携带一个或多个半导体器件的基板。基板可以附着于或以其他方式并入所述壳体或外壳内。
术语“半导体器件组件”可以指由一个或多个半导体器件、半导体器件封装和/或基板组成的组件,其可以包括插入物、支架和/或其他合适的基板。半导体器件组件可以制造为(但不限于)离散封装形式、条状或矩阵形式和/或晶圆面板形式。
随着制造商在3D集成电路和封装中不断增加模具数量,多个模具堆造成的过热成为一个更大的问题。这些堆栈内的温度波动会导致组件和互连变形,降低性能,最终导致器件故障。此外,购买带有多个模具堆的器件用于其产品的客户通常需要进行模后研磨,例如生产更薄的手机、笔记本电脑和手表。传统的散热器使用热界面材料(如热糊或热粘合剂)连接到顶部模具。然而,这些热界面材料不能承受研磨过程的力。这可能需要客户将器件变薄,并应用单独的散热器,这增加了步骤数和总成本。
为了解决这些问题,本发明的实施例提供了一种半导体器件封装,包括镀在一堆半导体模具的顶部模具上的可研磨散热器。电镀散热器消除了使用热界面材料的需要。半导体器件堆栈和可研磨散热器可嵌入在模塑件中。模塑件为散热器提供了额外的支撑,并使客户能够根据需要同时研磨模塑件和散热器,使封装变薄,而无需研磨顶部模具或需要单独的散热器。为了制造这些封装,顶部模具可以安装在一个虚拟载体上、将其变薄,并镀上可研磨的散热器材料。这可以是一个晶圆级别的工艺,即在半导体晶圆从载体剥离并切成单独的镀模之前,将散热器材料镀上。然后,镀上的顶部模具可以安装在一堆半导体模具上,由模塑件封装,并进行研磨,以暴露散热器。
图1是根据本发明的实施例,半导体器件封装100的横断面视图。封装100包括安装在基板104上的半导体压模102的堆栈。封装100还包括围绕半导体压模102堆栈的模塑件140。半导体压模102的堆栈可能包括一个镀有金属散热器112的顶部模具106。金属散热器可以是铜、铝或其他合适的散热器材料。如图所示,散热器112的上表面和模塑件140的上表面可能由于研磨模塑件140和散热器112而共面。例如,模塑件140和散热器112可以用砂轮或研磨盘来研磨。因此,散热器112可以表现出磨痕的研磨。散热器112和模塑件140可以进一步研磨,例如由一个在较大系统中使用半导体器件封装100的客户进行研磨。
顶部模具106可以用金属散热器112进行预制,然后通过任何合适的工艺安装在核心模具108上。例如,顶部模具106可以热压粘合(TCB)到核心模具108a。模具附着膜(如非导电膜或CV膜)可以当作堆栈102的模具之间的间隔膜。通过在半导体晶圆上镀一个金属层,顶部模具106可与金属散热器112一起制造。在一些实施例中,在镀前把种子层沉积在晶圆上,例如通过物理气相沉积(PVD)。例如,种子层可以是很薄的一层铜或钛。种子层可以是大约1微米厚。下面的图2A-E更详细地描述了制造流程。
半导体模具102的堆栈可以包括所述顶部模具106和一个或多个核心模具108。例如,核心模具108可以是存储器模具,例如高带宽存储器(HBM)装置的DRAM模具。另外,核心模具108可以是其它类型的存储器,例如SRAM、SDRAM或闪存,或非存储器装置。核心模具108的厚度可以与顶部模具106大致相同。例如,核心模具108和顶部模具106可各自为约50微米厚。虽然图1显示了包括顶部模具106和核心模具108在内的总共五个模具,但本发明的实施例可以包括更多的模具,例如8、12、16个或更多模具。在一些实施例中,堆栈102可具有少至一个模具,即只有一个顶部模具106。此外,在一些实施例中,堆栈102的模具可以具有相同的尺寸(如图1所示),也可以具有不同的尺寸。堆栈102的模具可以具有不同的堆栈方式,例如锥形堆栈、悬垂模具堆栈等。
可以通过硅通孔(TSV)和凸点来互连半导体模具102的堆栈。在一些实施例中,堆栈102的模具可以使用键合线而不是TSV来连接,或在TSV之外连接。例如,模具之间的间隔膜可以提供将键合线连接到模具所需的空间。然后可以将键合线耦合到封装基板104(未示出)上的衬垫上。
封装基板104可以是或包括内插器、印刷电路板、介电隔离件、另一个半导体模(例如,逻辑模)或另一个合适的基板。封装基板104可包括电耦合到半导体模具堆栈102的衬垫。在一些实施例中,封装基板104包括额外的半导体组件(例如掺杂硅片或硅铁硅片)、非导电部件(例如,各种陶瓷基板,例如氧化铝(Al2O3)等)、氮化铝和/或导电部分(例如,互连电路、TSV等)。封装基板104可进一步包含电耦合到封装基板104且被配置成将封装100电耦合到外部装置(未示出)的电连接器124(例如,焊盘、导电凸块、导电柱、导电环氧树脂和/或其它合适的导电元件)。封装基板104可以选择包括一个或多个信号路由结构或层(未示出),一个或多个信号路由结构或层包括诸如迹线、通孔等的导电部件,其在电连接器124与半导体管芯堆栈102之间传输信号。
图2A-G说明了在制造过程中处于不同阶段的半导体器件组装。图2A是根据本发明的实施例,安装在载体250上的半导体晶圆200的横断面视图。半导体晶圆200可以使用标准安装流程将其安装在载体250上。例如,可以使用临时安装粘合剂202将晶圆200安装到载体。载体250可由玻璃或其它合适的材料制成。
图2B是根据本发明的实施例,减薄后安装在载体上的图2A的半导体晶圆200的横断面视图。半导体晶圆可以通过后磨200来减薄(例如用砂轮)。半导体晶圆200可以减薄到约50微米厚度。
图2C是根据本发明的实施例,具有种子层204的半导体晶圆200的横断面视图。种子层204可以通过PVD方法沉积在半导体晶圆200的背面上,例如溅镀或蒸发沉积。种子层可包括金属(例如铜或钛200,并且有助于在半导体晶圆200上电镀金属层,如下图2D所示。在一些实施例中,半导体晶圆200的背面在沉积种子层204之前进行钝化。钝化可以去除半导体晶圆200的表面上的污染,并提高镀金属层的附着力。例如,半导体晶圆200可以通过化学气相沉积(CVD)形成氮化硅或氧化硅的钝化层来钝化。钝化层和种子层204加起来可以小于1微米厚。
图2D是根据本发明的实施例,具有镀金属层206的半导体晶圆200的横断面视图。可通过图2C的种子层204来促进所镀金属层206的电镀。镀层金属层206可包括适合散热器的金属,例如铜或铝。金属层206可具有大约50至250微米、100至200微米、125至175微米等的厚度。例如,金属层206可以是大约135微米厚。镀金属层206可以类似于图1的金属散热器112,除了它镀在半导体晶圆200上而不是单独的模具上。在金属层206被镀后,半导体晶圆200可以从载体250上剥离。
图2E是根据本发明的实施例,具有镀金属层206a-c的多个半导体模具200a-c的横断面视图。在从图2A-D的载体250剥离后,图2A-D的具有金属层206的半导体晶圆200可以切块形成多个半导体模具,包括分别镀有金属层206a-c的半导体模具200a-c。半导体晶圆200和金属层206可以用切割锯沿着一条或多条锯路切块。可以使用本领域已知的其他合适的切块方法,只要它们除了可以切块晶圆200之外还可以切块金属层206。根据切单方法的不同,金属层206a-c或半导体晶圆200a-c可以沿其侧壁显示切单的证据。例如,金属层206a-c的侧壁或半导体模具200a-c的侧壁可以显示与机械变化相关的标记,例如用锯子或刀片切割的锯痕。在一些实施例中,锯条可以用直线模式来布置。
图2F是根据本发明的实施例,包括多个半导体模具堆栈212a-c的中间半导体结构210的横断面视图。图2F仅为说明目的而显示三个半导体模具堆栈212a-c,但中间半导体结构210可根据所述模具的大小包括更多数量的模具堆栈。例如,晶圆可以是直径300mm的圆,而模具可以是10x10mm的正方形。半导体晶圆堆212a-c还可以在每个晶圆堆中包括更多数量的模具,例如8个、12个或16个模具。
半导体模具堆栈212a-c每个可包括具有金属层的顶部模具,类似于图1的半导体模具堆栈102。每个半导体模具堆栈212a-c可通过将来自图2E的半导体模具堆栈200a-c中的一个安装到核心模具具堆栈214上而形成。因此半导体模具200a-c作为半导体模具堆栈212a-c的顶部模具,类似于图1的顶部模具106。半导体模具200a-c可以通过热压键合(TCB)来安装,其中TCB会对键合碰撞模具施加热量。TCB通常是一个缓慢的过程,半导体模具200a-c背面的金属层206a-c可以改善应用热量的传递,从而与传统模具相比,能增强TCB工艺。在TCB之前,模具附着膜(例如NCF可以层压在模具上。或者,应用毛细管底填料(CUF)来填充TCB后模堆之间的间隙。
核心模具214可以使用与安装顶部半导体模具200a类似的工艺彼此安装在一起,例如,使用层压模具附着膜的TCB。核心模具214可通过TSV进行电互连,与连接线相比,TSV在模之间需要更少的空间。然而,也可以使用键合线。核心模具214可以是存储器模具,例如DRAM。
半导体模具堆栈212a-c可安装在接口(IF)晶圆216上。例如,核心模具214可以通过TCB安装在IF晶圆216上。IF晶圆216可包括多个模具。例如,IF晶圆216可包括多个逻辑模,例如存储器控制器或GPU。在一些实施例中,IF晶圆216可包括类似于核心模具214的模。例如,核心模具214和IF晶圆216都可以包含存储器模具。IF晶圆216可包括诸如电路或TSV的电连接,例如,IF晶圆可能包括可在背面变薄之后暴露出来的TSV。
在核心模具214上叠加半导体模具200a-c后,半导体模堆212a-c和金属层206a-c至少可部分被模塑件220包围。例如,模塑件220可以封装这些组件。模塑件220可以是半导体封装中使用的任何合适的模塑化合物,例如环氧树脂,并通过注射成型、转移成型或压缩成型形成。
图2G是根据本发明的实施例,包括研磨后的多个半导体模具堆栈212a-c的中间半导体结构210的横断面视图。中间半导体结构210可以用磨料砂轮或研磨盘来研磨。因此,金属层206a-c可以显示出表明砂轮或研磨盘磨损的机械改变的证据。例如,这种机械改变的证据可以包括漩涡、凹槽或其他痕迹。模塑件220可以被研磨,直到金属层206a-c暴露并与模塑平齐。这就产生了带有嵌入式散热器的器件,可以承受那些想要更薄器件的用户的进一步研磨。研磨和暴露金属层206a-c后,中间半导体结构210可以附着在载体上,IF晶圆216可以变薄。
图2H是根据本发明的实施例,多个切单的半导体器件封装210a-c的横断面视图。图2G的中间半导体结构210可以通过切块锯或其他合适的切块机构切单成半导体器件封装210a-c。切单的半导体器件封装210a-c的每个都可以类似于图1中的半导体器件封装100。如图所示,图2G所示的IF晶圆216可以被切单成单独的216a-c模。此外,图2G的中间半导体结构210可以作为切块工艺的一部分受到额外的处理,例如背面研磨。例如,如图2G所示,因为这样的研磨,模具216a-c可能比IF晶圆216更薄。
图3是根据本发明的实施例,包括镀有可研磨金属散热器306的半导体器件封装302的半导体器件组件300的横断面视图。半导体器件封装302可以类似于图1的半导体器件封装100和图2H的切单的半导体器件封装210a-c。半导体器件封装302包括类似于图1和2H金属散热器112的可研磨金属散热器306和金属层206a-c。
半导体器件组件300可以是存储器器件,例如高带宽存储器(HBM)器件。例如,半导体器件封装302可包括由TSV互连的DRAM模具堆栈,并安装在与处理器芯片304相邻的封装基板310上,例如图形处理单元(GPU)模具。半导体器件封装302可以通过插入体耦合到处理器模304(未示出)。封装基板310可以作为较大系统的一部分安装在PCB 320上,例如使用电连接器315。请注意,这只是一个说明性的示例,包括嵌入式可研磨散热器的半导体器件封装可以用于各种设备或系统,如下面的图5所述。
图4是示出根据本发明的实施例,制造半导体器件封装的方法400的流程图。在405,金属层被镀在半导体晶圆上。例如,金属层可以类似于图2D的金属层206。在一些实施例中,半导体晶圆在电镀之前钝化。所述金属层的电镀可包括沉积一个种子层,如图2C和2D的种子层204。
在410,半导体晶圆和在405镀的金属层被切单以产生多个半导体模具的半导体模具。半导体模具仍然镀有所述金属层的一部分。例如,半导体晶圆和金属层可以使用切块锯或其他合适的切块工艺进行切单。在一些实施例中,然后可以通过热压键合等方法将镀有所述金属层的部分的半导体模具安装在半导体模具的堆栈上。
在415,步骤410中的半导体模具封装一个模塑件。例如,模塑件可类似于图1的模塑件140和图2F-H的模塑件220。在一些实施例中,所述模压封装安装在晶圆上的半导体模堆,例如图2F中的IF晶圆216。
在420,模塑件和金属层的部分进行研磨。模塑件和金属层部分的研磨可以同时进行,例如使用砂轮或研磨盘。在420的研磨之后,金属层部分的研磨成型面与研磨面可共面。在一些实施例中,金属层可以显示出与砂轮磨损一致的研磨痕迹。
图5是包括根据本发明的实施例,半导体器件的系统500的示意图。拥有如上图1-4中所述特征的任何半导体器件和/或芯片之一可以被合并到无数更大和/或更复杂的系统中,其中一个有代表性的例子是图5所示的系统500。系统500可以包括一个处理器502、一个存储器505(例如,SRAM、DRAM、闪存和/或其他存储器设备)、输入/输出设备506和/或其他子系统或组件508。如上图1-4中所述的半导体模具和/或封装可以包括在图5所示的任何元件中。所得到的系统500可以配置为执行各种合适的计算、处理、存储、传感、成像和/或其他功能中的任何一种。因此,系统500的代表性示例包括但不限于计算机和/或其他数据处理器,例如台式计算机、笔记本电脑、互联网设备、手持设备(例如,掌上计算机、可穿戴计算机、蜂窝或移动电话、个人数字助理、音乐播放器等)、平板电脑、多处理器系统、基于处理器或可编程的消费电子产品、网络计算机和小型机。系统500的其他代表性例子包括灯、摄像机、车辆等。关于这些和其他示例,系统500可以安置在单个单元中或分布在多个相互连接的单元上(例如,通过通信网络)。系统500的组件可相应地包括本地和/或远程存储器存储设备和各种合适的计算机可读介质中的任何一种。
从上述内容中可以明白,本发明的具体实施例在此已为了说明目的而进行了描述,但是可以在不偏离本发明的范围的情况下进行各种修改。因此,除了所附权利主张外,本发明不受限制。
Claims (20)
1.一种半导体器件封装,包括:
一种半导体模具堆栈,包括一个顶部模具和顶部模具下方的一个或多个核心模具;
一种金属散热器,镀在所述顶部模具的顶表面,且具有多个侧面与所述半导体模堆的多个侧壁的相应侧面共面;而且
一种围绕半导体模具堆栈和金属散热器的模塑件,其中模塑件包括与所述金属散热器的外露上表面共面的上表面,
其中,模塑件的上表面和金属散热器的暴露上表面都经过机械改变。
2.权利主张1的半导体器件封装,其中金属散热器的在机械方面改变的上表面包括磨痕。
3.权利主张1的半导体器件封装,其中每一个的多个侧面和每一个的多个侧壁被机械改变。
4.权利主张3的半导体器件封装,其中金属散热器的机械改变的侧面包括锯痕。
5.权利主张1的半导体器件封装,其中所述金属散热器具有介于约100微米与200微米之间的厚度。
6.权利主张1的半导体器件封装,进一步包括:
顶部模具和金属散热器之间的种子层。
7.权利主张1的半导体器件封装,其中金属散热器由铜组成。
8.权利主张1的半导体器件封装,其中顶部模具有约50微米的厚度。
9.权利主张1的半导体器件封装,其中顶部模具的顶表面是钝化的。
10.一种半导体器件封装的制造方法,包括:
在半导体晶圆的背面镀一个金属层;
将半导体晶圆与金属层切单,以产生多个半导体模具,每个半导体模具镀有所述金属层的一部分;
将所述多个半导体模具中的一个封装成模塑件;以及
研磨所述模塑件和所述金属层的部分,其中研磨后所述金属层部分的研磨面与所述成型件的研磨面共面。
11.权利主张10的方法,进一步包括:
将半导体晶圆安装在载体上;以及
电镀金属层后,将半导体晶圆从载体上剥离。
12.权利主张10的方法,其中电镀金属层包括:
半导体晶圆背面钝化。
13.权利要求12的方法,其中电镀金属层进一步包括:
在半导体晶圆的钝化背面沉积种子层;以及
在种子层上镀金属层。
14.权利主张10的方法,进一步包括:
在电镀金属层之前,通过化学-机械平面化使半导体晶圆变薄。
15.权利主张10的方法,进一步包括:
将所述多个半导体模中的一个安装在一堆核心半导体模上,然后用模压封装所述多个半导体模中的一个,
其中,模塑件进一步封装了核心半导体模具的堆栈。
16.权利要求15的方法,其中半导体模具通过热压键合安装在堆栈上。
17.权利要求10的方法,其中多个半导体模具中的一个是第一半导体模具,该方法进一步包括:
将所述多个半导体模具中的第二半导体模具封装在所述模具中,所述第二半导体模具镀有所述第二部分金属层;以及
研磨模塑件和金属层的第二部分,
其中,第一半导体模和第二半导体模安装在同一晶圆上,以及
其中,在所述模塑件和所述金属层的部分的研磨后,所述金属层的第二部分的研磨面与所述金属层的第二部分的第二研磨面共面。
18.一种半导体器件组件,包括:
封装基板;
与封装基板耦合的处理器模;
一种耦合到封装基板并电连接到处理器模的半导体模堆,所述半导体模堆栈包括:
顶部模具和在所述顶部模具下方的多个核心模;
一种可研磨的金属散热器,镀在所述顶部模具的顶表面,且具有多个侧面与所述半导体模堆的多个侧壁的相应侧面共面;以及
一种围绕半导体模具堆栈和可研磨金属散热器的模塑件,
其中,可研磨金属散热器的上表面暴露于所述模塑件,并与所述模塑件的上表面共面,以及
其中,所述模具的上表面和所述可研磨金属散热器的上表面均经过机械改变。
19.权利主张18的半导体器件组件,其中处理器模具是图形处理单元(GPU)模具,而核心模具和顶部模具是内存模具。
20.权利主张18的半导体器件组件,其中可研磨金属散热器的上表面和成型的顶部表面显示砂轮磨损的研磨痕迹。
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US17/583,038 US20230238300A1 (en) | 2022-01-24 | 2022-01-24 | Grindable heat sink for multiple die packaging |
US17/583,038 | 2022-01-24 |
Publications (1)
Publication Number | Publication Date |
---|---|
CN116487343A true CN116487343A (zh) | 2023-07-25 |
Family
ID=87216660
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
CN202310092288.9A Pending CN116487343A (zh) | 2022-01-24 | 2023-01-30 | 用于多个模具封装的可研磨散热器 |
Country Status (2)
Country | Link |
---|---|
US (1) | US20230238300A1 (zh) |
CN (1) | CN116487343A (zh) |
-
2022
- 2022-01-24 US US17/583,038 patent/US20230238300A1/en active Pending
-
2023
- 2023-01-30 CN CN202310092288.9A patent/CN116487343A/zh active Pending
Also Published As
Publication number | Publication date |
---|---|
US20230238300A1 (en) | 2023-07-27 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
US11929349B2 (en) | Semiconductor device having laterally offset stacked semiconductor dies | |
US20240071884A1 (en) | Alternative surfaces for conductive pad layers of silicon bridges for semiconductor packages | |
US10867897B2 (en) | PoP device | |
US11164807B2 (en) | Arrangement and thermal management of 3D stacked dies | |
US9059072B2 (en) | Semiconductor packages and methods of fabricating the same | |
CN108538734B (zh) | 具有嵌入式层叠硅通孔管芯的衬底 | |
US6326697B1 (en) | Hermetically sealed chip scale packages formed by wafer level fabrication and assembly | |
US20060216868A1 (en) | Package structure and fabrication thereof | |
US10593620B2 (en) | Fan-out package with multi-layer redistribution layer structure | |
US20230207472A1 (en) | Semiconductor package and manufacturing method of semiconductor package | |
CN112509991A (zh) | 集成电路封装结构、集成电路封装单元及相关制造方法 | |
US10381288B2 (en) | Packaged semiconductor die and CTE-engineering die pair | |
CN115566014A (zh) | 集成电路封装结构及制备方法 | |
CN116487343A (zh) | 用于多个模具封装的可研磨散热器 | |
US10790210B2 (en) | Semiconductor package and manufacturing method thereof | |
CN207250483U (zh) | 晶圆级芯片封装结构 | |
CN110828430A (zh) | 一种封装结构及其制备方法 | |
CN210692483U (zh) | 一种封装结构 | |
CN210516718U (zh) | 一种封装结构 | |
KR20110038561A (ko) | 멀티칩 모듈들을 위한 개선된 전기적 연결들 |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
PB01 | Publication | ||
PB01 | Publication |