JPWO2008108334A1 - 半導体装置及び該半導体装置の製造方法 - Google Patents
半導体装置及び該半導体装置の製造方法 Download PDFInfo
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- JPWO2008108334A1 JPWO2008108334A1 JP2009502572A JP2009502572A JPWO2008108334A1 JP WO2008108334 A1 JPWO2008108334 A1 JP WO2008108334A1 JP 2009502572 A JP2009502572 A JP 2009502572A JP 2009502572 A JP2009502572 A JP 2009502572A JP WO2008108334 A1 JPWO2008108334 A1 JP WO2008108334A1
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- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
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- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
- H01L2224/13001—Core members of the bump connector
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- H01L2224/13025—Disposition the bump connector being disposed on a via connection of the semiconductor or solid-state body
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- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
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- H01L2224/161—Disposition
- H01L2224/16135—Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
- H01L2224/16145—Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
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Abstract
Description
Claims (9)
- 基板と、該基板に接合され、該基板の熱を放出するための放熱部材と、前記基板を保護すべく該基板及び前記放熱部材の周囲を取り囲む保護部材とを備え、前記放熱部材の少なくとも一部は、前記保護部材から露出していることを特徴とする半導体装置。
- 前記基板には、該基板を貫通し、熱伝導率が前記保護部材の熱伝導率よりも高い熱伝達用貫通体が設けられており、該熱伝達用貫通体は、前記放熱部材に結合されていることを特徴とする請求項1に記載の半導体装置。
- 前記放熱部材上には、板部材が前記放熱部材に間隔をおき且つ該放熱部材にほぼ平行になるように配置されていることを特徴とする請求項1又は請求項2に記載の半導体装置。
- 前記基板の周囲を取り囲み且つ前記間隔を充填する樹脂接着剤を更に備え、前記放熱部材の少なくとも一部は、前記樹脂接着剤及び前記保護部材から露出していることを特徴とする請求項1乃至3のいずれか1項に記載の半導体装置。
- 基板と、該基板を取り囲む保護部材とを備える半導体装置であって、前記保護部材の表面に凹凸部が形成されていることを特徴とする半導体装置。
- 前記保護部材の前記凹凸部上には、板部材が前記表面に間隔をおき且つ前記保護部材の前記表面にほぼ平行になるように配置されていることを特徴とする請求項5に記載の半導体装置。
- 前記基板は、複数の半導体チップが積層されることにより形成されることを特徴とする請求項1乃至6のいずれか1項に記載の半導体装置。
- 前記基板がDRAMであることを特徴とする請求項1から請求項7のいずれか1項に記載の半導体装置。
- 熱伝達用貫通体が設けられた基板と該基板の熱を放出するための放熱部材とを互いに重ね合わせること、
前記基板及び前記放熱部材が互いに重なり合った状態で前記熱伝達用貫通体を前記放熱部材に結合すること、
前記熱伝達用貫通体を介して互いに接合された前記基板及び前記放熱部材の周囲を保護部材で取り囲むこと、
該保護部材の一部を除去することにより、前記放熱部材の少なくとも一部を前記保護部材から露出させること、
を含むことを特徴とする半導体装置の製造方法。
Applications Claiming Priority (5)
Application Number | Priority Date | Filing Date | Title |
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JP2007055351 | 2007-03-06 | ||
JP2007055351 | 2007-03-06 | ||
JP2007091083 | 2007-03-30 | ||
JP2007091083 | 2007-03-30 | ||
PCT/JP2008/053768 WO2008108334A1 (ja) | 2007-03-06 | 2008-03-03 | 半導体装置及び該半導体装置の製造方法 |
Publications (1)
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JPWO2008108334A1 true JPWO2008108334A1 (ja) | 2010-06-17 |
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JP2009502572A Pending JPWO2008108334A1 (ja) | 2007-03-06 | 2008-03-03 | 半導体装置及び該半導体装置の製造方法 |
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US (2) | US8436465B2 (ja) |
JP (1) | JPWO2008108334A1 (ja) |
KR (1) | KR101524173B1 (ja) |
TW (2) | TWI424551B (ja) |
WO (1) | WO2008108334A1 (ja) |
Families Citing this family (12)
Publication number | Priority date | Publication date | Assignee | Title |
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JP5298762B2 (ja) * | 2008-10-21 | 2013-09-25 | 株式会社ニコン | 積層型半導体装置、積層型半導体装置の製造方法及び半導体基板 |
JP2010251347A (ja) * | 2009-04-10 | 2010-11-04 | Elpida Memory Inc | 半導体装置の製造方法 |
US10181454B2 (en) * | 2010-03-03 | 2019-01-15 | Ati Technologies Ulc | Dummy TSV to improve process uniformity and heat dissipation |
KR101715761B1 (ko) * | 2010-12-31 | 2017-03-14 | 삼성전자주식회사 | 반도체 패키지 및 그 제조방법 |
KR101719636B1 (ko) * | 2011-01-28 | 2017-04-05 | 삼성전자 주식회사 | 반도체 장치 및 그 제조 방법 |
US8552567B2 (en) * | 2011-07-27 | 2013-10-08 | Micron Technology, Inc. | Semiconductor die assemblies, semiconductor devices including same, and methods of fabrication |
US8937309B2 (en) | 2011-08-08 | 2015-01-20 | Micron Technology, Inc. | Semiconductor die assemblies, semiconductor devices including same, and methods of fabrication |
JP2013179373A (ja) * | 2013-06-20 | 2013-09-09 | Nikon Corp | 積層型半導体装置 |
US9960150B2 (en) * | 2016-06-13 | 2018-05-01 | Micron Technology, Inc. | Semiconductor device assembly with through-mold cooling channel formed in encapsulant |
US10008395B2 (en) | 2016-10-19 | 2018-06-26 | Micron Technology, Inc. | Stacked semiconductor die assemblies with high efficiency thermal paths and molded underfill |
US20180122777A1 (en) * | 2016-10-31 | 2018-05-03 | Raytheon Company | Hybrid micro-circuit device with stacked chip components |
KR20220075507A (ko) | 2020-11-30 | 2022-06-08 | 삼성전자주식회사 | 고 전도 층을 갖는 반도체 패키지 |
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2008
- 2008-03-03 WO PCT/JP2008/053768 patent/WO2008108334A1/ja active Application Filing
- 2008-03-03 KR KR1020097019046A patent/KR101524173B1/ko active IP Right Grant
- 2008-03-03 US US12/529,925 patent/US8436465B2/en active Active
- 2008-03-03 JP JP2009502572A patent/JPWO2008108334A1/ja active Pending
- 2008-03-06 TW TW097107795A patent/TWI424551B/zh active
- 2008-03-06 TW TW102145529A patent/TWI520299B/zh active
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2013
- 2013-03-15 US US13/836,994 patent/US9159640B2/en active Active
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JP2001156247A (ja) * | 1999-11-25 | 2001-06-08 | Seiko Epson Corp | 半導体装置 |
JP2005244143A (ja) * | 2004-03-01 | 2005-09-08 | Hitachi Ltd | 半導体装置 |
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Publication number | Publication date |
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KR20090127278A (ko) | 2009-12-10 |
TWI520299B (zh) | 2016-02-01 |
KR101524173B1 (ko) | 2015-05-29 |
US20130207257A1 (en) | 2013-08-15 |
TWI424551B (zh) | 2014-01-21 |
TW201411805A (zh) | 2014-03-16 |
TW200845355A (en) | 2008-11-16 |
US20100109154A1 (en) | 2010-05-06 |
US8436465B2 (en) | 2013-05-07 |
WO2008108334A1 (ja) | 2008-09-12 |
US9159640B2 (en) | 2015-10-13 |
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