TWI520299B - Semiconductor device and method for manufacturing the same - Google Patents
Semiconductor device and method for manufacturing the same Download PDFInfo
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Description
本發明係關於一種半導體裝置及該半導體裝置之製造方法。
以往已知的一種半導體裝置係具備:形成有電路圖案之基板;及以包圍該基板的方式配置且用以保護該基板的保護構件。在如上所示之半導體裝置中,用以釋出在基板所發生之熱的散熱構件係透過接著層而接著於保護構件的表面。
然而,由於在基板與散熱構件之間介有保護構件及接著層,因此基板的熱係經由保護構件及接著層而傳達至散熱構件。因此,保護構件及接著層將形成熱阻,而有使基板的散熱性惡化的問題點。
本發明係鑑於如上所示情形而研創,其課題在提供一種散熱性佳的半導體裝置及該半導體裝置之製造方法。
為了解決前述課題,本發明之特徵為具備:基板;與該基板相接合,用以釋出該基板之熱的散熱構件;及包圍該基板及前述散熱構件之周圍,以保護前述基板的保護構件,前述散熱構件之至少一部分係自前述保護構件露出。
此外,本發明之特徵係包含:使設有熱傳達用貫穿體的基板、及用以釋出該基板的熱的散熱構件相互重疊;在前述基板及前述散熱構件相互重疊的狀態下,將前述熱傳達用貫穿體與前述散熱構件相結合;以保護構件包圍透過前述熱傳達用貫穿體相互結合之前述基板及前述散熱構件的周圍;藉由去除該保護構件的一部分,使前述散熱構件之至少一部分自前述
保護構件露出。
根據本發明,可將在基板發生的熱在不經由保護構件及接著層的情形下傳達至散熱構件,而可自該散熱構件釋出。藉此可在不導致半導體裝置大型化的情形下,有效釋出在基板所產生的熱。
1‧‧‧半導體晶片
1a‧‧‧表面
1b‧‧‧背面
2‧‧‧熱傳導用貫穿體(導熱孔)
3‧‧‧樹脂接著劑(底部填料)
4‧‧‧保護構件(包覆模具)
4a‧‧‧表面
5‧‧‧中介層
6‧‧‧邏輯LSI
7‧‧‧接著層
8‧‧‧散熱構件
9‧‧‧散熱構件(擋層)
9a‧‧‧表面
9b‧‧‧背面
10‧‧‧半導體裝置
11‧‧‧基板(DRAM)
12‧‧‧板構件
13‧‧‧孔
14‧‧‧熱傳導體
15‧‧‧半導體裝置
16‧‧‧凹凸部
第一圖係顯示本發明實施形態之第1例之半導體裝置之概要圖。
第二圖係顯示第一圖所示半導體裝置之製造方法的示意圖。
第三圖係顯示第一圖所示半導體裝置之製造方法的示意圖。
第四圖係顯示本發明第二實施態樣之半導體裝置之概要圖。
第五圖係顯示本發明第三實施態樣之半導體裝置之概要圖。
第六圖係顯示與本發明之半導體裝置之比較例的圖。
第七圖係顯示在第一圖所示半導體裝置之散熱構件的表面吹放冷卻用的風時的風速與封裝體內最高溫度的關係予以模擬後之結果的曲線圖。
第八圖係顯示設在第一圖所示DRAM之散熱構件之表面之散熱面積與封裝體內最高溫度的關係予以模擬後之結果的曲線圖。
以下使用圖式說明本發明之實施形態之例。在以下說明中,係顯示將本發明適用於具有3次元構造之半導體裝置10之例。
如第一圖所示,本實施例之半導體裝置10係具備DRAM 11。
DRAM 11在圖式之例中,係具有形成有DRAM電路圖案的8片半導體晶片1。各半導體晶片1係分別藉由將由例如矽所構成之圖未示的晶圓在形成有電路圖案之複數個區域予以分離而形成。此外,各半導體晶片1係在各晶片之間架起間隔且層積。此外,各半導體晶片1係藉由用以將該各半導體晶片間作電性連接之圖未示之配線用金屬體,分別予以結合。在各半導體晶片1係以貫通該各半導體晶片的方式,設置作為熱傳達用貫穿體之複數個導熱孔(thermal via)2。各導熱孔2係分別以銅或多晶矽之熱傳導性佳的材料所形成。當以銅形成各導熱孔2時,其熱傳導率為392W/
m℃,當以多晶矽形成各導熱孔2時,其熱傳導率為148W/m℃。
此外,半導體裝置10係具備以包圍DRAM的方式配置的底部填料(underfill)3。底部填料3係由例如脂肪族系環氧樹脂及醚系環氧樹脂之具有接著性的環氧樹脂所構成,在充填各半導體晶片1之間的間隔以補強強度同時,亦具有保護DRAM 11的作用。底部填料3之熱傳導率在圖式之例中為0.7W/m℃。此外,半導體裝置10係具備用以保護各半導體晶片1之作為保護構件的包覆模具(overmold)4。包覆模具4係由環氧樹脂及陶瓷等所構成,以包圍底部填料3之外側的方式配置。包覆模具4的熱傳導率在圖式之例中為0.7W/m℃。
在構成該DRAM 11之經層積的8片半導體晶片1中構成最上層的半導體晶片1上,係配置有散熱構件9。散熱構件9在圖式之例中係由例如金屬及陶瓷等所形成的板構件所構成,以與構成前述最上層之半導體晶片1大致平行的方式配置。此外,散熱構件9係與各導熱孔2相結合。藉此,散熱構件9係透過各導熱孔2而與DRAM 11相接合。
在圖式之例中,底部填料3及包覆模具4之散熱構件9之表面側的部分係予以去除。藉此,散熱構件9的表面由底部填料3及包覆模具4露出於半導體裝置10之外部。在散熱構件9之表面9a設置有凹凸部,藉此使散熱構件9對於外氣的接觸面積變大,因此,散熱面積將變大。
自各半導體晶片1產生的熱係通過各導熱孔2而傳達至散熱構件9,且由該散熱構件之表面9a釋出至大氣。此外,當在DRAM 11結合有例如圖未示之CPU或GPU等邏輯LSI時,由邏輯LSI發生的熱的一部分係通過各導熱孔2而傳達至散熱構件9,且由該散熱構件的表面9a釋出至大氣。為了更加提升散熱效率,亦可在散熱構件9之表面9a流通作為熱媒體的流體,藉由流體而將熱帶走。
以下使用第二圖及第三圖說明第一圖所示半導體裝置10之製造方法。
在製造半導體裝置10時,首先,在與二片半導體晶片1之表面1a之彼此相對應的複數個位置分別藉由蝕刻開出導熱孔2用的孔13,如第二圖(a)所示,以使彼此相對應的各孔13彼此相向的方式配置各半導體晶片1。
此外,在各孔充填由銅或多晶矽等所構成的熱傳導體14。接著,如第二圖(b)所示,藉由施行鍍敷,使充填在各半導體晶片1所對應之各孔13的熱傳導體14彼此相結合。藉此,使兩半導體晶片1彼此相接合。此外,如第二圖(c)所示,藉由分別研磨各半導體晶片1的背面1b,使各半導體晶片1的厚度變薄,藉此使充填在各孔13的熱傳導體14分別露出。藉此,形成貫穿所層積之二片半導體晶片1的複數個導熱孔2,而形成二層層積體。接著,如第二圖(d)所示,在二片半導體晶片1中之一方的背面1b,使形成有各孔13之新的半導體晶片1的表面1a相對向,藉由與上述相同的手段,形成形成有複數個導熱孔2之三層層積體。以下,同樣地,藉由層積8片半導體晶片1,而形成DRAM 11。
在圖式之例中,在形成DRAM 11之後,將DRAM 11與散熱構件9彼此相接合。此時,在散熱構件9的背面9b(參照第二圖(e)),在與該各導熱孔2相對應的位置分別預先形成孔13,而以使背面與構成DRAM 11之最上層的半導體晶片1相對向的方式配置散熱構件9。接著,在散熱構件9之各孔13分別充填熱傳導體14,藉由鍍敷而使充填於設在散熱構件9之孔13的熱傳導體14及各導熱孔2相結合。藉此,如第二圖(e)所示,完成透過各導熱孔2將散熱構件9接合在DRAM 11。亦即,本發明之散熱構件9係構成與構成DRAM 11之複數個半導體晶片1相連續層積的擋層(dummy layer)。此外,當使用可進行鍍敷之導電性金屬作為散熱構件9時,並不需要在擋層9設置孔13。此時,可藉由例如接著劑,將散熱構件9直接接合在最上層的半導體晶片1。
之後,將由DRAM 11及層積在該DRAM之散熱構件9所構成的層積體放入圖未示之模型中,將由液狀之接著性樹脂所構成的底部填料3流入前述模型內,藉此將底部填料3充填於各半導體晶片1間及DRAM 11與散熱構件9之間之同時,以底部填料3包圍前述層積體。之後,使底部填料3硬化,如第三圖(a)所示,完成以底部填料3包覆前述層積體的構造體。更進一步地,將該構造體放入圖未示之模型之中,藉由將由液狀樹脂劑所構成的包覆模具4流入前述模型內,而以包覆模具4包圍前述構造體。之後,
藉由使包覆模具4硬化,如第三圖(b)所示,完成以包覆模具4包覆底部填料3的構造體。
最後,藉由研磨去除該構造體上部的包覆模具4及底部填料3,藉此使散熱構件9的表面9a由包覆模具4及底部填料3露出。此外,藉由熔劑將已進入散熱構件9之表面9a之凹部的底部填料3熔解,完成第三圖(c)所示之半導體裝置10。
根據本實施例,如前述,將散熱構件9接合於構成DRAM 11之複數個半導體晶片1中構成最上層之半導體晶片1,而使散熱構件9的表面由底部填料3及包覆模具4露出。
例如,如第六圖所示之半導體裝置15,將由複數個半導體晶片1所構成的DRAM 11由包覆模具4覆蓋,且透過接著層7而將散熱板8接著在該包覆模具的表面時,DRAM 11的熱係經由包覆模具4及接著層7而傳達至散熱板8。因此,散熱效率為差。若加大散熱板8的尺寸,雖然在某種程度下將使散熱性提升,但是會有無法達成作為層積半導體晶片1之目的之一的將半導體裝置小型化的問題點。此外,藉由增加冷卻用空氣的風速,雖將使散熱性提升,但是會有送風風扇的消耗電力變大,而且噪音變大的問題點。此外,在第六圖所示例中,邏輯LSI6係配置在DRAM 11的下方,邏輯LSI6係透過中介層(interposer)5而連接於DRAM。中介層5係用以取得DRAM與邏輯LSI6之配線的介面。
對此,根據本實施例,可在不用透過包覆模具4及第六圖所示之接著層7的情形下,將在各半導體晶片1所產生的熱傳達至散熱構件9,且由該散熱構件釋出。藉此可更加有效釋出在DRAM 11發生的熱,而不會導致半導體裝置10之大型化。
此外,根據本實施例,如上述,將熱傳導率相較於底部填料3及包覆模具4之熱傳導率大幅提高的複數個導熱孔2設在各半導體晶片1,散熱構件9係與各導熱孔2相結合。因此,可將在各半導體晶片1產生的熱更加確實地傳達至散熱構件9。
此外,根據本實施例,散熱構件9係在複數個半導體晶片1之層積步
驟中,以與各半導體晶片1之層積方法相同的方法,與構成最上層的半導體晶片1相接合。藉此,相較於在DRAM 11的周圍形成有底部填料3及包覆模具4之後,再將散熱構件9接合於DRAM 11的情況,可輕易地將散熱構件9與DRAM 11相組合。
此外,當散熱構件9及各導熱孔2分別由金屬構成時,在將散熱構件9及各導熱孔2相接合時,必須將該等構件加熱。在本實施例中,在DRAM 11周圍形成底部填料3及包覆模具4之前,先進行散熱構件9及各導熱孔2的接合,因此並不會發生因用以接合散熱構件9及導熱孔2的熱,而使樹脂製的底部填料3及包覆模具4熔解。
對此,當在DRAM 11周圍形成底部填料3及包覆模具4之後,使DRAM 11之最上層的半導體晶片1的各導熱孔2露出,而在將散熱構件9接合於該半導體晶片的情況下,當為了進行金屬接合而加熱時,會使樹脂製之底部填料3及包覆模具4熔解。
在第一圖至第三圖所示例中,係顯示在散熱構件9的背面9b形成複數個孔13,分別將熱傳導體14充填於該孔,藉由鍍敷使該熱傳導體與設在構成最上層之半導體晶片1的熱傳導體14相結合之例,但是亦可在散熱構件9之背面9b在不形成孔13的情形下直接接合最上層之半導體晶片1的熱傳導體14來取代之。
此外,在第一圖至第三圖所示例中,係顯示在形成DRAM 11時,將各半導體晶片1彼此相接合之例,但是亦可在將複數個前述晶圓彼此層積的狀態下相接合之後,將該層積後之各晶圓在複數個區域予以分離,藉此形成DRAM 11來取代之。
再者,在第一圖至第三圖所示例中,係顯示使散熱構件9之表面9a由包覆模具4及底部填料3露出之例,亦可以使散熱構件9的側面由包覆模具4及底部填料3露出,或可將散熱構件9的表面9a局部性而非全面性地由包覆模具4及底部填料3露出來取代或加至前例。
第四圖係顯示本發明第二實施態樣之半導體裝置10之概要圖。在該半導體裝置10中,並未設置第一圖至第三圖所示之散熱構件9,而在包覆模
具4的表面4a設有凹凸部16。因此,包覆模具4的表面面積將增加,而使DRAM 11的熱直接釋出。因此,與在包覆模具4的表面4a安裝有散熱構件之習知技術不同,並不需要接著層。藉此與透過接著層及包覆模具而將熱傳至散熱構件的情形相比較,可確實提升散熱效率。
此外,在第四圖中係顯示藉由形成非常大的凹凸部16而使包覆模具4的表面積增大之例,但亦可藉由在包覆模具4的表面4a施行噴砂處理(shot blast)等機械加工或蝕刻處理等化學處理,使包覆模具4的表面4a變得粗糙,藉此可增大包覆模具4的表面積。
第五圖係顯示本發明第三實施態樣之半導體裝置10之概要圖。在該半導體裝置10中,係在第四圖所示實施態樣之包覆模具4的表面4a上,以在該表面隔著間隔而且與該表面大致呈平行的方式配置有板構件12。當在包覆模具4與板構件12之間流動冷卻用流體時,會發生亂流。藉此,與因自然對流所造成的液體流、或僅在包覆模具4的表面流動流體時的層流相較,可提升熱傳達效率。
此外,在第五圖中,係以與包覆模具4之表面4a大致平行的方式打開間隔設置板構件12,但是亦可以與如第一圖所示所形成之DRAM 11之散熱構件9之表面9a大致平行的方式打開間隔,設置板構件12,而在散熱構件9與板構件12之間流動冷卻用流體。
再者,在第一至第三實施態樣中係顯示以具有複數個半導體晶片1之DRAM 11構成基板之例,但亦可以具有單一半導體晶片1之DRAM 11構成基板來取代之。
更進一步地,在第一至第三實施形態中係顯示半導體裝置10具備DRAM 11之例,亦可以將本發明適用於具備例如CPU、GPU等DRAM 11以外之基板的半導體裝置取代或加至前例。此時,可將CPU及GPU如本實施例之DRAM 11所示藉由層積複數個半導體晶片而形成。
此外,在第一至第三實施態樣中係顯示將由有別於複數個半導體晶片1之構件所構成的散熱構件9接合於半導體晶片1之例,但亦可利用具有用以將其他各半導體晶片1之熱釋出之散熱功能的半導體晶片1構成所層積
之複數個半導體晶片1中構成2個最端層之2個半導體晶片1之其中一方,而可將該半導體晶片作為散熱構件加以使用。
[實施例]
以下說明本發明之實施例。第七圖所示曲線圖係表示將冷卻用的風吹在第一圖所示DRAM 11之散熱構件9的表面時之風速與DRAM 11之封裝體內最高溫度的關係予以模擬後之結果的曲線圖。模擬條件係在第一圖之DRAM 11中,將散熱構件9之表面9a之散熱面積設為0.000144m2,且沿著散熱構件9之表面9a吹放冷卻用的風。其中,當風速為0.022m/sec時,風量係未使用冷卻用風扇之自然對流的等級(level),風的方向在全方位為均等。
第八圖所示曲線圖係表示將設在第一圖所示DRAM 11之散熱構件9之表面9a之散熱面積與封裝體內最高溫溫度之關係予以模擬後之結果的曲線圖。模擬條件係設為在第一圖之DRAM 11中,以使冷卻用的風不會由外部吹在散熱構件9之表面9a的方式,將以自然對流所發生的風(風速0.022m/sec)吹在散熱構件9之表面9a,且該風的方向在全方位為均等。
由第七圖及第八圖可知,在第一圖之DRAM 11中,當散熱構件9之表面9a的散熱面積為0.000144m2時,若風速約0.5m/sec以上的風不吹在散熱構件9之表面9a,封裝體內最高溫度將不會在100℃以下。但是,藉由將散熱構件9之表面9a的散熱面積設在0.00065m2以上,在風不會由外部吹在散熱構件9之表面9a的情形下,可僅以藉由自然對流所發生的風,將封裝體內最高溫度設為100℃以下。
1‧‧‧半導體晶片
2‧‧‧熱傳導用貫穿體(導熱孔)
3‧‧‧樹脂接著劑(底部填料)
4‧‧‧保護構件(包覆模具)
9‧‧‧散熱構件(擋層)
9a‧‧‧表面
10‧‧‧半導體裝置
11‧‧‧基板(DRAM)
Claims (7)
- 一種半導體裝置,包含:半導體晶片;貫穿構件,其係貫穿前述基板,用以傳導熱;散熱構件,其係與前述貫穿構件相結合,用以傳導熱及釋出前述半導體晶片之熱;及底部填料,其包覆前述半導體晶片及前述散熱構件並填充於前述半導體晶片及前述散熱構件之間,其中前述散熱構件之一部分係由前述底部填料露出於外部大氣。
- 如申請專利範圍第1項之半導體裝置,其中更包含保護構件,其係包圍前述半導體晶片及前述散熱構件,用以保護前述半導體晶片;其中前述散熱構件之至少一部分係由前述保護構件露出。
- 如申請專利範圍第1項之半導體裝置,其中前述貫穿構件之熱傳導率比前述保護構件之熱傳導率更高。
- 如申請專利範圍第1項之半導體裝置,其中更包含板構件,該板構件配置於前述散熱構件之上方,且在前述板構件與前述散熱構件之間形成間隔,前述板構件與前述散熱構件實質上平行。
- 如申請專利範圍第1項之半導體裝置,其中前述複數個半導體晶片被至少一個間隔分離;前述半導體裝置更包含樹脂接著劑,該樹脂接著劑包圍前述基板且充填前述間隔,其中前述散熱構件至少一部分由前述樹脂接著劑露出。
- 一種半導體裝置,包含:基板;貫穿構件,其係貫穿前述基板;及保護構件,其係包圍前述基板,前述保護構件之表面包含複數個凹凸部;其中前述保護構件之一部分與前述貫穿構件接觸,其中更包含板構件,該板構件配置於前述複數個凹凸部之上方,且前述板構件與前述保護構件之前述表面之間形成間隔,前述板構件與前述保護構件之前述表 面實質上平行。
- 如申請專利範圍第1、2、3及4至6項中任一項之半導體裝置,其中前述基板為DRAM。
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2008
- 2008-03-03 JP JP2009502572A patent/JPWO2008108334A1/ja active Pending
- 2008-03-03 KR KR1020097019046A patent/KR101524173B1/ko active IP Right Grant
- 2008-03-03 US US12/529,925 patent/US8436465B2/en active Active
- 2008-03-03 WO PCT/JP2008/053768 patent/WO2008108334A1/ja active Application Filing
- 2008-03-06 TW TW102145529A patent/TWI520299B/zh active
- 2008-03-06 TW TW097107795A patent/TWI424551B/zh active
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US20100109154A1 (en) | 2010-05-06 |
US9159640B2 (en) | 2015-10-13 |
US20130207257A1 (en) | 2013-08-15 |
US8436465B2 (en) | 2013-05-07 |
KR101524173B1 (ko) | 2015-05-29 |
WO2008108334A1 (ja) | 2008-09-12 |
TWI424551B (zh) | 2014-01-21 |
JPWO2008108334A1 (ja) | 2010-06-17 |
KR20090127278A (ko) | 2009-12-10 |
TW200845355A (en) | 2008-11-16 |
TW201411805A (zh) | 2014-03-16 |
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