KR20220075507A - 고 전도 층을 갖는 반도체 패키지 - Google Patents

고 전도 층을 갖는 반도체 패키지 Download PDF

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Publication number
KR20220075507A
KR20220075507A KR1020200163646A KR20200163646A KR20220075507A KR 20220075507 A KR20220075507 A KR 20220075507A KR 1020200163646 A KR1020200163646 A KR 1020200163646A KR 20200163646 A KR20200163646 A KR 20200163646A KR 20220075507 A KR20220075507 A KR 20220075507A
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South Korea
Prior art keywords
semiconductor chip
conductivity layer
layer
encapsulant
disposed
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KR1020200163646A
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English (en)
Inventor
김선재
강은실
김대현
서선경
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삼성전자주식회사
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Priority to KR1020200163646A priority Critical patent/KR20220075507A/ko
Priority to US17/332,471 priority patent/US11948851B2/en
Publication of KR20220075507A publication Critical patent/KR20220075507A/ko

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Abstract

반도체 패키지는 제1 반도체 칩 상의 제2 반도체 칩을 포함한다. 상기 제1 반도체 칩 및 상기 제2 반도체 칩 사이에 다수의 내부 단자가 배치된다. 상기 제1 반도체 칩 및 상기 제2 반도체 칩 사이에 고 전도 층(High Thermal Conductivity Layer)이 배치된다. 상기 고 전도 층 상에 배치되고 상기 제2 반도체 칩에 접촉된 봉지재가 제공된다. 상기 제1 반도체 칩, 상기 고 전도 층, 및 상기 봉지재의 측벽들은 실질적으로 동일한 평면을 이룬다.

Description

고 전도 층을 갖는 반도체 패키지{SEMICONDUCTOR PACKAGE INCLUDING HIGH THERMAL CONDUCTIVITY LAYER}
고 전도 층을 갖는 반도체 패키지 및 그 형성 방법에 관한 것이다.
전자 시스템의 경박단소화에 따라 다수의 반도체 칩을 탑재할 수 있는 다양한 반도체 패키지들이 연구되고 있다. 상기 다수의 반도체 칩의 각각은 동작 중 주변 환경보다 높은 온도의 열이 발생될 수 있다. 상기 다수의 반도체 칩에서 발생하는 열은 상기 전자 시스템의 오 동작을 유발하고 상기 전자 시스템의 수명에 나쁜 영향을 준다.
본 발명 기술적 사상의 실시예들에 따른 과제는 효율적인 방열 특성을 갖는 반도체 패키지 및 그 형성 방법을 제공하는데 있다.
본 발명 기술적 사상의 실시예들에 따른 반도체 패키지는 제1 반도체 칩 상의 제2 반도체 칩을 포함한다. 상기 제1 반도체 칩 및 상기 제2 반도체 칩 사이에 다수의 내부 단자가 배치된다. 상기 제1 반도체 칩 및 상기 제2 반도체 칩 사이에 고 전도 층(High Thermal Conductivity Layer)이 배치된다. 상기 고 전도 층 상에 배치되고 상기 제2 반도체 칩에 접촉된 봉지재가 제공된다. 상기 제1 반도체 칩, 상기 고 전도 층, 및 상기 봉지재의 측벽들은 실질적으로 동일한 평면을 이룬다.
본 발명 기술적 사상의 실시예들에 따른 반도체 패키지는 활성 영역 및 상기 활성 영역의 측면들에 연속된(in continuity with) 다수의 스크라이브 레인(Scribe Lane)을 갖는 배선 구조체를 포함한다. 상기 배선 구조체 상에 반도체 칩이 배치된다. 상기 배선 구조체 및 상기 반도체 칩 사이에 다수의 내부 단자가 배치된다. 상기 배선 구조체 및 상기 반도체 칩 사이에 배치되고 상기 활성 영역 및 상기 다수의 스크라이브 레인에 접촉된 고 전도 층(High Thermal Conductivity Layer)이 제공된다. 상기 배선 구조체 및 상기 고 전도 층 상에 배치되고 상기 반도체 칩에 접촉된 봉지재가 제공된다.
본 발명 기술적 사상의 실시예들에 따른 반도체 패키지는 배선 구조체 상의 반도체 칩을 포함한다. 상기 배선 구조체 및 상기 반도체 칩 사이에 다수의 내부 단자가 배치된다. 상기 배선 구조체 및 상기 반도체 칩 사이에 고 전도 층(High Thermal Conductivity Layer)이 배치된다. 상기 고 전도 층 상에 배치되고 상기 반도체 칩에 접촉된 봉지재가 제공된다. 상기 배선 구조체, 상기 고 전도 층, 및 상기 봉지재의 측벽들은 실질적으로 동일한 평면을 이룬다. 상기 고 전도 층의 최 상단은 상기 반도체 칩의 최 하단보다 높은 레벨에 배치된다. 상기 고 전도 층의 최 상단은 상기 반도체 칩의 최 상단보다 낮은 레벨에 배치된다. 상기 고 전도 층은 상기 반도체 칩의 측면에 접촉된다. 상기 고 전도 층 및 상기 반도체 칩의 최대 접촉 높이는 제1 길이이고, 상기 반도체 칩의 두께는 제2 길이이며, 상기 제1 길이는 상기 제2 길이의 절반보다 크다.
본 발명 기술적 사상의 실시예들에 따르면, 배선 구조체 및 반도체 칩 사이를 채우고 상기 배선 구조체의 스크라이브 레인(Scribe Lane) 상에 연장된 고 전도 층(High Thermal Conductivity Layer)이 제공된다. 상기 고 전도 층은 상기 배선 구조체 및 상기 반도체 칩에서 발생하는 열을 분산하고 외부로 방출하는 역할을 할 수 있다. 효율적인 방열 특성을 갖는 반도체 패키지를 구현할 수 있다.
도 1 내지 도 8은 본 발명 기술적 사상의 실시예들에 따른 반도체 패키지를 설명하기 위한 단면도들이다.
도 9, 도 10, 도 11, 도 14, 및 도 19는 본 발명 기술적 사상의 실시예들에 따른 반도체 패키지 형성 방법들을 설명하기 위한 단면도들이다.
도 12 및 도 13은 도 11의 일부분을 보여주는 부분도들이다.
도 15 내지 도 18은 도 14의 일부분을 보여주는 부분도들이다.
도 1 내지 도 8은 본 발명 기술적 사상의 실시예들에 따른 반도체 패키지를 설명하기 위한 단면도들이다.
도 1을 참조하면, 본 발명 기술적 사상의 실시예들에 따른 반도체 패키지는 배선 구조체(10), 제1 반도체 칩(40), 다수의 제1 내부 단자(53), 다수의 제1 내부 열 분산 단자(54), 제1 고 전도 층(High Thermal Conductivity Layer; 58), 다수의 외부 단자(63), 적어도 하나의 외부 열 분산 단자(64), 및 봉지재(67)를 포함할 수 있다.
일 실시예에서, 상기 배선 구조체(10)는 로직 칩(Logic Chip), 버퍼 칩(Buffer Chip), 컨트롤러 칩(Controller Chip), 애플리케이션 프로세서 칩(Application Processor Chip), 인터포저 칩(Interposer Chip), 휘발성 메모리 칩(Volatile Memory Chip), 비-휘발성 메모리 칩(Non-Volatile Memory Chip), 또는 이들의 조합과 같은 반도체 칩을 포함할 수 있다. 상기 배선 구조체(10)는 인쇄 회로 기판, 인터포저 기판, 상기 반도체 칩, 또는 이들의 조합을 포함할 수 있다. 이하에서는 설명의 편의를 위하여, 상기 배선 구조체(10)가 상기 로직 칩(Logic Chip)인 경우를 상정하여 설명하기로 한다.
일 실시예에서, 상기 제1 반도체 칩(40)은 메모리 칩(Memory Chip), 로직 칩(Logic Chip), 버퍼 칩(Buffer Chip), 컨트롤러 칩(Controller Chip), 애플리케이션 프로세서 칩(Application Processor Chip), 인터포저 칩(Interposer Chip), 또는 이들의 조합을 포함할 수 있다. 상기 제1 반도체 칩(40)은 휘발성 메모리 칩(Volatile Memory Chip), 비-휘발성 메모리 칩(Non-Volatile Memory Chip), 또는 이들의 조합과 같은 상기 메모리 칩을 포함할 수 있다. 이하에서는 설명의 편의를 위하여, 상기 제1 반도체 칩(40)이 상기 메모리 칩인 경우를 상정하여 설명하기로 한다.
상기 배선 구조체(10)는 활성 영역(11) 및 다수의 스크라이브 레인(Scribe Lane; SL1, SL2)을 포함할 수 있다. 상기 다수의 스크라이브 레인(SL1, SL2)의 각각은 상기 활성 영역(11)의 측면들에 연속될(in continuity with) 수 있다. 상기 활성 영역(11)은 상기 다수의 스크라이브 레인(SL1, SL2) 사이에 배치될 수 있다. 일 실시예에서, 상기 활성 영역(11) 및 상기 다수의 스크라이브 레인(SL1, SL2)은 단결정 실리콘 층과 같은 반도체 층을 포함할 수 있다.
상기 활성 영역(11) 내에 다수의 제1 관통 전극(13) 및 적어도 하나의 제1 열 분산 관통 전극(14)이 배치될 수 있다. 상기 다수의 제1 관통 전극(13) 및 상기 적어도 하나의 제1 열 분산 관통 전극(14)은 서로 이격될 수 있다. 상기 다수의 제1 관통 전극(13) 및 상기 적어도 하나의 제1 열 분산 관통 전극(14)의 각각은 상기 활성 영역(11)을 수직하게 관통할 수 있다. 상기 다수의 제1 관통 전극(13) 및 상기 적어도 하나의 제1 열 분산 관통 전극(14)은 Cu, W, WN, Ni, Co, Al, Ti, TiN, Ta, TaN, Ag, Pt, Au, Ru, Cr, Sn, 또는 이들의 조합과 같은 도전성 물질(Conductive Material)을 포함할 수 있다. 상기 적어도 하나의 제1 열 분산 관통 전극(14)은 상기 다수의 제1 관통 전극(13)과 실질적으로 동시에 형성된 실질적으로 동일한 물질 층을 포함할 수 있다. 상기 적어도 하나의 제1 열 분산 관통 전극(14)은 상기 다수의 제1 관통 전극(13)의 각각과 실질적으로 동일한 크기를 가질 수 있다. 상기 적어도 하나의 제1 열 분산 관통 전극(14)은 생략될 수 있다.
상기 활성 영역(11)의 하면 상에 상기 다수의 외부 단자(63) 및 상기 적어도 하나의 외부 열 분산 단자(64)가 배치될 수 있다. 상기 다수의 외부 단자(63)의 각각은 상기 다수의 제1 관통 전극(13) 중 대응하는 하나에 전기적으로 접속될 수 있다. 상기 적어도 하나의 외부 열 분산 단자(64)는 상기 적어도 하나의 제1 열 분산 관통 전극(14)에 전기적으로 접속될 수 있다.
상기 다수의 외부 단자(63)는 Sn, Ag, Cu, W, WN, Ni, Co, Al, Ti, TiN, Ta, TaN, Pt, Au, Ru, Cr, 또는 이들의 조합과 같은 도전성 물질(Conductive Material)을 포함할 수 있다. 상기 다수의 외부 단자(63)의 각각은 도전성 범프, 도전성 포스트, 도전성 핀, 도전성 필라, 솔더 볼, 또는 이들의 조합을 포함할 수 있다. 상기 적어도 하나의 외부 열 분산 단자(64)는 상기 다수의 외부 단자(63)의 각각과 유사한 구성을 포함할 수 있다. 일 실시예에서, 상기 적어도 하나의 외부 열 분산 단자(64)는 상기 다수의 외부 단자(63)의 각각과 실질적으로 동시에 형성된 실질적으로 동일한 물질을 포함할 수 있다. 상기 적어도 하나의 외부 열 분산 단자(64)는 상기 다수의 외부 단자(63)의 각각과 실질적으로 동일한 크기를 가질 수 있다.
상기 제1 반도체 칩(40)은 상기 배선 구조체(10) 상에 배치될 수 있다. 상기 제1 반도체 칩(40)의 수평 폭은 상기 배선 구조체(10)의 수평 폭보다 좁을 수 있다. 상기 다수의 제1 내부 단자(53) 및 상기 다수의 제1 내부 열 분산 단자(54)는 상기 제1 반도체 칩(40) 및 상기 배선 구조체(10) 사이에 배치될 수 있다. 상기 제1 고 전도 층(High Thermal Conductivity Layer; 58)은 상기 배선 구조체(10) 및 상기 제1 반도체 칩(40) 사이에 배치될 수 있다. 상기 제1 고 전도 층(58)은 상기 배선 구조체(10) 상을 덮을 수 있다. 상기 제1 고 전도 층(58)은 상기 제1 반도체 칩(40)의 측면들을 부분적으로 덮을 수 있다. 상기 다수의 제1 내부 단자(53) 및 상기 다수의 제1 내부 열 분산 단자(54)의 각각은 상기 제1 고 전도 층(58)을 관통하여 상기 배선 구조체(10) 및 상기 제1 반도체 칩(40)에 접촉될 수 있다.
상기 다수의 제1 내부 단자(53)는 Sn, Ag, Cu, W, WN, Ni, Co, Al, Ti, TiN, Ta, TaN, Pt, Au, Ru, Cr, 또는 이들의 조합과 같은 도전성 물질(Conductive Material)을 포함할 수 있다. 상기 다수의 제1 내부 단자(53)의 각각은 도전성 범프, 도전성 포스트, 도전성 핀, 도전성 필라, 솔더 볼, 또는 이들의 조합을 포함할 수 있다. 상기 다수의 제1 내부 단자(53)의 각각은 상기 다수의 제1 관통 전극(13) 중 대응하는 하나에 접속될 수 있다.
상기 다수의 제1 내부 단자(53)는 제1 피치(P1)를 갖도록 배치될 수 있다. 상기 다수의 제1 내부 단자(53) 각각의 최대 수평 폭은 제1 폭(W1)일 수 있다. 상기 다수의 제1 내부 단자(53) 사이의 최소 간격은 제2 폭(W2)일 수 있다. 상기 제1 피치(P1)는 상기 제1 폭(W1) 및 상기 제2 폭(W2)의 합에 해당될 수 있다. 상기 제1 피치(P1)는 1㎛ 내지 80㎛ 일 수 있다. 일 실시예에서, 상기 제1 피치(P1)는 약10㎛ 내지 약25㎛ 일 수 있다.
상기 다수의 제1 내부 열 분산 단자(54)의 각각은 상기 다수의 제1 내부 단자(53)의 각각과 유사한 구성을 포함할 수 있다. 일 실시예에서, 상기 다수의 제1 내부 열 분산 단자(54)의 각각은 상기 다수의 제1 내부 단자(53)의 각각과 실질적으로 동시에 형성된 실질적으로 동일한 물질을 포함할 수 있다. 상기 다수의 제1 내부 열 분산 단자(54)의 각각은 상기 다수의 제1 내부 단자(53)와 이격될 수 있다. 상기 다수의 제1 내부 열 분산 단자(54)의 각각은 상기 다수의 제1 내부 단자(53)의 각각과 실질적으로 동일한 크기를 가질 수 있다. 상기 다수의 제1 내부 열 분산 단자(54) 및 상기 다수의 제1 내부 단자(53)는 상기 제1 피치(P1)를 갖도록 배치될 수 있다. 상기 다수의 제1 내부 열 분산 단자(54) 중 적어도 하나는 상기 적어도 하나의 제1 열 분산 관통 전극(14)에 접속될 수 있다.
상기 제1 고 전도 층(High Thermal Conductivity Layer; 58)의 열전도율은 1 W/mK 이상일 수 있다. 일 실시예에서, 상기 제1 고 전도 층(58)의 열전도율은 약1 W/mK 내지 약5 W/mK 일 수 있다. 상기 제1 고 전도 층(High Thermal Conductivity Layer; 58)은 필러(Filler) 및 레진(Resin)을 갖는 언더필(Under Fill) 또는 액상 봉지재(Liquid Encapsulant)를 포함할 수 있다. 상기 필러(Filler)는 높은 열전도율을 갖는 물질을 포함할 수 있다. 상기 필러(Filler)는 유동성 확보에 유리한 구상 필러를 포함할 수 있다. 상기 필러(Filler)는 알루미늄 산화물(Al2O3), 알루미늄 질화물(AlN), 붕소 질화물(BN), 실리콘 산화물(SiO2), 또는 이들의 조합을 포함할 수 있다. 상기 필러(Filler)는 0.1㎛ 내지 10㎛ 의 직경을 갖는 것일 수 있다. 상기 필러(Filler)의 직경은 공정 효율에 기반하여 선택될 수 있다. 상기 필러(Filler)의 직경은 상기 배선 구조체(10) 및 상기 제1 반도체 칩(40) 사이의 최소 간격 및 유동성에 기반하여 선택될 수 있다. 일 실시예에서, 상기 필러(Filler)는 약0.7㎛ 내지 약3㎛ 의 직경을 갖는 것일 수 있다.
일 실시예에서, 상기 알루미늄 산화물(Al2O3)은 α-ray 방출이 적은 Low α-ray 방출 등급(Emission rate: 0.01 CPH/cm2 이하) 이상의 것이 사용될 수 있다. 상기 알루미늄 산화물(Al2O3)은 알파(α)상, 감마(γ)상, 다결정, 또는 이들의 조합을 포함할 수 있다. 상기 레진(Resin)은 Mesogen Pi-Pi(π-π) 스태킹(Stacking) 가능한 biphenyl, naphthyl, anthracenyl 등의 다-방향족(multi-aromatic)을 뼈대 구조(backbone structure)로 가지는 LCERs(liquid crystalline epoxy resins)을 포함할 수 있다. 예를들면, biphenyl의 경우 Japan Epoxy Resins 사의 YX-4000(K), YX-4000H(K), naphthyl의 경우 DIC 사의 HP4032D, HP4032SS 등을 포함할 수 있다.
상기 제1 고 전도 층(High Thermal Conductivity Layer; 58)은 상기 배선 구조체(10) 및 상기 제1 반도체 칩(40) 사이를 채우고 상기 제1 반도체 칩(40)의 측면들 상에 연장될 수 있다. 일 실시예에서, 상기 제1 고 전도 층(58)은 상기 배선 구조체(10)의 일면을 완전히 덮을 수 있다. 상기 제1 고 전도 층(58)은 상기 활성 영역(11) 및 상기 다수의 스크라이브 레인(Scribe Lane; SL1, SL2)을 완전히 덮을 수 있다. 상기 제1 고 전도 층(58)은 상기 활성 영역(11) 및 상기 다수의 스크라이브 레인(SL1, SL2)에 직접적으로 접촉될 수 있다.
상기 제1 고 전도 층(58)의 최 상단은 상기 제1 반도체 칩(40)의 최 하단보다 높은 레벨에 형성될 수 있다. 상기 제1 고 전도 층(58)은 상기 제1 반도체 칩(40)의 측면들에 직접적으로 접촉될 수 있다. 상기 제1 반도체 칩(40)의 측면과 상기 제1 고 전도 층(58)의 최대 접촉 높이는 제1 길이(D1)를 보일 수 있다. 상기 제1 반도체 칩(40)의 두께는 제2 길이(D2)를 보일 수 있다. 상기 제1 길이(D1)는 상기 제2 길이(D2)의 절반보다 클 수 있다. 상기 제1 고 전도 층(58)의 최 상단은 상기 제1 반도체 칩(40)의 최 상단보다 낮은 레벨에 형성될 수 있다. 상기 제1 고 전도 층(58)의 상면은 다양한 프로파일을 보일 수 있다. 상기 제1 고 전도 층(58)의 상면은 경사면을 포함할 수 있다. 일 실시예에서, 상기 제1 고 전도 층(58)의 상면은 상기 제1 반도체 칩(40)에서 멀리 떨어질수록 낮은 레벨에 형성될 수 있다.
상기 배선 구조체(10) 및 상기 제1 반도체 칩(40) 사이의 최소 간격은 제3 길이(D3)를 보일 수 있다. 상기 제3 길이(D3)는 1㎛ 내지 50㎛ 일 수 있다. 일 실시예에서, 상기 제3 길이(D3)는 약10㎛ 내지 약20㎛ 일 수 있다. 상기 봉지재(67)는 상기 제1 고 전도 층(58) 상에 배치될 수 있다. 일 실시예에서, 상기 봉지재(67)는 에폭시 몰딩 컴파운드(Epoxy Molding Compound)를 포함할 수 있다. 상기 봉지재(67)는 상기 제1 고 전도 층(58)의 상면 및 상기 제1 반도체 칩(40)의 측면에 접촉될 수 있다.
일 실시예에서, 상기 배선 구조체(10), 상기 제1 고 전도 층(58), 및 상기 봉지재(67)의 측면들은 실질적으로 동일한 평면을 이룰 수 있다. 제1 스크라이브 레인(SL1), 상기 제1 고 전도 층(58), 및 상기 봉지재(67)의 측면들은 수직 정렬될 수 있다. 상기 제1 스크라이브 레인(SL1), 상기 제1 고 전도 층(58), 및 상기 봉지재(67)의 측면들은 실질적으로 동일한 평면을 이룰 수 있다. 제2 스크라이브 레인(SL2), 상기 제1 고 전도 층(58), 및 상기 봉지재(67)의 측면들은 수직 정렬될 수 있다. 상기 제2 스크라이브 레인(SL2), 상기 제1 고 전도 층(58), 및 상기 봉지재(67)의 측면들은 실질적으로 동일한 평면을 이룰 수 있다. 상기 배선 구조체(10), 상기 제1 고 전도 층(58), 및 상기 봉지재(67)의 측면들은 노출될 수 있다.
상기 다수의 제1 관통 전극(13), 상기 다수의 제1 내부 단자(53), 및 상기 다수의 외부 단자(63)는 신호 전달, 전원 공급, 및 접지와 같은 상기 배선 구조체(10) 및 상기 제1 반도체 칩(40)의 구동에 필요한 것일 수 있다. 상기 적어도 하나의 제1 열 분산 관통 전극(14), 상기 다수의 제1 내부 열 분산 단자(54), 및 상기 적어도 하나의 외부 열 분산 단자(64)는 상기 배선 구조체(10) 및 상기 제1 반도체 칩(40)에서 발생하는 열을 분산하고 외부로 방출하는 역할을 할 수 있다. 상기 제1 고 전도 층(58)은 상기 배선 구조체(10), 상기 제1 반도체 칩(40), 상기 다수의 제1 내부 단자(53), 및 상기 다수의 제1 내부 열 분산 단자(54)에 직접적으로 접촉될 수 있다. 상기 제1 고 전도 층(58)은 상기 배선 구조체(10) 및 상기 제1 반도체 칩(40)에서 발생하는 열을 분산하고 외부로 방출하는 역할을 할 수 있다.
도 2 내지 도 4를 참조하면, 제1 고 전도 층(58)의 상면 및 봉지재(67)의 접촉면은 상기 제1 고 전도 층(58)의 유동성 및 형성 방법에 기반하여 다양한 프로파일을 보일 수 있다. 상기 제1 고 전도 층(58)의 상면은 경사면을 포함할 수 있다. 일 실시예에서, 상기 제1 고 전도 층(58)의 상면은 제1 반도체 칩(40)에서 멀리 떨어질수록 낮은 레벨에 형성될 수 있다.
도 5를 참조하면, 상기 다수의 외부 단자(도 1의 63) 및 상기 적어도 하나의 외부 열 분산 단자(도 1의 64)는 생략될 수 있다. 일 실시예에서, 상기 배선 구조체(10)는 인쇄 회로 기판, 인터포저 기판, 상기 반도체 칩, 또는 이들의 조합을 포함할 수 있다. 예를들면, 상기 배선 구조체(10)는 패키지 기판 및/또는 메인 보드와 같은 인쇄 회로 기판을 포함할 수 있다. 상기 다수의 제1 관통 전극(도 1의 13) 및 상기 적어도 하나의 제1 열 분산 관통 전극(도 1의 14)은 생략될 수 있다. 일 실시예에서, 활성 영역(11) 내에 다수의 수평 배선(도시하지 않음) 및 다수의 수직 배선(도시하지 않음)이 배치될 수 있다.
도 6을 참조하면, 제1 고 전도 층(High Thermal Conductivity Layer; 58)은 활성 영역(11) 및 제1 반도체 칩(40) 사이를 채우고 다수의 스크라이브 레인(SL1, SL2) 상에 연장될 수 있다. 상기 제1 고 전도 층(58)은 제1 스크라이브 레인(SL1) 및 제2 스크라이브 레인(SL2)의 상면들에 직접적으로 접촉될 수 있다. 봉지재(67)는 상기 제1 고 전도 층(58) 및 배선 구조체(10) 상을 덮을 수 있다. 상기 봉지재(67)는 상기 제1 스크라이브 레인(SL1) 및 상기 제2 스크라이브 레인(SL2)의 상면들에 직접적으로 접촉될 수 있다.
상기 배선 구조체(10) 및 상기 봉지재(67)의 측면들은 실질적으로 동일한 평면을 이룰 수 있다. 상기 제1 스크라이브 레인(SL1) 및 상기 봉지재(67)의 측면들은 수직 정렬될 수 있다. 상기 제1 스크라이브 레인(SL1) 및 상기 봉지재(67)의 측면들은 실질적으로 동일한 평면을 이룰 수 있다. 상기 제2 스크라이브 레인(SL2) 및 상기 봉지재(67)의 측면들은 수직 정렬될 수 있다. 상기 제2 스크라이브 레인(SL2) 및 상기 봉지재(67)의 측면들은 실질적으로 동일한 평면을 이룰 수 있다.
도 7을 참조하면, 제1 고 전도 층(High Thermal Conductivity Layer; 58)은 활성 영역(11) 및 제1 반도체 칩(40) 사이를 채우고, 제2 스크라이브 레인(SL2)상을 덮고, 제1 스크라이브 레인(SL1) 상을 부분적으로 덮을 수 있다. 상기 제1 고 전도 층(58)은 상기 제1 스크라이브 레인(SL1)의 상면에 직접적으로 접촉될 수 있다.
상기 제1 스크라이브 레인(SL1) 및 상기 봉지재(67)의 측면들은 수직 정렬될 수 있다. 상기 제1 스크라이브 레인(SL1) 및 상기 봉지재(67)의 측면들은 실질적으로 동일한 평면을 이룰 수 있다. 상기 제2 스크라이브 레인(SL2), 상기 제1 고 전도 층(58), 및 상기 봉지재(67)의 측면들은 수직 정렬될 수 있다. 상기 제2 스크라이브 레인(SL2), 상기 제1 고 전도 층(58), 및 상기 봉지재(67)의 측면들은 실질적으로 동일한 평면을 이룰 수 있다.
도 8을 참조하면, 본 발명 기술적 사상의 실시예들에 따른 반도체 패키지는 배선 구조체(10), 제1 반도체 칩(40), 다수의 제1 내부 단자(53), 다수의 제1 내부 열 분산 단자(54), 제1 고 전도 층(High Thermal Conductivity Layer; 58), 제2 반도체 칩(81), 다수의 제2 내부 단자(73), 다수의 제2 내부 열 분산 단자(74), 제2 고 전도 층(77), 제3 반도체 칩(82), 다수의 제3 내부 단자(87), 다수의 제3 내부 열 분산 단자(88), 제3 고 전도 층(78), 제4 반도체 칩(83), 다수의 제4 내부 단자(93), 다수의 제4 내부 열 분산 단자(94), 제4 고 전도 층(79), 다수의 외부 단자(63), 적어도 하나의 외부 열 분산 단자(64), 및 봉지재(67)를 포함할 수 있다.
일 실시예에서, 상기 제1 반도체 칩(40), 상기 제2 반도체 칩(81), 상기 제3 반도체 칩(82), 및 상기 제4 반도체 칩(83)의 각각은 메모리 칩(Memory Chip), 로직 칩(Logic Chip), 버퍼 칩(Buffer Chip), 컨트롤러 칩(Controller Chip), 애플리케이션 프로세서 칩(Application Processor Chip), 인터포저 칩(Interposer Chip), 또는 이들의 조합을 포함할 수 있다. 상기 제1 반도체 칩(40), 상기 제2 반도체 칩(81), 상기 제3 반도체 칩(82), 및 상기 제4 반도체 칩(83)의 각각은 휘발성 메모리 칩(Volatile Memory Chip), 비-휘발성 메모리 칩(Non-Volatile Memory Chip), 또는 이들의 조합과 같은 상기 메모리 칩을 포함할 수 있다.
상기 제1 반도체 칩(40)을 관통하는 다수의 제2 관통 전극(71) 및 적어도 하나의 제2 열 분산 관통 전극(72)이 배치될 수 있다. 상기 제2 반도체 칩(81)을 관통하는 다수의 제3 관통 전극(85) 및 적어도 하나의 제3 열 분산 관통 전극(86)이 배치될 수 있다. 상기 제3 반도체 칩(82)을 관통하는 다수의 제4 관통 전극(91) 및 적어도 하나의 제4 열 분산 관통 전극(92)이 배치될 수 있다.
상기 다수의 제2 내부 단자(73), 상기 다수의 제3 내부 단자(87), 및 상기 다수의 제4 내부 단자(93)는 상기 다수의 제1 내부 단자(53)와 유사한 구성을 포함할 수 있다. 상기 다수의 제2 내부 열 분산 단자(74), 상기 다수의 제3 내부 열 분산 단자(88), 및 상기 다수의 제4 내부 열 분산 단자(94)는 상기 다수의 제1 내부 열 분산 단자(54)와 유사한 구성을 포함할 수 있다.
상기 다수의 제2 관통 전극(71), 상기 다수의 제3 관통 전극(85), 및 상기 다수의 제4 관통 전극(91)은 상기 다수의 제1 관통 전극(13)과 유사한 구성을 포함할 수 있다. 상기 적어도 하나의 제2 열 분산 관통 전극(72), 상기 적어도 하나의 제3 열 분산 관통 전극(86), 및 상기 적어도 하나의 제4 열 분산 관통 전극(92)은 상기 적어도 하나의 제1 열 분산 관통 전극(14)과 유사한 구성을 포함할 수 있다.
상기 제2 고 전도 층(77), 상기 제3 고 전도 층(78), 및 상기 제4 고 전도 층(79)의 각각은 상기 제1 고 전도 층(58)과 유사한 구성을 포함할 수 있다. 상기 제2 고 전도 층(77)은 상기 제1 반도체 칩(40) 및 상기 제2 반도체 칩(81) 사이를 채우고 상기 제1 반도체 칩(40) 및 상기 제2 반도체 칩(81)의 측면들 상에 연장될 수 있다. 상기 제2 고 전도 층(77)은 상기 제1 반도체 칩(40) 및 상기 제2 반도체 칩(81)의 측면들에 직접적으로 접촉될 수 있다. 상기 제2 고 전도 층(77)은 상기 제1 고 전도 층(58)의 상면에 직접적으로 접촉될 수 있다.
상기 제3 고 전도 층(78)은 상기 제2 반도체 칩(81) 및 상기 제3 반도체 칩(82) 사이를 채우고 상기 제2 반도체 칩(81) 및 상기 제3 반도체 칩(82)의 측면들 상에 연장될 수 있다. 상기 제3 고 전도 층(78)은 상기 제2 반도체 칩(81) 및 상기 제3 반도체 칩(82)의 측면들에 직접적으로 접촉될 수 있다. 상기 제3 고 전도 층(78)은 상기 제2 고 전도 층(77)의 상면에 직접적으로 접촉될 수 있다. 상기 제4 고 전도 층(79)은 상기 제3 반도체 칩(82) 및 상기 제4 반도체 칩(83) 사이를 채우고 상기 제3 반도체 칩(82) 및 상기 제4 반도체 칩(83)의 측면들 상에 연장될 수 있다. 상기 제4 고 전도 층(79)은 상기 제3 반도체 칩(82) 및 상기 제4 반도체 칩(83)의 측면들에 직접적으로 접촉될 수 있다. 상기 제4 고 전도 층(79)은 상기 제3 고 전도 층(78)의 상면에 직접적으로 접촉될 수 있다.
상기 봉지재(67)는 상기 제1 고 전도 층(58), 상기 제2 고 전도 층(77), 상기 제3 고 전도 층(78), 및 상기 제4 고 전도 층(79) 상을 덮을 수 있다. 상기 봉지재(67)는 상기 제4 반도체 칩(83)의 측면들에 직접적으로 접촉될 수 있다.
상기 다수의 제1 내부 열 분산 단자(54), 상기 다수의 제2 내부 열 분산 단자(74), 상기 다수의 제3 내부 열 분산 단자(88), 상기 다수의 제4 내부 열 분산 단자(94), 상기 적어도 하나의 외부 열 분산 단자(64), 상기 적어도 하나의 제1 열 분산 관통 전극(14), 상기 적어도 하나의 제2 열 분산 관통 전극(72), 상기 적어도 하나의 제3 열 분산 관통 전극(86), 및 상기 적어도 하나의 제4 열 분산 관통 전극(92)은 상기 배선 구조체(10), 상기 제1 반도체 칩(40), 상기 제2 반도체 칩(81), 상기 제3 반도체 칩(82), 및 상기 제4 반도체 칩(83)에서 발생하는 열을 분산하고 외부로 방출하는 역할을 할 수 있다. 상기 제1 고 전도 층(58), 상기 제2 고 전도 층(77), 상기 제3 고 전도 층(78), 및 상기 제4 고 전도 층(79)은 상기 배선 구조체(10), 상기 제1 반도체 칩(40), 상기 제2 반도체 칩(81), 상기 제3 반도체 칩(82), 및 상기 제4 반도체 칩(83)에서 발생하는 열을 분산하고 외부로 방출하는 역할을 할 수 있다.
도 9, 도 10, 도 11, 도 14, 및 도 19는 본 발명 기술적 사상의 실시예들에 따른 반도체 패키지 형성 방법들을 설명하기 위한 단면도들이고, 도 12 및 도 13은 도 11의 일부분(110)을 보여주는 부분도들이며, 도 15 내지 도 18은 도 14의 일부분(140)을 보여주는 부분도들이다.
도 9를 참조하면, 활성 영역(11) 및 상기 활성 영역(11)의 측면에 연속된 다수의 스크라이브 레인(Scribe Lane; SL1, SL2)을 갖는 다수의 배선 구조체(10)가 제공될 수 있다. 상기 활성 영역(11)을 관통하는 다수의 제1 관통 전극(13) 및 적어도 하나의 제1 열 분산 관통 전극(14)이 형성될 수 있다.
상기 활성 영역(11)의 하면 상에 다수의 외부 단자(63) 및 적어도 하나의 외부 열 분산 단자(64)가 형성될 수 있다. 상기 다수의 외부 단자(63)의 각각은 상기 다수의 제1 관통 전극(13) 중 대응하는 하나에 전기적으로 접속될 수 있다. 상기 적어도 하나의 외부 열 분산 단자(64)는 상기 적어도 하나의 제1 열 분산 관통 전극(14)에 전기적으로 접속될 수 있다.
도 10을 참조하면, 상기 다수의 배선 구조체(10) 상에 다수의 제1 반도체 칩(40)이 장착될 수 있다. 상기 다수의 제1 반도체 칩(40) 및 상기 다수의 배선 구조체(10) 사이에 다수의 제1 내부 단자(53) 및 다수의 제1 내부 열 분산 단자(54)가 형성될 수 있다. 상기 다수의 제1 내부 단자(53) 및 상기 다수의 제1 내부 열 분산 단자(54)는 상기 배선 구조체(10) 및 상기 제1 반도체 칩(40)에 접촉될 수 있다. 일 실시예에서, 상기 다수의 제1 반도체 칩(40) 및 상기 다수의 배선 구조체(10) 사이에 다수의 제1 내부 단자(53) 및 다수의 제1 내부 열 분산 단자(54)를 형성하는 것은 열압착 본딩(Thermocompression Bonding) 공정을 포함할 수 있다.
도 11을 참조하면, 상기 다수의 배선 구조체(10) 상에 제1 고 전도 층(High Thermal Conductivity Layer; 58)이 형성될 수 있다. 상기 제1 고 전도 층(58)은 상기 다수의 배선 구조체(10) 및 상기 다수의 제1 반도체 칩(40) 사이를 채우고 상기 다수의 제1 반도체 칩(40)의 측면들 상에 연장될 수 있다. 상기 제1 고 전도 층(58)은 상기 다수의 스크라이브 레인(Scribe Lane; SL1, SL2)을 완전히 덮을 수 있다. 상기 제1 고 전도 층(58)의 상면은 유동성 및 형성 방법에 기반하여 다양한 프로파일을 보일 수 있다.
도 12를 참조하면, 상기 활성 영역(11)은 제1 표면(11F) 및 상기 제1 표면(11F)과 대향하는 제2 표면(11B)을 포함할 수 있다. 상기 제1 표면(11F)은 전면(Front Surface)에 해당될 수 있으며, 상기 제2 표면(11B)은 후면(Back Surface)에 해당될 수 있다. 상기 제1 표면(11F) 상에 제1 절연층(23) 및 제2 절연층(25)이 차례로 적층될 수 있다. 상기 제1 표면(11F)에 인접한 트랜지스터(21)와 같은 다양한 종류의 능동 소자들이 형성될 수 있다.
일 실시예에서, 상기 트랜지스터(21)는 상기 활성 영역(11)의 내부 및/또는 상기 제1 절연층(23) 내에 형성될 수 있다. 상기 트랜지스터(21)는 핀펫(fin Field Effect Transistor; finFET), MBCFET® 와 같은 멀티-브리지 채널 트랜지스터(multi-bridge channel transistor), 나노와이어 트랜지스터, 수직 트랜지스터, 리세스 채널 트랜지스터(recess channel transistor), 3-D 트랜지스터, 플라나 트랜지스터(planar transistor), 또는 이들의 조합을 포함할 수 있다.
상기 제2 표면(11B) 상에 제3 절연층(33) 및 제4 절연층(35)이 차례로 적층될 수 있다. 상기 제1 고 전도 층(58)은 상기 제4 절연층(35) 상에 형성될 수 있다. 상기 활성 영역(11), 상기 제1 절연층(23), 및 상기 제3 절연층(33)을 관통하는 제1 관통 전극(13)이 형성될 수 있다. 상기 제1 관통 전극(13)의 측면을 둘러싸는 절연 스페이서(15)가 형성될 수 있다.
상기 제1 절연층(23) 및 상기 제2 절연층(25) 내에 다수의 내부 배선(27) 및 제1 패드(29)가 형성될 수 있다. 상기 다수의 내부 배선(27)은 다수의 수평 배선 및 다수의 수직 배선을 포함할 수 있다. 상기 제2 절연층(25) 상에 외부 단자(63)가 형성될 수 있다. 상기 외부 단자(63)는 상기 제2 절연층(25)을 관통하여 상기 제1 패드(29)에 접촉될 수 있다. 상기 다수의 내부 배선(27)중 몇몇은 상기 제1 패드(29) 및 상기 제1 관통 전극(13)에 접속될 수 있다. 상기 다수의 내부 배선(27)중 몇몇은 상기 트랜지스터(21)에 접속될 수 있다.
상기 제4 절연층(35) 내에 제2 패드(39)가 형성될 수 있다. 상기 제2 패드(39)는 상기 제1 관통 전극(13)에 접속될 수 있다. 상기 제4 절연층(35) 상에 제1 내부 단자(53)가 형성될 수 있다. 상기 제1 내부 단자(53)는 상기 제1 고 전도 층(58) 및 상기 제4 절연층(35)을 관통하여 상기 제2 패드(39)에 접촉될 수 있다.
상기 외부 단자(63)는 상기 제1 패드(29), 상기 다수의 내부 배선(27), 상기 제1 관통 전극(13), 및 상기 제2 패드(39)를 경유하여 상기 제1 내부 단자(53)에 접속될 수 있다. 상기 외부 단자(63)는 상기 제1 패드(29) 및 상기 다수의 내부 배선(27)을 경유하여 상기 트랜지스터(21)에 접속될 수 있다. 일 실시예에서, 상기 외부 단자(63), 상기 제1 관통 전극(13), 및 상기 제1 내부 단자(53)는 수직 정렬될 수 있다.
상기 제1 관통 전극(13), 상기 다수의 내부 배선(27), 상기 제1 패드(29), 및 상기 제2 패드(39)의 각각은 단일층 또는 멀티층 일 수 있다. 상기 제1 관통 전극(13), 상기 다수의 내부 배선(27), 상기 제1 패드(29), 및 상기 제2 패드(39)의 각각은 Cu, W, WN, Ni, Co, Al, Ti, TiN, Ta, TaN, Ag, Pt, Au, Ru, Cr, Sn, 또는 이들의 조합과 같은 도전성 물질(Conductive Material)을 포함할 수 있다.
상기 절연 스페이서(15), 상기 제1 절연층(23), 상기 제2 절연층(25), 상기 제3 절연층(33), 및 상기 제4 절연층(35)의 각각은 단일층 또는 멀티층 일 수 있다. 상기 절연 스페이서(15), 상기 제1 절연층(23), 상기 제2 절연층(25), 상기 제3 절연층(33), 및 상기 제4 절연층(35)의 각각은 실리콘산화물, 실리콘질화물, 실리콘산질화물, 로우-K 유전물(Low-K Dielectrics), 하이-K 유전물(High-K Dielectrics), 또는 이들의 조합과 같은 절연물을 포함할 수 있다.
도 13을 참조하면, 외부 단자(63) 및 제1 내부 단자(53)의 각각은 제1 관통 전극(13)과 어긋나게 정렬될 수 있다. 예를들면, 상기 외부 단자(63), 상기 제1 관통 전극(13), 및 상기 제1 내부 단자(53)의 중심들을 지나고 제1 표면(11F)에 수직한 직선들은 서로 평행하게 정렬될 수 있다.
도 14를 참조하면, 상기 제1 고 전도 층(58) 상에 봉지재(67)가 형성될 수 있다. 상기 봉지재(67)는 에폭시 몰딩 컴파운드(Epoxy Molding Compound)를 포함할 수 있다. 상기 봉지재(67)는 상기 다수의 제1 반도체 칩(40)의 측면에 접촉될 수 있다.
도 15를 참조하면, 상기 봉지재(67)의 상면은 상기 제1 반도체 칩(40)의 상면과 같거나 낮은 레벨에 형성될 수 있다. 상기 제1 반도체 칩(40)의 상면은 노출될 수 있다.
도 16을 참조하면, 상기 봉지재(67)의 상면은 상기 제1 반도체 칩(40)의 상면과 실질적으로 동일한 레벨에 형성될 수 있다. 상기 봉지재(67) 및 상기 제1 반도체 칩(40)의 상면들은 실질적으로 동일한 레벨에 노출될 수 있다.
도 17을 참조하면, 상기 봉지재(67)의 상면은 상기 제1 반도체 칩(40)의 상면보다 높은 레벨에 형성될 수 있다.
도 18을 참조하면, 상기 봉지재(67)는 상기 제1 반도체 칩(40) 및 상기 제1 고 전도 층(58) 상을 완전히 덮도록 형성될 수 있다.
도 19를 참조하면, 쏘잉(Sawing)공정을 이용하여 상기 다수의 스크라이브 레인(SL1, SL2)을 절단할 수 있다.
이상, 첨부된 도면을 참조하여 본 발명의 기술적 사상에 따른 실시예들을 설명하였지만, 본 발명이 속하는 기술 분야에서 통상의 지식을 가진 자는 본 발명이 그 기술적 사상이나 필수적인 특징을 변경하지 않고서 다른 구체적인 형태로 실시될 수 있다는 것을 이해할 수 있을 것이다. 이상에서 기술한 실시예는 모든 면에서 예시적인 것이며 한정적이 아닌 것으로 이해하여야 한다.
10: 배선 구조체
11: 활성 영역
SL1, SL2: 스크라이브 레인(Scribe Lane)
13: 관통 전극
14: 열 분산 관통 전극
40: 반도체 칩
53: 내부 단자
54: 내부 열 분산 단자
58: 고 전도 층(High Thermal Conductivity Layer)
63: 외부 단자
64: 외부 열 분산 단자
67: 봉지재

Claims (10)

  1. 제1 반도체 칩;
    상기 제1 반도체 칩 상의 제2 반도체 칩;
    상기 제1 반도체 칩 및 상기 제2 반도체 칩 사이의 다수의 내부 단자;
    상기 제1 반도체 칩 및 상기 제2 반도체 칩 사이의 고 전도 층(High Thermal Conductivity Layer); 및
    상기 고 전도 층 상에 배치되고 상기 제2 반도체 칩에 접촉된 봉지재를 포함하되,
    상기 제1 반도체 칩, 상기 고 전도 층, 및 상기 봉지재의 측벽들은 동일한 평면을 이루는 반도체 패키지.
  2. 제1 항에 있어서,
    상기 고 전도 층의 열전도율은 1 W/mK 내지 5 W/mK 인 반도체 패키지.
  3. 제1 항에 있어서,
    상기 고 전도 층은 필러(Filler) 및 레진(Resin)을 포함하되,
    상기 필러는 알루미늄 산화물(Al2O3), 알루미늄 질화물(AlN), 붕소 질화물(BN), 실리콘 산화물(SiO2), 또는 이들의 조합을 포함하는 반도체 패키지.
  4. 제3 항에 있어서,
    상기 필러(Filler)의 직경은 0.7㎛ 내지 3㎛ 인 반도체 패키지.
  5. 제3 항에 있어서,
    상기 레진(Resin)은 LCERs(liquid crystalline epoxy resins)을 포함하는 반도체 패키지.
  6. 제1 항에 있어서,
    상기 제1 반도체 칩은
    활성 영역; 및
    상기 활성 영역의 측면에 연속된(in continuity with) 적어도 하나의 스크라이브 레인(Scribe Lane)을 포함하되,
    상기 고 전도 층은 상기 활성 영역 및 상기 적어도 하나의 스크라이브 레인에 접촉된 반도체 패키지.
  7. 제6 항에 있어서,
    상기 적어도 하나의 스크라이브 레인, 상기 고 전도 층, 및 상기 봉지재의 측벽들은 동일한 평면을 이루는 반도체 패키지.
  8. 제1 항에 있어서,
    상기 고 전도 층의 최 상단은 상기 제2 반도체 칩의 최 하단보다 높은 레벨에 배치되며,
    상기 고 전도 층의 최 상단은 상기 제2 반도체 칩의 최 상단보다 낮은 레벨에 배치되고,
    상기 고 전도 층은 상기 제2 반도체 칩의 측면에 접촉된 반도체 패키지.
  9. 활성 영역 및 상기 활성 영역의 측면들에 연속된 다수의 스크라이브 레인(Scribe Lane)을 갖는 배선 구조체;
    상기 배선 구조체 상의 반도체 칩;
    상기 배선 구조체 및 상기 반도체 칩 사이의 다수의 내부 단자;
    상기 배선 구조체 및 상기 반도체 칩 사이에 배치되고 상기 활성 영역 및 상기 다수의 스크라이브 레인에 접촉된 고 전도 층(High Thermal Conductivity Layer); 및
    상기 배선 구조체 및 상기 고 전도 층 상에 배치되고 상기 반도체 칩에 접촉된 봉지재를 포함하는 반도체 패키지.
  10. 배선 구조체;
    상기 배선 구조체 상의 반도체 칩;
    상기 배선 구조체 및 상기 반도체 칩 사이의 다수의 내부 단자;
    상기 배선 구조체 및 상기 반도체 칩 사이의 고 전도 층(High Thermal Conductivity Layer); 및
    상기 고 전도 층 상에 배치되고 상기 반도체 칩에 접촉된 봉지재를 포함하되,
    상기 배선 구조체, 상기 고 전도 층, 및 상기 봉지재의 측벽들은 동일한 평면을 이루고,
    상기 고 전도 층의 최 상단은 상기 반도체 칩의 최 하단보다 높은 레벨에 배치되며,
    상기 고 전도 층의 최 상단은 상기 반도체 칩의 최 상단보다 낮은 레벨에 배치되고,
    상기 고 전도 층은 상기 반도체 칩의 측면에 접촉되며,
    상기 고 전도 층 및 상기 반도체 칩의 최대 접촉 높이는 제1 길이이고, 상기 반도체 칩의 두께는 제2 길이이며, 상기 제1 길이는 상기 제2 길이의 절반보다 큰 반도체 패키지.
KR1020200163646A 2020-11-30 2020-11-30 고 전도 층을 갖는 반도체 패키지 KR20220075507A (ko)

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Family Cites Families (19)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5864178A (en) * 1995-01-12 1999-01-26 Kabushiki Kaisha Toshiba Semiconductor device with improved encapsulating resin
US5866953A (en) 1996-05-24 1999-02-02 Micron Technology, Inc. Packaged die on PCB with heat sink encapsulant
JP2000150729A (ja) * 1998-11-10 2000-05-30 Hitachi Ltd 樹脂封止半導体装置
JP2008071953A (ja) * 2006-09-14 2008-03-27 Nec Electronics Corp 半導体装置
WO2008108334A1 (ja) 2007-03-06 2008-09-12 Nikon Corporation 半導体装置及び該半導体装置の製造方法
JP2009188011A (ja) * 2008-02-04 2009-08-20 Nec Electronics Corp フリップチップ半導体装置の製造方法と製造装置
JP5579402B2 (ja) 2009-04-13 2014-08-27 ピーエスフォー ルクスコ エスエイアールエル 半導体装置及びその製造方法並びに電子装置
US8803332B2 (en) 2009-09-11 2014-08-12 Taiwan Semiconductor Manufacturing Company, Ltd. Delamination resistance of stacked dies in die saw
JP5250524B2 (ja) * 2009-10-14 2013-07-31 ルネサスエレクトロニクス株式会社 半導体装置及びその製造方法
KR101719636B1 (ko) 2011-01-28 2017-04-05 삼성전자 주식회사 반도체 장치 및 그 제조 방법
KR101817159B1 (ko) * 2011-02-17 2018-02-22 삼성전자 주식회사 Ｔｓｖ를 가지는 인터포저를 포함하는 반도체 패키지 및 그 제조 방법
US9269646B2 (en) 2011-11-14 2016-02-23 Micron Technology, Inc. Semiconductor die assemblies with enhanced thermal management and semiconductor devices including same
JP2014091744A (ja) * 2012-10-31 2014-05-19 3M Innovative Properties Co アンダーフィル組成物、半導体装置およびその製造方法
KR20140106038A (ko) * 2013-02-25 2014-09-03 삼성전자주식회사 반도체 장치 및 이의 제조 방법
KR102084540B1 (ko) 2013-10-16 2020-03-04 삼성전자주식회사 반도체 패키지 및 그 제조방법
KR101630769B1 (ko) 2014-06-24 2016-06-16 매그나칩 반도체 유한회사 방열 반도체 칩 패키지 및 그 제조 방법
US9337119B2 (en) 2014-07-14 2016-05-10 Micron Technology, Inc. Stacked semiconductor die assemblies with high efficiency thermal paths and associated systems
KR20210059866A (ko) * 2019-11-15 2021-05-26 삼성전자주식회사 언더 필 물질 층을 포함하는 반도체 패키지 및 그 형성방법
US20210193552A1 (en) * 2019-12-19 2021-06-24 Intel Corporation Thermally conductive slugs/active dies to improve cooling of stacked bottom dies

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