TW201428936A - 將中央處理單元／圖形處理單元／邏輯晶片嵌入疊合式封裝結構基板之方法 - Google Patents

將中央處理單元／圖形處理單元／邏輯晶片嵌入疊合式封裝結構基板之方法 Download PDF

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Publication number
TW201428936A
TW201428936A TW102140309A TW102140309A TW201428936A TW 201428936 A TW201428936 A TW 201428936A TW 102140309 A TW102140309 A TW 102140309A TW 102140309 A TW102140309 A TW 102140309A TW 201428936 A TW201428936 A TW 201428936A
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Taiwan
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substrate
high power
wafer
insulating layer
power wafer
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TW102140309A
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English (en)
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Abraham F Yee
Jayprakash Chipalkatti
Shantanu Kalchuri
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Nvidia Corp
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Publication of TW201428936A publication Critical patent/TW201428936A/zh

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Abstract

本發明的具體實施例揭示一種積體電路系統，其中低功率晶片可位於高功率晶片附近，而不會遭致過熱的影響。在一個具體實施例內，該積體電路系統可包含：一第一基板，一高功率晶片，其嵌入該第一基板；一第二基板，位於該第一基板的一第一側旁，該第一基板與該第二基板彼此電連通；以及一低功率晶片，其位於該第二基板上。在許多具體實施例內，一散熱層安置在該高功率晶片旁邊，如此該高功率晶片產生的熱量可有效逸散進入底下固定至該第一基板的印刷電路板，藉此進一步避免熱量從該高功率晶片轉移至該低功率晶片。因此，可延長該低功率晶片的壽命。

Description

將中央處理單元/圖形處理單元/邏輯晶片嵌入疊合式封裝結構基板之 方法
本發明的具體實施例一般係關於積體電路晶片封裝，尤其係關於具備高功率晶片與低功率晶片的疊合式(POP，package-on-package)封裝系統。
隨著電子工業的發展，對於具備改良效能並且更小的電子裝置之需求越高。為了讓電子組件達到更高整合密度以及更小佔用面積，因此開發出俗稱的「疊合式(POP)」技術。疊合式屬於一種三維封裝技術，運用於垂直堆疊許多導線架型半導體封裝，其上彼此之間具有介面可用於佈線。
縮小封裝厚度已經成為成功實施該疊合式技術的一項挑戰，因為這通常是封裝內含晶片與其他裝置的熱管理與裝置效能之間的取捨。尤其是，利用將記憶體晶片、被動裝置以及積體電路封裝的其他低功率組件定位在盡可能靠近中央處理單元(CPU，central processor unit)以及積體電路封裝內其他高功率裝置之處，則加速積體電路封裝內裝置之間的通訊並且降低封裝寄生效應。不過，已知高功率晶片產生的熱量對於附近的記憶體晶片以及其他裝置會有不利的影響。因此，在整合成單一積體電路封裝時，將記憶體晶片與被動裝置直接堆疊在中央處理單元或其他高功率晶片之上或之下在熱量管理方面並不可行，因為這種組態必然會限制高功率晶片的功率或影響記憶體晶片的效能。
如上面的例示，業界需要一種具有更高積體電路密度並且封裝大小相對降低之封裝系統。進一步需要能夠垂直堆疊避免晶片之間熱傳輸的高功率晶片與低功率晶片配置。
本發明的具體實施例揭示一種積體電路系統，其中一或多個低功率晶片可位於高功率晶片附近，而不會遭致過熱的影響。在一個具體實施例內，該積體電路系統包含嵌入一第一封裝基板的一高功率晶片，以及位於一第二封裝基板上的一低功率晶片，其中該第二封裝基板位於該第一封裝基板之上，形成一堆疊。因為該第一封裝基板的部分將該嵌入的高功率晶片與該低功率晶片熱隔離，所以該低功率晶片可定位在該高功率晶片附近而不會過熱。在特定具體實施例內，在該高功率晶片一側附近定位一薄的散熱層，將該高功率晶片的熱量擴散進入該第一封裝晶片。在模造的疊合式封裝系統內，該第一封裝基板內的熱量透過焊錫球傳遞進入一底層印刷電路板(PCB，printed circuit board)，此當成該積體電路系統的散熱器。
本發明的一項優點為一記憶體晶片或其他低功率晶片可定位在嵌入該相同積體電路系統內一封裝基板的一高功率晶片附近，而不會因為該高功率晶片而過熱。這種靠近的優點可降低該封裝系統的整體厚度，如此可實現較薄並且較輕的電子裝置。藉由在該高功率晶片旁邊安置一散熱層，則該高功率晶片產生的熱量可有效逸散進入該印刷電路板(PCB)，這樣進一步避免熱量從該高功率晶片轉移至該低功率晶片。因此，可延長該低功率晶片的壽命。
100‧‧‧積體電路系統
101‧‧‧高功率晶片
102、105‧‧‧低功率晶片
110‧‧‧第一封裝基板
114‧‧‧導電線
117‧‧‧絕緣層
119‧‧‧核心層
123‧‧‧導電穿孔
125‧‧‧矽貫穿孔
140‧‧‧第二封裝基板
142‧‧‧電連接
143‧‧‧頂端表面
145‧‧‧焊墊
148‧‧‧模造材料
152‧‧‧頂端表面
154‧‧‧底端表面
156‧‧‧頂端表面
158‧‧‧底端表面
165‧‧‧導電焊墊
167‧‧‧導電焊墊
170‧‧‧電連接
180‧‧‧封裝導線
190‧‧‧印刷電路板
200‧‧‧積體電路系統
202‧‧‧散熱層
209‧‧‧層
300‧‧‧積體電路系統
302‧‧‧頂端絕緣層
304‧‧‧底端絕緣層
305‧‧‧模造材料
306‧‧‧空間
308‧‧‧空間
310‧‧‧第一支撐基板
310‧‧‧周邊
312a、312b‧‧‧導電線
312c、312d‧‧‧導電線
314a‧‧‧導電線
316、318‧‧‧散熱部件
316a、316b‧‧‧散熱部件
330‧‧‧焊墊
340‧‧‧第二支撐基板
342‧‧‧鉛錫凸塊
344‧‧‧導電穿孔
350‧‧‧導線
352‧‧‧頂端絕緣層
354‧‧‧底端絕緣層
358‧‧‧球閘陣列
362‧‧‧導電穿孔
366‧‧‧C4凸塊
368‧‧‧焊墊
如此上面簡單彙總可詳細了解本發明上述特色的方式，本發明的更特定說明則參照具體實施例，某些具體實施例說明於附圖內。不過吾人應該注意，附圖只說明本發明的典型具體實施例，因此並不對發明領域產生限制，本發明承認其他等效具體實施例。
第一圖為根據本發明一個具體實施例的一積體電路(IC，integrated circuit)系統之圖解剖面圖。
第二圖為根據本發明的另一個具體實施例，具有一散熱機構位於一高功率晶片附近以提高該高功率晶片熱傳遞係數的一積體電路系統之圖解剖面圖。
第三圖為根據仍舊本發明的另一個具體實施例，具有一散熱 機構位於一高功率晶片附近以提高該高功率晶片熱傳遞係數的一積體電路系統之圖解剖面圖。
為了清晰起見，在合適的地方使用一致的參考編號，來指定圖式之間共用的相同元件。本說明書假設，一個具體實施例的特徵不需要進一步說明，就可併入另一個具體實施例內。
第一圖為根據本發明一個具體實施例的一積體電路(IC)系統100之圖解剖面圖。積體電路系統100一般包含多個積體電路晶片及/或其他分離的微電子組件，並且設置成將該等晶片與組件電連接與機械連接至一印刷電路板190。該積體電路系統可為一或多個高功率晶片101與一或多個低功率晶片102、105的垂直組合，即是堆疊組態，其中一或多個低功率晶片102、105與一或多個高功率晶片101熱隔離。因此，低功率晶片102、105並未顯著受到源自於高功率晶片101的熱量影響。
在此揭露事項當中，高功率晶片101為一高功率處理器，例如中央處理單元(CPU，central processing unit)、一圖形處理單元(GPU，graphics processing unit)、應用處理器或其他邏輯裝置，或可在操作期間產生足夠熱量的任何積體電路晶片，對於積體電路系統100內的低功率晶片102、105或被動裝置效能有不利的影響。例如：高功率晶片通常為正常操作期間產生至少10W或更多熱量的晶片。相反地，低功率晶片為在操作期間不會產生足夠熱量，而對相鄰積體電路晶片或裝置效能產生不利影響之晶片。例如：低功率晶片為正常操作期間產生大約1W數量級熱量，即是不超過大約5W的任何積體電路晶片。低功率晶片可為積體電路系統100內的被動裝置，例如記憶體裝置，像是隨機存取記憶體或快閃記憶體、一輸入/輸出晶片或在正常操作中不會產生5W以上的任何其他晶片。
在第一圖所示的具體實施例內，積體電路系統100包含嵌入一第一封裝基板110的一高功率晶片101，以及安裝在一第二封裝基板140上的一低功率晶片102。低功率晶片102可透過導電焊墊165安裝在第二封裝基板140上。若使用低功率晶片的包裝，則頂端低功率晶片105可透過導電焊墊167安裝在底端低功率晶片102之上。第一封裝基板110大體上 與第二封裝基板140平行並且相對。第二封裝基板140放在第一封裝基板110的頂端表面143之上，並且透過電連接142電連接至第一封裝基板110。第二封裝基板140與第一封裝基板110之間的電連接142可用業界內任何技術可行的方式進行，例如鉛錫凸塊或鉛錫球。電連接142可實體接觸第一封裝基板110的頂端表面143上形成之對應焊墊145。吾人考慮到第二封裝基板140與第一封裝基板110之間的該電連接也可由其他接合技術執行，例如覆晶接合技術或針閘陣列(PGA，pin grid array)技術。
安裝在第二封裝基板140上的低功率晶片102可包裝在一模造材料148內，以保護低功率晶片102。若想要，運用包覆材料保護電連接142，可改善電連接142的可靠度。該模造或包覆材料可為樹脂，例如環氧樹脂、丙烯酸樹脂、有機矽樹脂、聚氨酯樹脂、聚酰胺樹脂、聚酰亞胺樹脂等。任何其他技術可行封裝技術也可用來保護低功率晶片102或低功率晶片102至第一封裝基板110的電連接142。雖然未顯示，不過吾人也考慮模造材料148背向第二封裝基板140的頂側150可固定至散熱器或其他冷卻機構，以強化積體電路系統100的熱傳遞係數。
低功率晶片102安裝在堆疊組態中高功率晶片101的反面，並且透過第一封裝基板110內形成的導電線114以及導電穿孔123電連接至高功率晶片101和印刷電路板190。高功率晶片101與第一封裝基板110之間的電連接可用業界內任何技術可行的方式進行。請注意，導電線114和導電穿孔123及其組態都為示範方式，可用來將高功率晶片101電連接至外部組件。具有不同路徑配置/組態的任何已知電連接可用來替代導電線114與導電穿孔123，或加入其中。
在第一圖例示的具體實施例內，高功率晶片101包含矽貫穿孔(TSV，through-silicon via)125，其穿過高功率晶片101並且當成電源、接地以及信號互連穿過高功率晶片101。矽貫穿孔125設置成幫助高功率晶片101與第一封裝基板110之間快速電連接，接著幫助高功率晶片101、低功率晶片102與印刷電路板190之間的電連接。相對於線接技術，例如焊墊等等這類電連接製作在該高功率晶片的單一側上，並且使用厚金屬線將該等焊墊互連至外部電路，矽貫穿孔125可電連接至高功率晶片101兩側上 的組件。運用矽貫穿孔125，高功率晶片101可如第一圖所示嵌入積體電路系統100內，並且可將高功率晶片101電連接至低功率晶片102(透過導電線114、導電穿孔123以及電連接142)以及至印刷電路板190(透過複數條封裝導線180)。因此，在高功率晶片101與低功率晶片102之間可獲得非常短的路徑長度互連。
電路之間較短的互連路徑導致訊號傳遞更快，並且降低雜訊、干擾以及其他寄生效應。在積體電路封裝場內，寄生效應係由一晶片至外部組件的互連所引起，例如積體電路焊墊、焊線、封裝導線、導電線等等。利用將低功率晶片102與高功率晶片101堆疊成重疊組態，如第一圖內所示，低功率晶片102與高功率晶片101之間互連的長度縮至最短，這樣寄生效應大幅降低。進一步，相較於其中高功率晶片101與低功率晶片102並肩置於封裝基板同一側上的積體電路封裝，積體電路系統100的整體「佔用面積」縮至最小。此外，相較於其中高功率晶片安裝於第一封裝基板110的頂端表面143之現有疊合式封裝系統，將高功率晶片101嵌入第一封裝基板110，可降低積體電路系統100的厚度「H1」至少大約25μm或更多。最重要是，因為高功率晶片101靠近印刷電路板190(當成積體電路系統100的散熱器)，並且部分第一封裝基板110可當成熱隔離層，所以低功率晶片102與嵌入的高功率晶片101熱隔離，不受高功率晶片101所產生熱量的不利影響。
第一封裝基板110提供積體電路系統100結構剛性以及一電介面，用於在高功率晶片101、低功率晶片102以及印刷電路板190之間傳遞輸入與輸出信號以及電源。第一封裝基板110可為絕緣層117的堆疊所構成之積層結構，或建立在其中嵌入高功率晶片101的核心層119頂端表面152和底端表面154上之積層。絕緣層117之間形成導電線114以及導電穿孔123，在高功率晶片101、低功率晶片102與印刷電路板190之間提供電連通。利用濕式或乾式蝕刻處理在核心層119內形成凹穴或凹陷開口，可將高功率晶片101嵌入第一封裝基板110內。該凹穴或凹陷開口的大小經過調整，用於容納高功率晶片101。在核心層119內形成高功率晶片101之後，則在高功率晶片101四周形成絕緣層117以及例如導電線114和導 電穿孔123這類電連接。雖然本說明書內未討論，不過精通技術人士應了解，導電線114可由任何合適的處理所形成，例如蝕刻貼合至第一封裝基板110中一或多積層的銅箔。導電穿孔123可為由電鍍處理或任何其他合適技術形成的銅填充穿孔。
高功率晶片101可位於第一封裝基板110內預定深度上。將高功率晶片101上放在靠近印刷電路板190的高度上，以促進熱逸散進入印刷電路板190，這在某些具體實施例內有所好處。吾人也考慮到，高功率晶片101可不需要完全嵌入第一封裝基板110。高功率晶片101的頂端表面152可齊平、稍微低於或稍微高於第一封裝基板110的頂端表面143。高功率晶片101的高度可根據處理法則或應用而變。在一個具體實施例內，高功率晶片101具有大約100μm至大約200μm的厚度「T1」，例如大約150μm。第一封包基板110可具有大約300μm至大約500μm的厚度「T2」，例如大約400μm。較厚或較薄的外型考量取決於應用情況。
第二圖為根據本發明的另一個具體實施例，具有一散熱機構位於一高功率晶片附近以提高該高功率晶片熱傳遞係數的一積體電路系統200之圖解剖面圖。請注意，例如第一圖內所示的導電線114以及導電穿孔123這類電連接已經簡化並且標示為170，或為了容易了解而省略。除了散熱層202已經嵌入第一封裝基板110以外，積體電路系統200的組態與操作大體上類似於積體電路系統100。在所示的具體實施例內，散熱層202形成為第一封裝基板110內的一層209，並且放置成實體接觸高功率晶片101的頂端表面156，以促進熱量從高功率晶片101逸散至第一封裝基板110。另外，散熱層202可與高功率晶片101分開一段距離。散熱層202可為金屬板的形式，具有比第一封裝基板110還要高的導熱性。在一個具體實施例內，散熱層202由銅或其他導電材料構成，例如鋁、金、銀或二或多種元素的合金。散熱層202可使用導電樹脂或導電膏製成的導電黏著層(未顯示)，接合至高功率晶片101的頂端表面156，以確定良好的熱傳導並且緊密固定至高功率晶片101。
散熱層202設置成將高功率晶片101產生的熱能導離低功率晶片102，藉此降低積體電路系統操作期間低功率晶片102過熱的風險。散 熱層202沿著第一封裝基板110的縱向方向，將熱量導入並充滿整個第一封裝基板110。然後熱量透過封裝導線180逸散至印刷電路板190。由於第一封裝基板110內散熱層202增加的表面積用於散熱，因此高功率晶片101產生的熱能可更有效率逸散進入印刷電路板190。
散熱層202可在與第一封裝基板110的頂端表面156平行之平面內橫向延伸。在第一封裝基板110的製造期間，可用一電鍍處理、物理汽相沉積(PVD，physical vapor deposition)或任何其他合適的沉積處理，形成散熱層202。散熱層202的長度「L1」可比第一封裝基板110的長度稍短，但是比高功率晶片101的長度還長。在一個範例中，散熱層202的長度「L1」介於大約20μm與大約150μm之間，例如大約80μm。雖然只顯示一個散熱層202，吾人考慮在任何合適的配置中，在第一封裝基板110中可使用二或多個散熱層，以強化從高功率晶片101去除熱量的效果。例如：二或多個散熱層(未顯示)可固定至高功率晶片101的底端表面158，具有或不具有散熱層202固定至高功率晶片101的頂端表面156。任何額外散熱層(若使用)都可沿著第一封裝基板110的縱向方向，橫向延伸通過第一封裝基板110，或根據應用在任何其他配置中。在某些具體實施例內，散熱層202及/或任何額外散熱層(若使用)可由二或多層金屬箔形成，並且在已知積體電路系統200的佔用面積以及高功率晶片101與低功率晶片102產生的熱量之下，由精通技術人士迅速決定其厚度。雖然未顯示，吾人考慮到散熱層202可包含貫穿孔，允許低功率晶片102與高功率晶片101之間不用接觸散熱層202就可互連。
第三圖為根據仍舊本發明的另一個具體實施例，具有一散熱機構位於一高功率晶片附近以提高該高功率晶片熱傳遞係數的一積體電路系統300之圖解剖面圖。除了高功率晶片101包覆在模造材料305內，該材料夾在一頂端絕緣層302與一底端絕緣層304之間以外，積體電路系統300類似於積體電路系統100的組態與操作。
高功率晶片101嵌入第一支撐基板310內。第一支撐基板310由頂端絕緣層302、底端絕緣層304以及夾在頂端絕緣層302與底端絕緣層304之間的模造材料305構成。模造材料305包覆高功率晶片101。尤 其是，模造材料305大體上填滿頂端絕緣層302、底端絕緣層304以及高功率晶片101的周邊310所定義之空間306、308，造成模造材料305包圍高功率晶片101。雖然未顯示，不過頂端與底端絕緣層302、304可為絕緣層(例如第一圖內所示的絕緣層117)的堆疊所構成的一積層結構，或建構在其中包覆高功率晶片101的模造材料305之頂端表面352與底端表面354上之積層。如此頂端與底端絕緣層302、304以及模造材料305(包覆高功率晶片101)形成第一支撐基板310，其功能類似於第一圖內所示的第一封裝基板110。
模造材料305的底端表面354大體上與底端絕緣層304的頂端表面共平面，而模造材料305的頂端表面352可與頂端絕緣層302的底端表面共平面。在這種情況下，高功率晶片101可與頂端絕緣層302及/或底端絕緣層304分隔一段所要距離。另外，頂端絕緣層302可為一連續層，覆蓋模造材料305的頂端表面352以及嵌入模造材料305內的高功率晶片101之頂端表面，而底端絕緣層304可為一連續層，覆蓋模造材料305的底端表面354以及嵌入模造材料305內的高功率晶片101之底端表面。在這兩種情況下，模造材料305可包含業界內已知容易流動的任何合適模造材料，因此大幅減少任何間隙的形成。在一個範例中，該模造材料為一模造化合物，例如環氧樹脂、丙烯酸樹脂、有機矽樹脂、聚氨酯樹脂、聚酰胺樹脂、聚酰亞胺樹脂等。
頂端絕緣層302可包含嵌入其中的一頂端重新分散部件，促進低功率晶片102、高功率晶片101與印刷電路板190之間電信號的繞送。在一個具體實施例內，該頂端重新分散部件為一導電線312a，在與模造材料305的頂端表面352平行之一平面內橫向延伸一所要長度。在另一個具體實施例內，該頂端重新分散部件可包含二或多條導電線(共平面或非共平面電線)，排列在頂端絕緣層302並且利用導電穿孔362以平行關係彼此電連接。運用該重新分散部件可減少第一支撐基板310內用於封裝系統300的繞送層數量。第三圖顯示一個示範配置，其中共平面導電線312a、312b分別電連接至底下的共平面導電線312d、312c。該頂端重新分散部件也可用來將高功率晶片101產生的熱量擴散進入頂端絕緣層302。吾人考慮到該 第一重新分散部件的配置與數量可根據外部連接、頂端絕緣層302的尺寸以及應用而變。在許多具體實施例內，該頂端重新分散部件由銅或其他導電材料構成，例如鋁、金、銀或二或多種元素的合金。
低功率晶片102、高功率晶片101以及印刷電路板190之間的電連接可用業界內已知的任何技術可行之晶片封裝電連接方式進行。在一個具體實施例內，一或多個頂端重新分散部件312a可分別透過導點穿孔344和導電穿孔346，分別連接至位於高功率晶片101一側上的鉛錫凸塊342以及一或多個焊墊330，一或多個焊墊330藉由貫穿高功率晶片101的矽貫穿孔344，與位於高功率晶片101另一側上的一或多個焊墊368電導通。類似地，一或多個焊墊368透過導線350以及球閘陣列358與印刷電路板190電導通。雖然本說明書內未討論，吾人考慮到相同的電連接可用來在低功率晶片102、高功率晶片101與印刷電路板190之間傳遞電源、接地及/或輸入/輸出信號。
類似地，底端絕緣層304可包含嵌入其中的一底端重新分散部件，促進低功率晶片102、高功率晶片101與印刷電路板190之間電信號的繞送，藉此可減少第一支撐基板310內用於封裝系統300的繞送層數量。該底端重新分散部件為一導電線314a，在與模造材料305的底端表面354平行之一平面內橫向延伸一所要長度。另外，該底端重新分散部件可包含二或多條導電線(共平面或非共平面電線)，排列在底端絕緣層304並且利用導電穿孔364以平行關係彼此電連接，藉此可減少第一支撐基板310內用於封裝系統300的繞送層數量。該底端重新分散部件也可用來將高功率晶片101產生的熱量擴散進入底端絕緣層304。雖然未顯示，不過吾人考慮到頂端與底端絕緣層302、304可包含一或多個電線路、焊墊接頭、穿孔、電線或業界內任何已知結構、構造、配置，用於實際將信號或電源從電路內一點傳送至另一點。該等頂端與底端重新分散部件也可用於任何其他配置/組態，來提高從高功率晶片101進入第一支撐基板310的熱傳遞係數。
具有頂端與底端絕緣層302、304以及嵌入其中的相關重新分散部件時，高功率晶片101可與安裝在第二支撐基板340(結構與操作相同於第一圖中的第二封裝基板140)上的低功率晶片102以及印刷電路板190 電連通。為了幫助熱量從高功率晶片101逸散至第一支撐基板310然後到印刷電路板190，在模造材料305內高功率晶片101的兩側上可形成一組散熱部件。在第三圖所示的具體實施例內，顯示兩個散熱部件316a、316b。不過，可考慮更少或更多散熱部件。散熱部件316a、316b可垂直通過模造材料305，電與熱連接頂端絕緣層302以及底端絕緣層304。尤其是，散熱部件316a、316b分別與頂端重新分散部件，例如導電線312d、312c以及底端重新分散部件，例如導電線314a、314b實體接觸。因此，頂端絕緣層302吸收的熱量可傳輸通過該組散熱部件316到達底端絕緣層304，然後通過封裝導線或導電機構，例如C4凸塊366，到達印刷電路板190。如上面所討論，印刷電路板190當成積體電路系統300的散熱器。由於第一支撐基板310內該組散熱部件316a、316b增加的表面積用於散熱，因此高功率晶片101產生的熱能可更有效率逸散進入印刷電路板190。
該組散熱部件可為利用雷射鑽孔或任何其他合適技術形成的導熱穿孔。該導熱穿孔使用任何合適的技術，例如電鍍處理，填入傳熱媒介。在一個範例中，該導熱穿孔填入金屬填充物，例如銅。不過，熱傳導性比第一支撐基板310還要高的任何材料都可使用。
在該散熱部件的發明組態之下，因為高功率晶片101已經嵌入該封裝基板，並且高功率晶片101產生的熱量可透過第二圖內所示的散熱層202，或第三圖內所示的該組散熱部件316、318，有效逸散進入印刷電路板190，所以低功率晶片102不受過熱影響。
總結來說，本發明的具體實施例揭示一種積體電路系統，其中一或多個低功率晶片可位於高功率晶片附近，而不會遭致過熱的影響。藉由在嵌入一封裝基板的該等一或多個高功率晶片旁邊安置一散熱層，則該高功率晶片產生的熱量可有效逸散進入該封裝基板然後進入一印刷電路板，其當成該積體電路系統的散熱器，藉此避免熱量從該高功率晶片轉移至該低功率晶片。結果，延長該記憶體晶片的壽命。
雖然上述指向本發明的具體實施例，不過可想出不背離本發明基本領域以及底下申請專利範圍的其他與進一步具體實施例。
101‧‧‧高功率晶片
102、105‧‧‧低功率晶片
110‧‧‧第一封裝基板
140‧‧‧第二封裝基板
142‧‧‧電連接
156‧‧‧頂端表面
158‧‧‧底端表面
165‧‧‧導電焊墊
167‧‧‧導電焊墊
170‧‧‧電連接
180‧‧‧封裝導線
190‧‧‧印刷電路板
200‧‧‧積體電路系統
202‧‧‧散熱層
209‧‧‧層

Claims (10)

  1. 一種積體電路系統，包含：一第一基板；一高功率晶片，其嵌入該第一基板；一第二基板，位於該第一基板的一第一側旁，其中該第一基板與該第二基板彼此電連通；以及一低功率晶片，其位於該第二基板上。
  2. 如申請專利範圍第1項之系統，進一步包含：一散熱層，其嵌入該第一基板，其中該散熱層沿著該高功率晶片的一縱向方向橫向延伸。
  3. 如申請專利範圍第2項之系統，其中該散熱層的長度比該高功率晶片的長度還要長。
  4. 如申請專利範圍第2項之系統，其中該散熱層位於該高功率晶片旁邊。
  5. 如申請專利範圍第2項之系統，其中該散熱層固定至該高功率晶片的至少一第一側。
  6. 如申請專利範圍第2項之系統，其中該散熱層由導電材料製成，包含銅、鋁、金、銀或二或多種導電元素的合金。
  7. 一種積體電路系統，包含：一第一基板，包含：一頂端絕緣層，其位於該第一基板的一頂端表面上；一底端絕緣層，位於該第一基板的一底端表面上，該頂端絕緣層與該底端絕緣層平行；一高功率晶片，位於該頂端絕緣層與該底端絕緣層之間並電連通；以及一模造材料，大體上填入圍繞該高功率晶片的一空間，該模造材料位於該頂端絕緣層與該底端絕緣層之間；一第二基板，位於該第一基板的一第一側旁，該第一基板與該第二基板彼此電連通；以及一低功率晶片，其位於該第二基板上。
  8. 如申請專利範圍第7項之系統，進一步包含：一頂端重新分散部件，其嵌入該頂端絕緣層內；以及一底端重新分散部件，其嵌入該底端絕緣層內，其中該頂端與底端重新分散部件設置成幫助該低功率晶片與該高功率晶片之間電信號的繞送。
  9. 如申請專利範圍第7項之系統，其中該模造材料另包含：一或多個散熱部件，其透過該模造材料形成，其中該散熱部件分別實際並且熱接觸該頂端重新分散部件以及該底端重新分散部件。
  10. 如申請專利範圍第9項之系統，其中該等一或多個散熱部件由導電材料製成，包含銅、鋁、金、銀或二或多種導電元素的合金。
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