CN110416153A - 层叠半导体晶片的方法 - Google Patents

层叠半导体晶片的方法 Download PDF

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Publication number
CN110416153A
CN110416153A CN201811397519.2A CN201811397519A CN110416153A CN 110416153 A CN110416153 A CN 110416153A CN 201811397519 A CN201811397519 A CN 201811397519A CN 110416153 A CN110416153 A CN 110416153A
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CN
China
Prior art keywords
splice terminal
semiconductor wafer
semiconductor chip
hole
splice
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CN201811397519.2A
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English (en)
Inventor
申灿镐
金胜桓
裴弼淳
郑辉朝
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SK Hynix Inc
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Hynix Semiconductor Inc
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Publication of CN110416153A publication Critical patent/CN110416153A/zh
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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
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Abstract

层叠半导体晶片的方法。公开了一种层叠半导体晶片的方法，该方法包括以下步骤：将下半导体晶片用粘合层附接到基底基板并且将上半导体晶片用另一附加层附接到下半导体晶片。向上半导体晶片应用热压接合技术，以使粘合层固化并且将上半导体晶片接合到下半导体晶片。

Description

层叠半导体晶片的方法
技术领域
本公开涉及半导体封装技术，并且更具体地，涉及一种层叠多个半导体晶片的方法。
背景技术
最近，在各种电子系统中需要具有高带宽和大储存容量的半导体封装件。响应于这种需求，一直致力于改进用于垂直层叠多个半导体晶片的技术，以增加嵌入在一个半导体封装件中的半导体晶片的数目。可以使用接合技术来垂直层叠多个半导体晶片。
发明内容
根据一个实施方式，一种层叠半导体晶片的方法包括以下步骤：提供基底基板，该基底基板具有设置在基底基板的表面上的第一接合端子；提供具有第二接合端子、第一通孔和第三接合端子的第一下半导体晶片；以及提供具有第四接合端子、第二通孔和第五接合端子的上半导体晶片。该方法进一步包括：将第一下半导体晶片与基底基板对齐，使得第二接合端子与第一接合端子接触；以及在第一下半导体晶片与基底基板之间提供第一粘合层。该方法还包括：将上半导体晶片与第一下半导体晶片对齐，使得第四接合端子与第三接合端子接触；以及在上半导体晶片和第一下半导体晶片之间提供第二粘合层。该方法附加包括：执行第一热压接合工序，以使第一粘合层和第二粘合层固化，由第一接合端子和第二接合端子形成第一接合结构，并且由第三接合端子和第四接合端子形成第二接合结构。
根据另一实施方式，一种层叠半导体晶片的方法包括以下步骤：提供基底基板，该基底基板具有设置在基底基板的表面上的第一接合端子；提供具有第二接合端子、第一通孔和第三接合端子的第一下半导体晶片；提供具有第四接合端子、第二通孔和第五接合端子的第一上半导体晶片；提供具有第六接合端子、第三通孔和第七接合端子的中间半导体晶片；以及提供具有第八接合端子、第四通孔和第九接合端子的第二上半导体晶片。该方法进一步包括：将第一下半导体晶片与基底基板对齐，使得第二接合端子与第一接合端子接触；以及在第一下半导体晶片和基底基板之间提供第一粘合层。该方法进一步包括：将第一上半导体晶片与第一下半导体晶片对齐，使得第四接合端子与第三接合端子接触；以及在第一上半导体晶片和第一下半导体晶片之间提供第二粘合层。该方法进一步包括：执行第一热压接合工序，以使第一粘合层和第二粘合层固化，由第一接合端子和第二接合端子形成第一接合结构，并且由第三接合端子和第四接合端子形成第二接合结构。该方法进一步包括：将中间半导体晶片与第一上半导体晶片对齐，使得第六接合端子与第五接合端子接触；以及在中间半导体晶片和第一上半导体晶片之间提供第三粘合层。该方法进一步包括：将第二上半导体晶片与中间半导体晶片对齐，使得第八接合端子与第七接合端子接触；以及在第二上半导体晶片和中间半导体晶片之间提供第四粘合层。该方法进一步包括：执行第二热压接合工序，以使第三粘合层和第四粘合层固化，由第五接合端子和第六接合端子形成第三接合结构，并且由第七接合端子和第八接合端子形成第四接合结构。
根据另一实施方式，一种层叠半导体晶片的方法包括以下步骤：在基底基板上层叠至少一个半导体晶片，其中，至少一个半导体晶片中的每一个包括位于半导体晶片的第一侧上的第一组接合端子、位于半导体晶片的第二侧上的第二组接合端子以及穿透半导体晶片的一组通孔，每个通孔将半导体晶片的第一侧上的接合端子连接到半导体晶片的第二侧上的接合端子。该方法进一步包括：将层叠在基底基板上方的至少一个半导体晶片按照第一侧向下的取向对齐，使得对齐层叠的至少一个半导体晶片中的最下层半导体晶片的第一组接合端子与基底基板的表面上的一组接合端子连接。该方法还包括：向对齐层叠的至少一个半导体晶片中的最上层半导体晶片的第二组接合端子施加热，使得所施加的热通过对齐层叠的至少一个半导体晶片的一组通孔传导，其中，由于所传导的热，最下层半导体晶片的第一组接合端子与基底基板的一组接合端子熔接，以在最下层半导体晶片和基底基板之间形成一组接合结构。
附图说明
图1、图2、图3、图4、图5和图6示出了根据一个实施方式的层叠半导体晶片的方法的截面图。
图7、图8、图9、图10、图11和图12示出了根据另一实施方式的层叠半导体晶片的方法的截面图。
图13示出了说明采用包括根据各种实施方式制造的至少一个半导体封装件的存储卡的电子系统的框图。
图14示出了说明包括根据各种实施方式制造的至少一个半导体封装的另一电子系统的框图。
具体实施方式
这里使用的术语可以对应于考虑到它们在各种实施方式中的功能而选择的词语，并且术语的含义可以被解释为根据实施方式所属领域的普通技术水平而不同。如果在本文中定义了术语，则该术语可以根据所提供的定义来解释。除非另外定义，否则本文所使用的术语(包括科学术语和技术术语)具有与本领域普通技术人员所通常理解的含义相同的含义。
应当理解，术语“第一”、“第二”、“第三”等在本文中用于标识各种元件。但是元件不应受这些术语的限制。这些术语用于将一个元件与另一个元件区分开，而不是用于指示元件的数目或顺序。例如，第一晶片和第二晶片、接合端子、接合结构、通孔和粘合层并不表示这种结构的数目限于两个或者第一个优先于第二个。
还应理解，当元件或层被称为在另一元件或层的“上”、“上方”、“下”、“下方”或“外部”时，该元件或层可以与另一元件或层直接接触，或者可以存在中间元件或中间层。用于描述元件或层之间的关系的其它词语应以类似的方式来解释(例如，“在...之间”与“直接在...之间”或“相邻”与“直接相邻”)。
诸如“在…之下”、“在…下方”、“下部的”、“在…上方”、“上部的”、“顶部的”、“底部的”等的空间相对术语可用于描述例如附图中示出的元件和/或特征与另一个元件和/或特征的关系。应当理解，空间相对术语旨在包括除了图中所示的方向之外的在使用和/或操作时装置的不同方向。例如，当图中的装置被翻转时，被描述为在另一元件或特征下方和/或之下的元件将被定向在另一元件或特征上方。当装置以其他方式定向(例如，旋转90度或在其它方位)时，应相应地解释本文所使用的空间相对描述符。
本文使用的词语“组(set)”可包括多个元件或仅具有单个元件。例如，对于各种实施方式，用于半导体晶片的一组通孔可包括多个通孔或仅包括单个通孔。类似地，至少一个半导体晶片可包括多个半导体晶片或仅具有单个半导体晶片。当至少一个半导体晶片的层叠件仅包括单个半导体晶片时，该单个半导体晶片表示层叠件中的最上层半导体晶片和最下层半导体晶片二者。层叠件中的相邻半导体晶片表示在层叠件中相邻的晶片。
半导体封装件可以包括诸如半导体芯片或半导体晶片之类的电子器件。半导体芯片或半导体晶片可以通过使用晶片切割(die sawing)工序将诸如晶圆的半导体基板分离成多个片来获得。半导体芯片可以对应于存储器芯片、逻辑芯片(包括专用集成电路(ASIC)芯片)或片上系统(SoC)。存储器芯片可以包括集成在半导体基板上的动态随机存取存储器(DRAM)电路、静态随机存取存储器(SRAM)电路、NAND型闪速存储器电路、NOR型闪速存储器电路、磁性随机存取存储器(MRAM)电路、电阻式随机存取存储器(ReRAM)电路、铁电式随机存取存储器(FeRAM)电路或相变随机存取存储器(PcRAM)电路。逻辑芯片可以包括集成在半导体基板上的逻辑电路。半导体封装件可用于诸如移动电话、与生物技术或医疗保健相关的电子系统或可穿戴电子系统之类的通信系统。
结合包括垂直层叠的多个半导体晶片的半导体封装件来描述本公开。多个半导体晶片可以通过硅通孔(TSV)结构彼此电连接。TSV结构中的每一个是指包括垂直穿透半导体晶片的诸如TSV之类的贯通电极的互连结构。多个半导体晶片可以通过包括TSV和凸块的互连结构彼此电连接。凸块可以是连接到TSV的连接构件。
本公开还可以涉及高带宽存储器(HBM)封装件。HBM封装件可以包括HBM接口，以提高HBM封装件和处理器芯片之间的数据传输速度。HBM封装件可以使用TSV结构来实现以增加输入/输出(I/O)端子的数目。支持HBM封装件的操作的处理器芯片可以是包括中央处理单元(CPU)或图形处理单元(GPU)、微处理器或微控制器、应用处理器(AP)、数字信号处理核心以及接口的专用集成电路(ASIC)芯片。
在整个说明书中，相同的附图标记表示相同的元件。尽管没有参照一附图提及或描述附图标记，但是可以参照另一附图提及或描述该附图标记。另外，即使一附图中未示出附图标记，也可以参照另一附图来提及或描述该附图标记。
图1至图6示出了根据一个实施方式的层叠半导体晶片的方法的截面图。
参照图1，第一下半导体晶片120可以附接到基底基板110。第二下半导体晶片130可以设置在第一下半导体晶片120上方。为了便于说明，可将第一下半导体晶片120和第二下半导体晶片130称为下半导体晶片。
基底基板110可以具有晶圆形状。基底基板110可以是包括集成电路的硅晶圆。在另一实施方式中，基底基板110可以是其上安装有下半导体晶片120和130的封装基板或内插件(interposer)。
基底基板110可以具有其上层叠有下半导体晶片120和130的表面111，并且电连接到第一下半导体晶片120的第一接合端子112可以设置在基底基板110的表面111上。设置在基底基板110上的第一接合端子112可以是导电连接凸块。基底基板110可以包括与第一接合端子112中的相应一个电连接的通孔113。通孔113的第一端可以分别连接到第一接合端子112。通孔113可以穿透基底基板110以具有硅通孔(TSV)形状。通孔113可以被称为第三通孔，以将通孔113与其它通孔区分开。
基底基板110可以包括彼此分隔开的第一区域114和第二区域115。第一区域114和第二区域115中的每一个可以包括第一接合端子112和通孔113。第一下半导体晶片120可以附接到基底基板110的第一区域114。
第一下半导体晶片120可以包括集成电路。第一下半导体晶片120可以具有与基底基板110的表面111面对的第一表面121和与基底基板110相对设置的第二表面122。第一下半导体晶片120可以包括基本上穿透第一下半导体晶片120的第一通孔123。第一通孔123可以对应于从第一下半导体晶片120的第一表面121基本上延伸到第二表面122的硅通孔(TSV)。第二接合端子126可以连接到第一通孔123的第一端，而第三接合端子127可以连接到第一通孔123的与第二接合端子126相对的第二端。
第二接合端子126可以提供用于将第一下半导体晶片120电连接到基底基板110的互连结构。第二接合端子126中的每一个可以包括连接到任意一个第一通孔123的第一连接凸块124和覆盖第一连接凸块124的一端的第一焊料凸块125。第二接合端子126的第一连接凸块124可以是诸如铜凸块之类的金属凸块。第二接合端子126的第一焊料凸块125可以包含锡银合金材料。可以在第一连接凸块124与第一焊料凸块125之间附加地设置诸如镍(Ni)层之类的阻挡层。第三接合端子127可以用作用于将第一下半导体晶片120电连接到第二下半导体晶片130的互连结构。第三接合端子127可以是导电连接凸块。
第一粘合层129可以设置在第一下半导体晶片120的第一表面121上。第一粘合层129可以覆盖第一下半导体晶片120的第一表面121并且可以内嵌第二接合端子126。第一粘合层129可以层压在第一下半导体晶片120的第一表面121上。第一粘合层129可以包括非导电膜(NCF)。
第一下半导体晶片120可以使用晶片附接技术附接到基底基板110的第一区域114。第一下半导体晶片120可以使用晶片附接工具来拾取并且可以与基底基板110的第一区域114对齐。结果，可将第一下半导体晶片120放置在基底基板110的第一区域114上。第一粘合层129可以用作用于将第一下半导体晶片120附接到基底基板110的表面111的介质材料。
第一下半导体晶片120可以附接到基底基板110，使得第一下半导体晶片120的第二接合端子126与基底基板110的第一接合端子112对齐。第一粘合层129可以以非固化状态存在于第一下半导体晶片120与基底基板110之间。在这种情况下，第一下半导体晶片120的第二接合端子126可以分别与基底基板110的第一接合端子112仅物理接触。也就是说，第一下半导体晶片120的第二接合端子126可不焊接或机械接合到基底基板110的第一接合端子112。因此，第一下半导体晶片120可以利用未固化的第一粘合层129不完全或不稳定地接合到基底基板110。因此，第一下半导体晶片120可以在预接合状态下附接到基底基板110。
为了获得第一下半导体晶片120和基底基板110之间的电稳定且可靠的互连状态，实施方式需要执行用于将热压接合技术应用于第一接合端子112和第二接合端子126的工艺操作。在第一下半导体晶片120附接到基底基板110之后，第二下半导体晶片130可以在尚未执行热压接合工序的预接合状态下附接到第一下半导体晶片120。
第二下半导体晶片130可以是与第一下半导体晶片120基本相同的半导体晶片。第二下半导体晶片130可以包括穿透第二下半导体晶片130的第四通孔133。第二下半导体晶片130可以进一步包括与第四通孔133的第一端连接的第七接合端子136和与第四通孔133的第二端连接的第八接合端子137。第七接合端子136中的每一个可以包括第二连接凸块134和第二焊料凸块135。第四粘合层139可以层压在第二下半导体晶片130的与第八接合端子137相对的表面上，以覆盖第七接合端子136。
参照图1和图2，第二下半导体晶片130可以使用晶片附接技术附接到第一下半导体晶片120。如图1中所示，可以将第二下半导体晶片130放置在第一下半导体晶片120上方并向下移动以将第二下半导体晶片130附接到第一下半导体晶片120，如图2所示。在这种情况下，第四粘合层139可以用作用于将第二下半导体晶片130附接到第一下半导体晶片120的介质材料。
参照图2，第四粘合层139可以以非固化状态存在于第一下半导体晶片120与第二下半导体晶片130之间。在这种情况下，第二下半导体晶片130的第七接合端子136可以分别与第一下半导体晶片120的第三接合端子127物理接触。也就是说，第七接合端子136的第二焊料凸块135可以与第一下半导体晶片120的第三接合端子127的表面接触。因此，第二下半导体晶片130可以在预接合状态下附接到第一下半导体晶片120。
参照图3，可以在下半导体晶片120和130上方提供上半导体晶片140。上半导体晶片140可以与下半导体晶片120和130基本相同。上半导体晶片140可以包括基本穿透上半导体晶片140的第二通孔143。上半导体晶片140还可以包括与第二通孔143的第一端连接的第四接合端子146和与第二通孔143的第二端连接的第五接合端子147。第四接合端子146中的每一个可以包括第三连接凸块144和第三焊料凸块145。第二粘合层149可以层压在上半导体晶片140的与第五接合端子147相对的表面上，以覆盖第四接合端子146。
执行热压接合工序的热压接合设备的热压接合工具101可以拾取上半导体晶片140并且可以将上半导体晶片140置于下半导体晶片120和130上方以将上半导体晶片和下半导体晶片120和130对齐。由于热压接合工具101包括加热器(未示出)，所以热压接合工具101可以将第三焊料凸块145加热至等于或高于第三焊料凸块145的熔点的温度。
参照图4，可以使用热压接合工具101执行第一热压接合工序。具体而言，保持上半导体晶片140的热压接合工具101可以向下移动以将上半导体晶片140置于第二下半导体晶片130上，并且可以向上半导体晶片140施加热和压力。施加到上半导体晶片140的热和压力可以被传导到位于上半导体晶片140下方的下半导体晶片120和130。
由热压接合工具101产生的热可以通过上半导体晶片140的第五接合端子147、第二通孔143和第四接合端子146被传导到第二下半导体晶片130的第八接合端子137。传导到第二下半导体晶片130的第八接合端子137的热可以通过第二下半导体130的第四通孔133和第七接合端子136被传导到第一下半导体晶片120的第三接合端子127。传导到第一下半导体晶片120的第三接合端子127的热可以通过第一下半导体晶片120的第一通孔123和第二接合端子126被传导到基底基板110的第一接合端子112。
由热压接合工具101产生的热可以通过彼此对齐的通孔143、133和123被传导到位于热压接合工具101下方的基底基板110。由热压接合工具101产生的热和压力可以引起基底基板110与第一下半导体晶片120之间、第一下半导体晶片120与第二下半导体晶片130之间以及第二下半导体晶片130与上半导体晶片140之间的第一热压接合。也就是说，基底基板110、第一下半导体晶片120、第二下半导体晶片130和上半导体晶片140可以通过热压接合技术同时彼此接合。
第二接合端子126和第一接合端子112可以通过第一热压接合工序彼此接合，以提供第一接合结构128。第七接合端子136和第三接合端子127可以通过第一热压接合工序彼此接合，以提供第二接合结构138。第四接合端子146和第八接合端子137可以通过第一热压接合工序彼此接合，以提供第六接合结构148。在执行第一热压接合工序的同时，第一焊料凸块125、第二焊料凸块135和第三焊料凸块145可以由于热压接合工具101所产生的热和压力而变形，以提供第一变形焊料凸块125'、第二变形焊料凸块135'和第三变形焊料凸块145'。第一变形焊料凸块125'可以将第一连接凸块124接合到第一接合端子112以形成第一接合结构128。对于一个实施方式，来自第一热压接合工序的热将第一焊料凸块125熔化，在移除热时，该熔化的第一焊料凸块125凝固以将第一连接凸块124导电地熔接到第一接合端子112。
基底基板110、第一下半导体晶片120、第二下半导体晶片130和上半导体晶片140可以通过由第一热压接合工序形成的第一接合结构128、第二接合结构138和第三接合结构148彼此物理地且电气地连接。
参照图5，可以使用第二热压接合工序将最上层半导体晶片150接合到上半导体晶片140。最上层半导体晶片150可以具有与上半导体晶片140的第五接合端子147面对的第六接合端子156。最上层半导体晶片150可以具有厚度T1。对于一些实施方式，厚度T1大于上半导体晶片140的厚度T2。在另外的实施方式中，最上层半导体晶片150中不包括通孔。
最上层半导体晶片150可以层叠在上半导体晶片140上并与上半导体晶片140对齐，使得第三粘合层设置在最上层半导体晶片150与上半导体晶片140之间。在最上层半导体晶片150被层叠在上半导体晶片140上之后，可以执行第二热压接合工序以使第三粘合层固化。第三粘合层可通过第二热压接合工序而变形，以提供第三变形粘合层159'。第六接合端子156和第五接合端子147可以通过第二热压接合工序彼此接合，以提供第三接合结构158。第六接合端子156的连接端子154和第五接合端子147可以通过第四变形焊料凸块155'彼此接合。通过第二热压接合工序固化的第三变形粘合层159'可以设置在最上层半导体晶片150与上半导体晶片140之间。
对于上面指出的实施方式，最上层半导体晶片150的厚度T1可以大于上半导体晶片140的厚度T2，并且在最上层半导体晶片150中不存在提供热传导路径的通孔。因此，即使执行第二热压接合工序，由第二热压接合工序产生的大部分热也会难以通过最上层半导体晶片150被传导到下半导体晶片120和130以及基底基板110。因此，可以在第二热压接合工序之前执行第一热压接合工序，以将上半导体晶片140、下半导体晶片120和130以及基底基板110彼此初始接合。
参照图6，在将下半导体晶片120和130、上半导体晶片140和最上层半导体晶片150依次层叠在基底基板110的第一区域114上并且彼此接合以形成第一层叠件102之后，可以在基底基板110的第二区域115上形成第二层叠件103。可以使用与形成第一层叠件102时使用的方法基本相同的方法来形成第二层叠件103。具体而言，可将第一下半导体晶片120-1和第二下半导体晶片130-1依次层叠在基底基板110的第二区域115上。然后可以将上半导体晶片140-1置于第二下半导体晶片130-1上，并且可向上半导体晶片140-1应用在形成第一层叠件102时使用的第一热压接合工序。此后，可以利用在形成第一层叠件102时使用的第二热压接合工序将最上层半导体晶片150-1接合到上半导体晶片140-1。结果，可以在基底基板110的第二区域115上形成包括下半导体晶片120-1和130-1、上半导体晶片140-1和最上层半导体晶片150-1的第二层叠件103。
在形成第一层叠件102之后，可以形成第二层叠件103。也就是说，可以使用两个单独的工艺操作来形成第一层叠件102和第二层叠件103。因此，可以抑制用于形成第一层叠件102的工序操作或用于形成第二层叠件103的工序操作在被同时执行时可能相互影响。结果，用于形成第一层叠件102的工序操作将不会导致在用于形成第二层叠件103的工序操作期间发生的工序失效。例如，可以防止第二层叠件103中的粘合层109由于在形成第一层叠件102时使用的热压接合工序而过早地固化。
图1至图6示出了在基底基板110的两个区域114和115中的每一个上层叠四个半导体晶片的示例。参照图7至图12描述多于四个的多个半导体晶片的层叠方法。
图7至图12示出了根据另一实施方式的层叠半导体晶片的方法的截面图。
参照图7，可以使用晶片附接技术将第一下半导体晶片220、第二下半导体晶片230和第三下半导体晶片260依次附接到基底基板210的第一区域214。在该阶段，没有半导体晶片附接到基底基板210的第二区域215。基底基板210可以包括设置在基底基板210的表面211上的第一接合端子212。基底基板210还可以包括电连接到第一接合端子212的第五通孔213。
第一下半导体晶片220可以具有与基底基板210的表面211面对的第一表面221和与基底基板210相对设置的第二表面222。第一下半导体晶片220可以包括第一通孔223。第一通孔223可以是从第一下半导体晶片220的第一表面221延伸到第一下半导体晶片220的第二表面222的硅通孔(TSV)。第二接合端子226可以分别连接到第一通孔223的第一端，而第三接合端子227可以分别连接到第一通孔223的第二端。第二接合端子226中的每一个可以包括连接到任意一个第一通孔223的第一连接凸块224和第一焊料凸块225。
第一粘合层229可以设置在第一下半导体晶片220的第一表面221上。第一粘合层229可以包括非导电膜(NCF)。第一粘合层229可以以非固化状态存在于第一下半导体晶片220与基底基板210之间。在这种情况下，第一下半导体晶片220的第二接合端子226可以分别与基底基板210的第一接合端子212未固定地物理接触。也就是说，第一下半导体晶片220可以在预接合状态下附接到基底基板210。
第二下半导体晶片230可以包括穿透第二下半导体晶片230的第六通孔233。第二下半导体晶片230可以包括与第六通孔233的第一端连接的第十一接合端子236和与第六通孔233的第二端连接的第十二接合端子237。第十一接合端子236中的每一个可以包括第二连接凸块234和第二焊料凸块235。第六粘合层239可以以非固化状态存在于第一下半导体晶片220与第二下半导体晶片230之间。
第三下半导体晶片260可以与第一下半导体晶片220和/或第二下半导体晶片230基本相同。第三下半导体晶片260可以包括第七通孔263。第三下半导体晶片260还可以包括与第七通孔263的第一端连接的第十三接合端子266和与第七通孔263的第二端连接的第十四接合端子267。第七粘合层269可以以非固化状态存在于第二下半导体晶片230与第三下半导体晶片260之间。
参照图8，可以在下半导体晶片220、230和260上设置第一上半导体晶片240。第一上半导体晶片240可以包括第二通孔243。第一上半导体晶片240还可以包括与第二通孔243的第一端连接的第四接合端子246以及与第二通孔243的第二端连接的第五接合端子247。
第一上半导体晶片240可以被置于第三下半导体晶片260上并与第三下半导体晶片260对齐。参照图1至图6描述的第一热压接合工序可以被应用于第一上半导体晶片240。在这种情况下，施加到第一上半导体晶片240的热和压力可以被传导到位于第一上半导体晶片240下方的第三下半导体晶片260、第二下半导体晶片230和第一下半导体晶片220。
施加到第一上半导体晶片240的热可以通过第一上半导体晶片240的第五接合端子247、第二通孔243和第四接合端子246被传导到第一下半导体晶片220的第三接合端子227。传导到第一下半导体晶片220的热可以通过第一下半导体晶片220的第三接合端子227、第一通孔223和第二接合端子226被传导到基底基板210的第一接合端子212。
第二接合端子226和第一接合端子212可以通过第一热压接合工序彼此接合，以提供第一接合结构228。第十一接合端子236和第三接合端子227可以通过第一热压接合工序彼此接合，以提供第二接合结构238。第四接合端子246和第十四接合端子267可以通过第一热压接合工序彼此接合，以提供第五接合结构248。第一焊料凸块(图7的225)可以由于第一热压接合工序期间产生的热和压力而变形，以提供第一变形焊料凸块225'。第一变形焊料凸块225'可以将第一连接凸块224接合到第一接合端子212，以形成第一接合结构228。第十一接合端子236的第二焊料凸块(图7的235)、第十三接合端子266的焊料凸块和第四接合端子246的焊料凸块也可以由于第一热压接合工序期间产生的热和压力而变形，以分别提供变形焊料凸块235'、265'和245'。
可以在第一上半导体晶片240下方层叠四个或更多个下半导体晶片。然而，如果设置在第一上半导体晶片240下方的下半导体晶片的数目过度增加，则由第一热压接合工序产生的热可能无法充足地传导至最下层半导体晶片，从而导致下半导体晶片与第一上半导体晶片240之间的接合失效。因此，在一些情况下，层叠在第一上半导体晶片240下方的下半导体晶片的数目可受到限制。对于不同的实施方式，可以改变几何形状和/或材料以容纳更大数目的晶片。例如，通孔可以更厚和/或由变化的热传导材料构造，以更高效地导热。
参照图9，一个或更多个中间半导体晶片270可以依次附接到第一上半导体晶片240。可以使用晶片附接技术拾取中间半导体晶片270，并且可以将中间半导体晶片270置于第一上半导体晶片240上并预接合到第一上半导体晶片240。中间半导体晶片270中的每一个可以包括第三通孔273。中间半导体晶片270中的每一个还可以包括与第三通孔273的第一端连接的第六接合端子276和与第三通孔273的第二端连接的第七接合端子277。第三粘合层279可以设置在中间半导体晶片270与第一上半导体晶片240之间。中间半导体晶片270可以附接到第一上半导体晶片240，使得第六接合端子276与第五接合端子247接触。例如，中间半导体晶片270的数目可以是两个或三个，并且中间半导体晶片270可以依次层叠在第一上半导体晶片240上并附接到第一上半导体晶片240。
参照图10，第二上半导体晶片280可以设置在中间半导体晶片270上。第二上半导体晶片280可以与第一上半导体晶片240基本相同。第二上半导体晶片280可以包括第四通孔283。第二上半导体晶片280还可以包括与第四通孔283的第一端连接的第八接合端子286和与第四通孔283的第二端连接的第九接合端子287。
第二上半导体晶片280可以被置于中间半导体晶片270上并与中间半导体晶片270对齐，并且可向第二上半导体晶片280应用参照图1至图6描述的第二热压接合工序。在这种情况下，施加到第二上半导体晶片280的热和压力可以通过第四通孔283被传导到位于第二上半导体晶片280下方的中间半导体晶片270。在第二热压接合工序之后，固化的粘合层289可以被设置在第二上半导体晶片280与中间半导体晶片270之间。
第八接合端子286和第七接合端子277可以通过第二热压接合工序彼此接合，以提供第四接合结构288。第六接合端子276和第五接合端子247也可以通过第二热压接合工序彼此接合，以提供第三接合结构278。
可以在第二上半导体晶片280下方层叠三个或更多个中间半导体晶片270。然而，如果设置在第二上半导体晶片280下方的中间半导体晶片的数目过度增加，则由第二热压接合工序产生的热可能无法充足地传导到最下层中间半导体晶片并且导致中间半导体晶片与第二上半导体晶片280之间的接合失效。因此，在一些情况下，层叠在第二上半导体晶片280下方的中间半导体晶片的数目可受到限制。对于不同的实施方式，可以改变几何形状和/或材料以容纳更多数目的晶片。例如，通孔可以更厚和/或由变化的热传导材料构造，以更高效地导热。
参照图11，可以使用第二热压接合工序将最上层半导体晶片250接合到第二上半导体晶片280。最上层半导体晶片250可以具有与第二上半导体晶片280的第九接合端子287面对的第十接合端子256。最上层半导体晶片250可以具有厚度T4。对于一些实施方式，厚度T4大于第二上半导体晶片280的厚度T3。在另外的实施方式中，最上层半导体晶片250中不包括通孔。
最上层半导体晶片250可以层叠在第二上半导体晶片280上，使得第五粘合层设置在最上层半导体晶片250与第二上半导体晶片280之间。在最上层半导体晶片250被层叠在第二上半导体晶片280上之后，可以执行第三热压接合工序以使第五粘合层固化。第五粘合层可以由于第三热压接合工序而变形，以提供第五固化粘合层289。第十粘合端子256和第九粘合端子287可以通过第三热压接合工序彼此接合，以提供第五接合结构258。
对于上面指出的实施方式，最上层半导体晶片250的厚度T4可以大于第二上半导体晶片280的厚度T3，并且最上层半导体晶片250中不存在提供热传导路径的通孔。因此，即使执行第三热压接合工序，由第三热压接合工序产生的大部分热也会难以通过最上层半导体晶片250传导到中间半导体晶片270。为此，第二热压接合工序可以在第三热压接合工序之前执行，以将第二上半导体晶片280和中间半导体晶片270彼此初始接合。
参照图12，在下半导体晶片220、230和260、第一上半导体晶片240、中间半导体晶片270、第二上半导体晶片280和最上层半导体晶片250依次层叠在基底基板210的第一区域214上并且彼此接合以形成第一层叠件202之后，可以在基底基板210的第二区域215上形成第二层叠件203。第二层叠件203可以使用与在形成第一层叠件202时使用的方法基本相同的方法形成。也就是说，下半导体晶片220-1、230-1和260-1、第一上半导体晶片240-1、中间半导体晶片270-1、第二上半导体晶片280-1和最上层半导体晶片250-1可以依次附接并接合到基底基板210的第二区域215。
再次参照图1，在第一下半导体晶片120被附接到基底基板110的同时，第一粘合层129可以将第一下半导体晶片120固定到基底基板110，以保持第一下半导体晶片120和基底基板110对齐。因此，当通过第一热压接合工序形成第一接合结构128时，可以保持第一连接凸块124与第一接合端子112之间的对齐状态。因此，可以减轻或避免第一连接凸块124与第一接合端子112之间的错位。
在第一下半导体晶片120被附接到基底基板110的同时，第一粘合层129可以设置在第一下半导体晶片120与基底基板110之间。因此，在使用热压接合工序将第一下半导体晶片120接合到基底基板110之后，可以不必执行利用底部填充层填充第一下半导体晶片120与基底基板110之间的空间的工序。因此，可以排除由于底部填充工序导致的工序失效。在下半导体晶片120和130附接到基底基板110之后，可以使用热压接合技术将下半导体晶片120和130以及上半导体晶片140同时彼此接合。结果，可以减少形成包括下半导体晶片120和130以及上半导体晶片140的层叠结构所花费的工序时间。
图13示出了说明包括采用根据所描述的实施方式制造的至少一个层叠封装件的存储卡7800的电子系统的框图。存储卡7800包括诸如非易失性存储器装置之类的存储器7810以及存储器控制器7820。存储器7810和存储器控制器7820可以存储数据并读出所存储的数据。存储器7810和存储器控制器7820中的至少一个可以包括根据所描述的实施方式制造的至少一个封装件。
存储器7810可以包括应用本公开所描述的实施方式的技术的非易失性存储器装置。存储器控制器7820可以控制存储器7810，使得响应于来自主机7830的读/写请求而读出所存储的数据或将数据进行存储。
图14示出说明包括根据所描述的实施方式制造的至少一个层叠封装件的电子系统8710的框图。电子系统8710可以包括控制器8711、输入/输出装置8712和存储器8713。控制器8711、输入/输出装置8712和存储器8713可以通过提供数据能够流动的路径的总线8715彼此联接。
在实施方式中，控制器8711可以包括微处理器、数字信号处理器、微控制器和/或能够执行与这些组件的功能相同功能的逻辑器件中的一个或更多个。控制器8711或存储器8713可以包括根据本公开所描述的实施方式制造的一个或更多个层叠封装件。输入/输出装置8712可以包括从小键盘、键盘、显示设备、触摸屏等中选择的至少一个组件。存储器8713是用于存储数据的设备。存储器8713可以存储控制器8711要执行的数据和/或命令等。
存储器8713可以包括诸如DRAM之类的易失性存储器装置和/或诸如闪速存储器之类的非易失性存储器装置。例如，闪速存储器可以被安装到诸如移动终端或台式计算机之类的信息处理系统。闪速存储器可以构成固态盘(SSD)。在这种情况下，电子系统8710可以将大量数据稳定地存储在闪速存储器系统中。
电子系统8710还可以包括被配置为向通信网络发送数据和从通信网络接收数据的接口8714。接口8714可以是有线型或无线型接口。例如，接口8714可以包括天线或者有线或无线收发器。
电子系统8710可以被实现为移动系统、个人计算机、工业计算机或执行各种功能的逻辑系统。例如，移动系统可以是个人数字助理(PDA)、便携式计算机、平板计算机、移动电话、智能电话、无线电话、膝上型计算机、存储卡、数字音乐系统和信息发送/接收系统中的任意一个。
如果电子系统8710是能够执行无线通信的装备，则电子系统8710可以被用在使用CDMA(码分多址)、GSM(全球移动通信系统)、NADC(北美数字蜂窝)、E-TDMA(增强时分多址)、WCDAM(宽带码分多址)、CDMA 2000、LTE(长期演进)或Wibro(无线宽带互联网)的技术的通信系统中。
已经出于说明性目的描述了本公开的实施方式。本领域技术人员将理解，在不脱离本公开和所附权利要求的范围和精神的情况下，可以进行各种修改、添加和替换。
相关申请的交叉引用
本申请要求于2018年4月30日提交的韩国专利申请No.10-2018-0050265的优先权，该韩国专利申请的全部内容通过引用并入本文中。

Claims (20)

1.一种层叠半导体晶片的方法，该方法包括以下步骤：
提供基底基板，该基底基板包括设置在所述基底基板的表面上的第一接合端子；
提供包括第二接合端子、第一通孔和第三接合端子的第一下半导体晶片；
提供包括第四接合端子、第二通孔和第五接合端子的上半导体晶片；
将所述第一下半导体晶片与所述基底基板对齐，使得所述第二接合端子与所述第一接合端子接触；
在所述第一下半导体晶片与所述基底基板之间提供第一粘合层；
将所述上半导体晶片与所述第一下半导体晶片对齐，使得所述第四接合端子与所述第三接合端子接触；
在所述上半导体晶片与所述第一下半导体晶片之间提供第二粘合层；以及
执行第一热压接合工序，以：
使所述第一粘合层和所述第二粘合层固化；
由所述第一接合端子和所述第二接合端子形成第一接合结构；并且
由所述第三接合端子和所述第四接合端子形成第二接合结构。
2.根据权利要求1所述的方法，
其中，所述第二接合端子包括与所述第一通孔连接的第二连接凸块和覆盖所述第二连接凸块的第二焊料凸块；并且
其中，所述第一热压接合工序使所述第二焊料凸块变形，以通过将所述第二连接凸块接合到所述第一接合端子来形成所述第一接合结构。
3.根据权利要求2所述的方法，其中，所述第一热压接合工序是在比所述第一粘合层的固化温度高的温度下执行的。
4.根据权利要求2所述的方法，其中，由所述第一热压接合工序产生的热通过所述第五接合端子、所述第二通孔、所述第四接合端子、所述第三接合端子、所述第一通孔和所述第二连接凸块被传导至所述第二焊料凸块。
5.根据权利要求1所述的方法，该方法还包括以下步骤：
提供包括第六接合端子并且厚度大于所述上半导体晶片的厚度的最上层半导体晶片；
将所述最上层半导体晶片与所述上半导体晶片对齐，使得所述第六接合端子与所述第五接合端子接触；
在所述最上层半导体晶片与所述上半导体晶片之间提供第三粘合层；以及
执行第二热压接合工序，以：
使所述第三粘合层固化；并且
由所述第五接合端子和所述第六接合端子形成第三接合结构。
6.根据权利要求1所述的方法，该方法还包括以下步骤：
在所述第一下半导体晶片与所述上半导体晶片之间提供第二下半导体晶片；以及
对齐所述第二下半导体晶片，使得所述第四接合端子通过所述第二下半导体晶片的通孔与所述第三接合端子接触。
7.根据权利要求1所述的方法，其中，通过所述第一热压接合工序形成包括所述第一下半导体晶片和所述上半导体晶片的第一层叠件，所述方法还包括以下步骤：
将附加下半导体晶片附接到所述基底基板的与所述第一层叠件间隔开的区域；以及
使用热压将附加上半导体晶片接合到所述附加下半导体晶片，以形成包括所述附加下半导体晶片和所述附加上半导体晶片的第二层叠件。
8.根据权利要求1所述的方法，其中，所述第一粘合层包括非导电膜NCF。
9.根据权利要求1所述的方法，
其中，所述第一下半导体晶片具有面向所述基底基板的第一表面；
其中，所述第二接合端子被设置在所述第一下半导体晶片的所述第一表面上；
其中，所述第三接合端子被设置在所述第一下半导体晶片的与所述基底基板相反的第二表面上；
其中，所述第一通孔穿透所述第一下半导体晶片；并且
其中，所述第二接合端子连接到所述第一通孔的第一端，所述第三接合端子连接到所述第一通孔的第二端。
10.根据权利要求1所述的方法，
其中，所述基底基板包括延伸到所述基底基板中并且连接到所述第一接合端子的第三通孔。
11.一种层叠半导体晶片的方法，该方法包括以下步骤：
提供基底基板，该基底基板包括设置在所述基底基板的表面上的第一接合端子；
提供包括第二接合端子、第一通孔和第三接合端子的第一下半导体晶片；
提供包括第四接合端子、第二通孔和第五接合端子的第一上半导体晶片；
提供包括第六接合端子、第三通孔和第七接合端子的中间半导体晶片；
提供包括第八接合端子、第四通孔和第九接合端子的第二上半导体晶片；
将所述第一下半导体晶片与所述基底基板对齐，使得所述第二接合端子与所述第一接合端子接触；
在所述第一下半导体晶片与所述基底基板之间提供第一粘合层；
将所述第一上半导体晶片与所述第一下半导体晶片对齐，使得所述第四接合端子与所述第三接合端子接触；
在所述第一上半导体晶片与所述第一下半导体晶片之间提供第二粘合层；
执行第一热压接合工序，以：
使所述第一粘合层和所述第二粘合层固化；
由所述第一接合端子和所述第二接合端子形成第一接合结构；并且
由所述第三接合端子和所述第四接合端子形成第二接合结构；
将所述中间半导体晶片与所述第一上半导体晶片对齐，使得所述第六接合端子与所述第五接合端子接触；
在所述中间半导体晶片与所述第一上半导体晶片之间提供第三粘合层；
将所述第二上半导体晶片与所述中间半导体晶片对齐，使得所述第八接合端子与所述第七接合端子接触；
在所述第二上半导体晶片与所述中间半导体晶片之间提供第四粘合层；以及
执行第二热压接合工序，以：
使所述第三粘合层和所述第四粘合层固化；
由所述第五接合端子和所述第六接合端子形成第三接合结构；并且
由所述第七接合端子和所述第八接合端子形成第四接合结构。
12.根据权利要求11所述的方法，
其中，所述第二接合端子包括与所述第一通孔连接的第二连接凸块和覆盖所述第二连接凸块的第二焊料凸块；并且
其中，所述第一热压接合工序使所述第二焊料凸块变形，以通过将所述第二连接凸块接合到所述第一接合端子来形成所述第一接合结构。
13.根据权利要求12所述的方法，其中，所述第一热压接合工序是在比所述第一粘合层的固化温度高的温度下进行的。
14.根据权利要求12所述的方法，其中，由所述第一热压接合工序产生的热通过所述第五接合端子、所述第二通孔、所述第四接合端子、所述第三接合端子、所述第一通孔和所述第二连接凸块被传导到所述第二焊料凸块。
15.根据权利要求11所述的方法，该方法还包括以下步骤：
提供包括第十接合端子并且厚度大于所述第二上半导体晶片的厚度的最上层半导体晶片；
将所述最上层半导体晶片与所述第二上半导体晶片对齐，使得所述第十接合端子与所述第九接合端子接触；
在所述最上层半导体晶片与所述第二上半导体晶片之间提供第五粘合层；以及
执行第三热压接合工序，以：
使所述第五粘合层固化；并且
由所述第九接合端子和所述第十接合端子形成第五接合结构。
16.根据权利要求11所述的方法，该方法还包括以下步骤：
在所述第一下半导体晶片与所述第一上半导体晶片之间提供第二下半导体晶片；
对齐所述第二下半导体晶片，使得所述第四接合端子通过所述第二下半导体晶片的通孔与所述第三接合端子接触；
在所述中间半导体晶片与所述第二上半导体晶片之间提供另一中间半导体晶片；以及
对齐所述另一中间半导体晶片，使得所述第八接合端子通过所述另一中间半导体晶片的通孔与所述第七接合端子接触。
17.根据权利要求11所述的方法，其中，通过所述第二热压接合工序形成包括所述第一下半导体晶片、所述第一上半导体晶片、所述中间半导体晶片和所述第二上半导体晶片的第一层叠件，所述方法还包括以下步骤：
将附加下半导体晶片附接到所述基底基板的与所述第一层叠件间隔开的区域；以及
使用热压将附加第一上半导体晶片接合到所述附加下半导体晶片，以形成包括所述附加下半导体晶片和所述附加第一上半导体晶片的第二层叠件。
18.一种层叠半导体晶片的方法，该方法包括以下步骤：
在基底基板上层叠至少一个半导体晶片，其中，所述至少一个半导体晶片中的每一个包括位于所述半导体晶片的第一侧上的第一组接合端子、位于所述半导体晶片的第二侧上的第二组接合端子以及穿透所述半导体晶片的一组通孔，每个通孔将所述半导体晶片的第一侧上的接合端子连接到所述半导体晶片的第二侧上的接合端子；
将层叠在所述基底基板上方的所述至少一个半导体晶片按照第一侧向下的取向对齐，使得对齐层叠的至少一个半导体晶片中的最下层半导体晶片的所述第一组接合端子与所述基底基板的表面上的一组接合端子连接；以及
向对齐层叠的至少一个半导体晶片中的最上层半导体晶片的所述第二组接合端子施加热，使得所施加的热通过对齐层叠的至少一个半导体晶片的所述一组通孔传导，其中，由于所传导的热，所述最下层半导体晶片的所述第一组接合端子与所述基底基板的所述一组接合端子熔接，以在所述最下层半导体晶片与所述基底基板之间形成一组接合结构。
19.根据权利要求18所述的方法，该方法还包括在所述最下层半导体晶片与所述基底基板之间设置粘合层，其中，所传导的热使所述粘合层固化。
20.根据权利要求19所述的方法，该方法还包括在所层叠的至少一个半导体晶片的相邻半导体晶片之间设置至少一个附加粘合层，其中，所传导的热使所述至少一个附加粘合层固化，并且其中，由于所传导的热，所述相邻半导体晶片之间的第一组接合端子和第二组接合端子熔接，以在所述相邻半导体晶片之间形成附加组的接合结构。
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US11387222B2 (en) * 2019-10-18 2022-07-12 Taiwan Semiconductor Manufacturing Co., Ltd. Integrated circuit package and method
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US12087733B2 (en) * 2021-05-13 2024-09-10 Taiwan Semiconductor Manufacturing Co., Ltd. Packages with multiple types of underfill and method forming the same

Citations (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH08250541A (ja) * 1995-03-07 1996-09-27 Nitto Denko Corp 半導体素子実装基板およびその製造方法
KR20010004890A (ko) * 1999-06-30 2001-01-15 김영환 웨이퍼 레벨 패키지의 제조방법
JP2004146751A (ja) * 2002-08-30 2004-05-20 Nec Corp 半導体装置及びその製造方法、回路基板、電子機器並びに半導体装置の製造装置
US20050236104A1 (en) * 2004-04-27 2005-10-27 Shuichi Tanaka Method for mounting semiconductor device, as well as circuit board, electrooptic device, and electronic device
US20110316164A1 (en) * 2010-06-29 2011-12-29 Chih-Chin Liao Corrugated die edge for stacked die semiconductor package
US20130183799A1 (en) * 2012-01-17 2013-07-18 Elpida Memory, Inc. Method for manufacturing semiconductor device
CN107134430A (zh) * 2016-02-29 2017-09-05 商升特公司 堆叠半导体管芯以用于系统级esd保护的半导体装置和方法
CN107564894A (zh) * 2016-06-30 2018-01-09 三星电子株式会社 制造半导体封装的方法

Family Cites Families (15)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8008764B2 (en) * 2008-04-28 2011-08-30 International Business Machines Corporation Bridges for interconnecting interposers in multi-chip integrated circuits
US8822281B2 (en) * 2010-02-23 2014-09-02 Stats Chippac, Ltd. Semiconductor device and method of forming TMV and TSV in WLCSP using same carrier
US8546188B2 (en) * 2010-04-09 2013-10-01 International Business Machines Corporation Bow-balanced 3D chip stacking
US9224647B2 (en) * 2010-09-24 2015-12-29 Stats Chippac, Ltd. Semiconductor device and method of forming TSV interposer with semiconductor die and build-up interconnect structure on opposing surfaces of the interposer
KR101813260B1 (ko) * 2011-01-14 2018-01-02 삼성전자주식회사 패턴형성 가능한 접착 조성물, 이를 이용한 반도체 패키지, 및 이의 제조방법
KR20130044048A (ko) * 2011-10-21 2013-05-02 에스케이하이닉스 주식회사 반도체 웨이퍼 및 이를 이용한 스택 패키지 제조방법
US20140159238A1 (en) 2012-12-07 2014-06-12 Qualcomm Incorporated Package having thermal compression flip chip (tcfc) and chip with reflow bonding on lead
US9257399B2 (en) * 2013-10-17 2016-02-09 Taiwan Semiconductor Manufacturing Company, Ltd. 3D integrated circuit and methods of forming the same
US9570421B2 (en) * 2013-11-14 2017-02-14 Taiwan Semiconductor Manufacturing Co., Ltd. Stacking of multiple dies for forming three dimensional integrated circuit (3DIC) structure
KR102258739B1 (ko) * 2014-03-26 2021-06-02 삼성전자주식회사 하이브리드 적층 구조를 갖는 반도체 소자 및 그 제조방법
US20150348874A1 (en) * 2014-05-29 2015-12-03 Taiwan Semiconductor Manufacturing Company, Ltd. 3DIC Interconnect Devices and Methods of Forming Same
US10418350B2 (en) * 2014-08-11 2019-09-17 Massachusetts Institute Of Technology Semiconductor structures for assembly in multi-layer semiconductor devices including at least one semiconductor structure
US9881904B2 (en) * 2014-11-05 2018-01-30 Massachusetts Institute Of Technology Multi-layer semiconductor devices fabricated using a combination of substrate and via structures and fabrication techniques
KR102467034B1 (ko) * 2016-05-17 2022-11-14 삼성전자주식회사 반도체 패키지
US10586909B2 (en) * 2016-10-11 2020-03-10 Massachusetts Institute Of Technology Cryogenic electronic packages and assemblies

Patent Citations (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH08250541A (ja) * 1995-03-07 1996-09-27 Nitto Denko Corp 半導体素子実装基板およびその製造方法
KR20010004890A (ko) * 1999-06-30 2001-01-15 김영환 웨이퍼 레벨 패키지의 제조방법
JP2004146751A (ja) * 2002-08-30 2004-05-20 Nec Corp 半導体装置及びその製造方法、回路基板、電子機器並びに半導体装置の製造装置
US20050236104A1 (en) * 2004-04-27 2005-10-27 Shuichi Tanaka Method for mounting semiconductor device, as well as circuit board, electrooptic device, and electronic device
US20110316164A1 (en) * 2010-06-29 2011-12-29 Chih-Chin Liao Corrugated die edge for stacked die semiconductor package
US20130183799A1 (en) * 2012-01-17 2013-07-18 Elpida Memory, Inc. Method for manufacturing semiconductor device
CN107134430A (zh) * 2016-02-29 2017-09-05 商升特公司 堆叠半导体管芯以用于系统级esd保护的半导体装置和方法
CN107564894A (zh) * 2016-06-30 2018-01-09 三星电子株式会社 制造半导体封装的方法

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