CN107564894A - 制造半导体封装的方法 - Google Patents

制造半导体封装的方法 Download PDF

Info

Publication number
CN107564894A
CN107564894A CN201710513118.8A CN201710513118A CN107564894A CN 107564894 A CN107564894 A CN 107564894A CN 201710513118 A CN201710513118 A CN 201710513118A CN 107564894 A CN107564894 A CN 107564894A
Authority
CN
China
Prior art keywords
chip
sub
encapsulation unit
semiconductor chip
semiconductor
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
CN201710513118.8A
Other languages
English (en)
Other versions
CN107564894B (zh
Inventor
金知晃
沈钟辅
韩相旭
赵汊济
张根豪
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Samsung Electronics Co Ltd
Original Assignee
Samsung Electronics Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Samsung Electronics Co Ltd filed Critical Samsung Electronics Co Ltd
Publication of CN107564894A publication Critical patent/CN107564894A/zh
Application granted granted Critical
Publication of CN107564894B publication Critical patent/CN107564894B/zh
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/50—Multistep manufacturing processes of assemblies consisting of devices, each device being of a type provided for in group H01L27/00 or H01L29/00
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/10—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices having separate containers
    • H01L25/105—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices having separate containers the devices being of a type provided for in group H01L27/00
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H01L21/561—Batch processing
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H01L21/563—Encapsulation of active face of flip-chip device, e.g. underfilling or underencapsulation of flip-chip, encapsulation preform on chip or mounting substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
    • H01L21/683—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H01L21/6835—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3157—Partial encapsulation or coating
    • H01L23/3185—Partial encapsulation or coating the coating covering also the sidewalls of the semiconductor body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49811—Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49811—Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads
    • H01L23/49816—Spherical bumps on the substrate for external connection, e.g. ball grid arrays [BGA]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L24/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L24/19—Manufacturing methods of high density interconnect preforms
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L24/20—Structure, shape, material or disposition of high density interconnect preforms
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L24/33—Structure, shape, material or disposition of the layer connectors after the connecting process of a plurality of layer connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L24/80 - H01L24/90
    • H01L24/92—Specific sequence of method steps
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/93—Batch processes
    • H01L24/94—Batch processes at wafer-level, i.e. with connecting carried out on a wafer comprising a plurality of undiced individual devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/93—Batch processes
    • H01L24/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L24/96—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being encapsulated in a common layer, e.g. neo-wafer or pseudo-wafer, said common layer being separable into individual assemblies after connecting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L25/065—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L25/0657—Stacked arrangements of devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H01L21/568—Temporary substrate used as encapsulation process aid
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2221/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof covered by H01L21/00
    • H01L2221/67—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere
    • H01L2221/683—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H01L2221/68304—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
    • H01L2221/68327—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support used during dicing or grinding
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/0556—Disposition
    • H01L2224/0557—Disposition the external layer being disposed on a via connection of the semiconductor or solid-state body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/1302—Disposition
    • H01L2224/13025—Disposition the bump connector being disposed on a via connection of the semiconductor or solid-state body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13075—Plural core members
    • H01L2224/1308—Plural core members being stacked
    • H01L2224/13082—Two-layer arrangements
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/13101—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of less than 400°C
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/13138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/13147—Copper [Cu] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16135—Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/16145—Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16135—Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/16145—Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
    • H01L2224/16146—Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked the bump connector connecting to a via connection in the semiconductor or solid-state body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/17—Structure, shape, material or disposition of the bump connectors after the connecting process of a plurality of bump connectors
    • H01L2224/171—Disposition
    • H01L2224/1718—Disposition being disposed on at least two different sides of the body, e.g. dual array
    • H01L2224/17181—On opposite sides of the body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L2224/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H01L2224/29001—Core members of the layer connector
    • H01L2224/29099—Material
    • H01L2224/29198—Material with a principal constituent of the material being a combination of two or more materials in the form of a matrix with a filler, i.e. being a hybrid material, e.g. segmented structures, foams
    • H01L2224/29199—Material of the matrix
    • H01L2224/2929—Material of the matrix with a principal constituent of the material being a polymer, e.g. polyester, phenolic based polymer, epoxy
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L2224/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H01L2224/29001—Core members of the layer connector
    • H01L2224/29099—Material
    • H01L2224/29198—Material with a principal constituent of the material being a combination of two or more materials in the form of a matrix with a filler, i.e. being a hybrid material, e.g. segmented structures, foams
    • H01L2224/29298—Fillers
    • H01L2224/29299—Base material
    • H01L2224/29386—Base material with a principal constituent of the material being a non metallic, non metalloid inorganic material
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32135—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/32145—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/33—Structure, shape, material or disposition of the layer connectors after the connecting process of a plurality of layer connectors
    • H01L2224/331—Disposition
    • H01L2224/3318—Disposition being disposed on at least two different sides of the body, e.g. dual array
    • H01L2224/33181—On opposite sides of the body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73201—Location after the connecting process on the same surface
    • H01L2224/73203—Bump and layer connectors
    • H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/81001—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector involving a temporary auxiliary member not forming part of the bonding apparatus
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/818—Bonding techniques
    • H01L2224/81801—Soldering or alloying
    • H01L2224/81815—Reflow soldering
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/838—Bonding techniques
    • H01L2224/8385—Bonding techniques using a polymer adhesive, e.g. an adhesive based on silicone, epoxy, polyimide, polyester
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
    • H01L2224/92—Specific sequence of method steps
    • H01L2224/921—Connecting a surface with connectors of different types
    • H01L2224/9212—Sequential connecting processes
    • H01L2224/92122—Sequential connecting processes the first connecting process involving a bump connector
    • H01L2224/92125—Sequential connecting processes the first connecting process involving a bump connector the second connecting process involving a layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
    • H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/06513—Bump or bump-like direct electrical connections between devices, e.g. flip-chip connection, solder bumps
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
    • H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/06517—Bump or bump-like direct electrical connections from device to substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
    • H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/06541—Conductive via connections through the device, e.g. vertical interconnects, through silicon via [TSV]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
    • H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/06555—Geometry of the stack, e.g. form of the devices, geometry to facilitate stacking
    • H01L2225/06565—Geometry of the stack, e.g. form of the devices, geometry to facilitate stacking the devices having the same size and there being no auxiliary carrier between the devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
    • H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/06555—Geometry of the stack, e.g. form of the devices, geometry to facilitate stacking
    • H01L2225/06568—Geometry of the stack, e.g. form of the devices, geometry to facilitate stacking the devices decreasing in size, e.g. pyramidical stack
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
    • H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/06596—Structural arrangements for testing
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/10—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers
    • H01L2225/1005—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/1011—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00 the containers being in a stacked arrangement
    • H01L2225/1017—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00 the containers being in a stacked arrangement the lowermost container comprising a device support
    • H01L2225/1023—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00 the containers being in a stacked arrangement the lowermost container comprising a device support the support being an insulating substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/10—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers
    • H01L2225/1005—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/1011—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00 the containers being in a stacked arrangement
    • H01L2225/1047—Details of electrical connections between containers
    • H01L2225/1058—Bump or bump-like electrical connections, e.g. balls, pillars, posts
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H01L23/3121—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation
    • H01L23/3128—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation the substrate having spherical bumps for external connection
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L24/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L24/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L24/17—Structure, shape, material or disposition of the bump connectors after the connecting process of a plurality of bump connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L24/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/73—Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/14—Integrated circuits
    • H01L2924/143—Digital devices
    • H01L2924/1431—Logic devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/14—Integrated circuits
    • H01L2924/143—Digital devices
    • H01L2924/1434—Memory
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Wire Bonding (AREA)
  • Semiconductor Integrated Circuits (AREA)
  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)

Abstract

本发明公开了一种制造半导体封装的方法，该方法包括：形成至少两个部分封装芯片叠层，每个部分封装芯片叠层包括每个包含多个基板通孔(TSV)的至少两个半导体芯片，并包括围绕所述至少两个半导体芯片的侧表面的第一模制层；以及在垂直于封装基板的顶表面的方向上在封装基板上顺序地安装所述至少两个部分封装芯片叠层，使得所述至少两个部分封装芯片叠层包括第一部分封装芯片叠层和直接连接到第一部分封装芯片叠层的第二部分封装芯片叠层。

Description

制造半导体封装的方法
技术领域
本公开涉及一种半导体封装和制造该半导体封装的方法，更具体地，涉及一种包括基板通孔(TSV)的半导体封装和制造该半导体封装的方法。
背景技术
随着电子产业的迅速进步以及用户需求增加，电子设备正变得越来越小型化和多功能。因此，已经提出每个包括TSV的多个半导体芯片在垂直方向上堆叠的半导体封装。
发明内容
各种公开的实施方式提供一种具有提高的可靠性的半导体封装。
某些公开的实施方式还提供一种制造半导体封装的方法，其减少在堆叠半导体芯片的过程中发生的缺陷。
在某些实施方式中，一种制造半导体封装的方法包括：提供第一子封装单元，该第一子封装单元包括垂直堆叠的至少两个第一半导体芯片和围绕所述至少两个第一半导体芯片的侧表面的第一模制层；以及提供第二子封装单元，该第二子封装单元包括垂直堆叠的至少两个第二半导体芯片以及围绕所述至少两个第二半导体芯片的侧表面并与第一模制层垂直地间隔开的第二模制层。第二子封装单元设置在第一子封装单元上。所述至少两个第一半导体芯片和所述至少两个第二半导体芯片每个包括基板通孔(TSV)。此外，所述至少两个第一半导体芯片中的最上面的第一半导体芯片电连接到所述至少两个第二半导体芯片中的最下面的第二半导体芯片，而在它们之间没有封装基板。提供一种封装基板，所述至少两个第一半导体芯片和所述至少两个第二半导体芯片上垂直地堆叠在该封装基板上以形成半导体封装。
在某些实施方式中，一种制造半导体封装的方法包括：提供封装基板；以及通过首先在封装基板上堆叠第一子封装单元以及随后在第一子封装单元上堆叠第二子封装单元，沿着垂直于封装基板的顶表面的方向在封装基板上堆叠多个子封装单元。所述多个子封装单元中的每个包括：第一缓冲器芯片或逻辑芯片；设置在第一缓冲器芯片或逻辑芯片上的第一存储器芯片；设置在第一存储器芯片上的第二存储器芯片；以及对于每个子封装单元，围绕第一存储器芯片和第二存储器芯片的每个的侧表面的第一模制层，其中第一缓冲器芯片或逻辑芯片、第一存储器芯片和第二存储器芯片中的每个包括基板通孔(TSV)。该方法还包括进行回流工艺以将第一子封装单元直接电连接到第二子封装单元。
在某些实施方式中，一种制造半导体封装的方法包括：形成至少两个部分封装芯片叠层，每个部分封装芯片叠层包括每个包含多个基板通孔(TSV)的至少两个半导体芯片，并包括围绕所述至少两个半导体芯片的侧部的第一模制层；以及在垂直于封装基板的顶部的方向上在封装基板上顺序地安装所述至少两个部分封装芯片叠层，使得所述至少两个部分封装芯片叠层包括第一部分封装芯片叠层和直接连接到第一部分封装芯片叠层的第二部分封装芯片叠层。
附图说明
从以下结合附图的详细描述，本发明构思的实施方式将被更清楚地理解，附图中：
图1至图13是示出根据示范性实施方式的制造半导体封装的方法的剖视图；
图14至图18是示出根据示范性实施方式的制造半导体封装的方法的剖视图；
图19是示出根据示范性实施方式的半导体封装的剖视图；
图20是示出根据示范性实施方式的半导体封装的剖视图；以及
图21是示出根据示范性实施方式的半导体封装的剖视图。
具体实施方式
在下文，将参照附图详细描述实施方式。在附图中，为了清楚起见，层和区域的尺寸和相对尺寸可以被夸大。相同的数字始终指代相同的元件。尽管不同的附图示出示范性实施方式的变型，但是这些附图不必旨在彼此相互排斥。而是，如将从以下的详细描述的上下文看到的，当将附图及其描述整体地考虑时，在不同的附图中绘出和描述的某些特征可以与来自其它附图的其它特征组合以产生各种实施方式。
尽管这里描述的附图可以使用诸如“一个实施方式”或“某些实施方式”的语言来提及，但是这些附图及其相应的描述不旨在与其它附图或描述相互排斥，除非上下文如此指示。因此，来自某些附图的某些方面可以与其它附图中的某些特征相同，和/或某些附图可以是特定示例性实施方式的不同表示或不同部分。
将理解，尽管这里可以使用术语第一、第二、第三等来描述各种元件、部件、区域、层和/或部分，但是这些元件、部件、区域、层和/或部分不应受这些术语限制。除非上下文另外地指示，否则这些术语仅用于将一个元件、部件、区域、层或部分与另一个元件、部件、区域、层或部分区别开，例如作为命名规则。因此，在说明书的一个部分中在下面论述的第一元件、部件、区域、层或部分可以在说明书的另一个部分中或在权利要求中被称为第二元件、部件、区域、层或部分，而没有背离本发明的教导。此外，在某些情况下，即使术语在说明书中没有使用“第一”、“第二”等描述，它仍然可以在权利要求中被称为“第一”或“第二”，以便使不同的被主张的元件相互区别开。
将理解，当称一个元件“连接”或“联接”到另一元件或“在”另一元件“上”时，它可以直接连接或联接到所述另一元件或直接在所述另一元件上，或者还可以存在居间元件。相反，当一元件被称为“直接连接”或“直接联接”到另一元件或“接触”另一元件或“与”另一元件“接触”时，不存在居间元件。用于描述元件之间的关系的其它词语应当以类似的方式解释(例如，“在……之间”与“直接在……之间”、“与……相邻”与“直接与……相邻”等)。
为了描述的方便，这里可以使用空间关系术语诸如“在……下面”、“在……之下”、“下”、“在……之上”、“上”等来描述一个元件或特征与另一个(另一些)元件或特征如附图所示的关系。将理解，空间关系术语旨在涵盖除了附图中所示的取向之外装置在使用或操作中的其它不同取向。例如，如果附图中的装置被翻转，则被描述为“在”其它元件“下面”或“之下”的元件将会“在”其它元件或特征“之上”取向。因此，术语“在……下面”能够涵盖之上和之下两种取向。装置可以另外地取向(旋转90度或在其它取向)，这里使用的空间关系描述符被相应地解释。
术语诸如“相同”、“相等”、“平面的”或“共平面”(如这里在参照取向、布局、位置、形状、尺寸、量或其它度量时使用的)不必表示精确相同的取向、布局、位置、形状、尺寸、量或其它度量，而是旨在涵盖可能例如由于制造工艺发生的在允许误差内的几乎相同的取向、布局、位置、形状、尺寸、量或其它度量。术语“基本上”可以在这里用于强调这个含义，除非上下文或其它陈述另外指示。例如，被描述为“基本上相同”、“基本上相等”或“基本上平坦”的项目可以精确地相同、相等或平坦，或可以是在可能例如由于制造工艺而发生的允许误差内的相同、相等或平坦。
诸如“约”或“大约”的术语可以反映仅以小的相对的方式变化和/或以不显著改变某些元件的操作、功能或结构的方式变化的量、尺寸、取向或布局。例如，从“约0.1至约1”的范围可以涵盖诸如0.1附近的0％-5％的偏差和在1附近的0％至5％的偏差的范围，特别是如果这样的偏差保持与所列范围相同的效果。
如这里使用的，被描述为“电连接”的项目被配置为使得电信号可以从一个项目传递到另一个。因此，物理地连接到无源电绝缘部件(例如印刷电路板的半固化片层、连接两个器件的电绝缘粘合剂、电绝缘底填充层或电绝缘模制层等)的无源导电部件(例如导线、焊盘、内部电线等)不电连接到那个部件。此外，彼此“直接电连接”的项目通过一个或更多个无源元件(诸如，例如导线、焊盘、内部电线、通孔等)电连接。因而，被直接电连接的部件不包括通过有源元件(诸如晶体管或二极管)电连接的部件。被直接电连接的元件可以被直接物理连接并被直接电连接。
图1至图13是示出根据示范性实施方式的制造半导体封装100的方法的剖视图。
参照图1，可以制备第一半导体晶片W1。第一半导体晶片W1可以包括通过第一划片槽(scribe lane)SL1彼此区分的多个第一半导体芯片C1。该多个第一半导体芯片C1可以每个包括第一半导体基板110、第一半导体器件层120和第一基板通孔(TSV)130。第一半导体基板110可以包括彼此相反的第一表面112和第二表面114a。第一半导体器件层120可以形成在第一半导体基板110的第一表面112上。第一TSV 130可以形成为从第一半导体基板110的第一表面112穿过第一半导体器件层120延伸到第一半导体基板110的内部。
第一半导体器件层120可以包括各种类型的多个单独的器件，并可以是例如集成电路器件。所述多个单独的器件可以包括各种微电子器件，例如金属氧化物半导体场效应晶体管(MOSFET)诸如互补金属-绝缘体-半导体(CMOS)晶体管、系统大规模集成(LSI)、图像传感器诸如CMOS成像传感器(CIS)、微机电系统(MEMS)、有源器件、无源器件等。第一半导体器件层120可以包括多个布线结构，该多个布线结构用于将所述多个单独的器件连接到形成在第一半导体基板110上的其它布线。然而，包括在第一半导体器件层120中的所述多个单独的器件的类型不限于以上描述的种类。
第一TSV 130可以从第一半导体基板110的第一表面112延伸到第一半导体基板110的内部。第一TSV 130的至少一部分可以具有柱形状。第一TSV 130可以包括具有柱形状的埋入导电层以及形成为围绕埋入导电层的侧表面的阻挡层。过孔绝缘层(未示出)可以设置在第一半导体基板110和第一TSV 130之间。第一TSV 130可以包括氧化物、氮化物、碳化物、聚合物或其组合。
在随后的工艺中，可以去除第一半导体基板110的一部分，并且第一TSV 130可以包括穿过从其去除了所述一部分的第一半导体基板110的导电材料。例如，第一TSV 130可以包括阻挡层和填充阻挡层内部的掩埋导电层。或者，例如，第一TSV 130可以包括阻挡层、填充阻挡层内部的埋入导电层以及金属布线层的部分和/或过路插塞的部分。第一TSV 130还可以穿过第一半导体器件层120，并可以连接到第一半导体器件层120内的电路(例如，以连接到第一半导体器件层120的集成电路)。
参照图2，电连接到第一TSV 130的第一连接焊盘132可以形成在第一半导体基板110上，第一连接凸块134可以形成在第一连接焊盘132上。
尽管没有示出，但是第一连接凸块134可以包括柱层(未示出)和设置在柱层上的焊料层(未示出)。例如，包括暴露第一连接焊盘132的一部分的开口(未示出)的掩模图案(未示出)可以形成在第一半导体器件层120上。随后，柱层和焊料层可以顺序地堆叠在第一连接焊盘132的通过掩模图案暴露的部分上。例如，柱层和焊料层可以通过执行电镀工艺形成。随后，可以去除掩模图案，并且具有凸形状的焊料层可以通过经由热处理使焊料层回流来形成。尽管在图2中第一连接凸块134被示意性地示为具有凸形状，但是第一连接凸块134的形状不限于上述形状。例如，第一连接凸块134可以形成为使得柱层具有包括垂直于第一半导体器件层120的顶部的侧壁的圆柱形形状，并且焊料层基本上具有在柱层上的半球形状。此外，柱层可以形成为其中包括不同金属材料的多个金属层堆叠的结构。
在示范性实施方式中，第一连接凸块134可以具有约20μm至约100μm的水平宽度(例如，在平行于第一半导体晶片W1的顶部的方向上的宽度)，但是不限于此。在一些实施方式中，第一连接凸块134可以具有约20μm至约60μm的水平宽度。
参照图3，其上形成第一连接凸块134的第一半导体晶片W1可以附接在第一载体基板10上。第一载体基板10可以包括第一支撑基板12和第一胶层(glue layer)14。第一半导体晶片W1可以附接在第一载体基板10上，其中第一连接凸块134面对第一载体基板10。第一连接凸块134可以被第一胶层14围绕。第一半导体基板110的第一表面112的因为没有被第一连接凸块134覆盖而暴露的部分可以接触第一胶层14。
参照图4，第一TSV 130可以通过去除第一半导体基板110的一部分而暴露。第一TSV 130可以暴露于第一半导体基板110的第二表面114。由于第一TSV 130暴露于第一半导体基板110的第二表面114，所以第一TSV 130可以具有穿过第一半导体基板110的形状。此外，在一些实施方式中，第一半导体基板110的一部分可以被去除，使得第一TSV 130相对于第二表面114进一步突出，因此延伸超过第二表面114。
例如，为了使第一TSV 130暴露，第一半导体基板110的一部分可以通过化学机械抛光(CMP)工艺、回蚀刻工艺或其组合去除。
随后，可以形成覆盖第一半导体晶片W1的暴露表面(例如第一半导体基板110的第二表面114)的第一后保护层136。第一后保护层136可以通过例如旋涂工艺或喷射工艺形成。第一后保护层136可以包括例如绝缘聚合物。为了形成第一后保护层136，可以形成覆盖第一半导体基板110的第二表面114和暴露的第一TSV 130的绝缘聚合物层，然后第一TSV130可以通过经由回蚀刻工艺去除绝缘聚合物层的一部分而暴露。
可以形成电连接到第一TSV 130的通过第一后保护层136暴露的部分的第一上连接焊盘138。可选地，可以省略第一上连接焊盘138。
参照图5，可以制备第二半导体芯片C2。为了制备第二半导体芯片C2，第二半导体晶片(未示出)可以与图1至图4所示的第一半导体晶片W1类似地处理，然后，第二半导体芯片C2可以通过分割或切割第二半导体晶片来制备。
第二半导体芯片C2可以包括第二半导体基板210和形成在第二半导体基板210上的第二半导体器件层220。第二半导体器件层220可以形成集成电路，并可以包括多个单独的器件，包括系统LSI、快闪存储器、动态随机存取存储器(DRAM)、静态随机存取存储器(SRAM)、电可擦除可编程只读存储器(EEPROM)、相变随机存取存储器(PRAM)、磁阻随机存取存储器(MRAM)或电阻随机存取存储器(RRAM)。
在示范性实施方式中，第二半导体晶片可以是包括通过与形成第一半导体晶片W1的工艺不同的工艺形成的不同种类的单独器件的半导体晶片。因此，第二半导体芯片C2可以是包括与第一半导体芯片C1中包括的单独器件不同的单独器件的不同种类的半导体芯片。例如，第一半导体晶片W1可以包括包含系统LSI的第一半导体芯片C1，第二半导体芯片C2可以包括DRAM。第一半导体芯片C1可以是逻辑芯片，第二半导体芯片C2可以是存储器芯片。
在其它实施方式中，第二半导体晶片可以是包括通过与形成第一半导体晶片W1的工艺相同的工艺形成的相同种类的单独器件的半导体晶片。第二半导体芯片C2可以是包括与第一半导体芯片C1中包括的单独器件相同的单独器件的相同种类的半导体芯片。例如，第一半导体晶片W1可以包括包含DRAM芯片的第一半导体芯片C1，第二半导体芯片C2可以包括DRAM。
第二半导体芯片C2可以提供为多个。所述多个第二半导体芯片C2可以以第二半导体晶片W2(其中所述多个第二半导体芯片C2彼此连接)的形式附接在第二载体基板20上，然后，第二半导体晶片可以被切割成所述多个第二半导体芯片C2。所述多个第二半导体芯片C2可以每个包括第二半导体基板210、第二半导体器件层220和第二TSV 230。第二半导体基板210可以包括彼此相反的第一表面212和第二表面214。第二TSV 230可以穿过第二半导体基板210。
所述多个第二半导体芯片C2可以每个包括第二连接焊盘232、第二连接凸块234、第二后保护层236和第二上连接焊盘238。对第二连接焊盘232、第二连接凸块234、第二后保护层236和第二上连接焊盘238的详细描述与以上参照图2描述的第一连接焊盘132、第一连接凸块134、第一后保护层136和第一上连接焊盘138类似。
参照图6，所述多个第二半导体芯片C2可以与图5所示的第二载体基板20分离，并可以堆叠在图6所示的第一半导体晶片W1上。所述多个第二半导体芯片C2可以在第一半导体晶片W1上堆叠为分别对应于第一半导体晶片W1中包括的所述多个第一半导体芯片C1。例如，所述多个第二半导体芯片C2可以在所述多个第一半导体芯片C1上堆叠为分别对应于第一半导体芯片C1。
在示范性实施方式中，每个第二半导体芯片C2可以附接在对应的第一半导体芯片C1上，其中第一绝缘材料层142在其间。例如，在所述多个第二半导体芯片C2以第二半导体晶片W2(其中所述多个第二半导体芯片C2彼此连接)的形式附接在第二载体基板20上之前，第一绝缘材料层142可以设置在第二半导体晶片W2和第二载体基板20之间。随后，第二半导体晶片W2可以被切割成所述多个第二半导体芯片C2，第一绝缘材料层142可以以附接在每个第二半导体芯片C2上的状态位于第一半导体芯片C1上。
每个第二半导体芯片C2可以堆叠在对应的第一半导体芯片C1上以使第一TSV 130电连接到第二TSV 230。为了使第一TSV 130电连接到第二TSV 230，每个第二半导体芯片C2可以堆叠在对应的第一半导体芯片C1上以使对应的第二半导体芯片C2的第二连接凸块234接触第一上连接焊盘138。如果没有形成第一上连接焊盘138，则第二连接凸块234可以接触第一TSV 130。
在第二半导体芯片C2分别堆叠在第一半导体芯片C1上之后，第二连接凸块234与第一上连接焊盘138之间或第二连接凸块234与第一TSV 130之间的粘附力可以通过执行回流工艺或热压缩工艺而增大，从而降低接触电阻。
如图6中示范性地示出的，第一绝缘材料层142可以设置在第一半导体芯片C1和第二半导体芯片C2之间以围绕第一上连接焊盘138和第二连接凸块234，并围绕多个第一上连接焊盘138和第二连接凸块234。例如，第一绝缘材料层142可以围绕并覆盖设置在第一半导体芯片C1和第二半导体芯片C2之间并将第一半导体芯片C1连接到第二半导体芯片C2的所有的第一上连接焊盘138和第二连接凸块234。在示范性实施方式中，第一绝缘材料层142可以是绝缘聚合物。例如，第一绝缘材料层142可以通过附接非导电膜(NCF)来形成。第一绝缘材料层142可以是密封第一半导体芯片C1和第二半导体芯片C2之间的连接部分并填充第一半导体芯片C1和第二半导体芯片C2之间的空间的底填充构件。
这里，术语“底填充构件”可以不必表示通过特定的制造方法形成或由特定材料形成的元件，而是可以表示填充半导体芯片之间的空间、半导体芯片和插入机构(interposer)之间的空间、或插入机构与印刷电路板(PCB)之间的空间的材料层。例如，应当理解，底填充构件表示这里描述的绝缘材料层、或下面将描述的底填充层或底填充材料层。
参照图7，通过重复以上参照图5和图6描述的工艺，多个第三半导体芯片C3可以以第二绝缘材料层144在其间在所述多个第二半导体芯片C2上的方式堆叠在第一半导体晶片W1上，以分别对应于所述多个第二半导体芯片C2。随后，通过执行回流工艺或热压缩工艺，每个第三半导体芯片C3可以电连接到对应的第二半导体芯片C2。类似地，多个第四半导体芯片C4可以以第三绝缘材料层146在其间在所述多个第三半导体芯片C3上的方式堆叠在第一半导体晶片W1上，以分别对应于所述多个第三半导体芯片C3。随后，通过执行回流工艺或热压缩工艺，每个第四半导体芯片C4可以电连接到对应的第三半导体芯片C3。此外，多个第五半导体芯片C5可以以第四绝缘材料层148在其间在所述多个第四半导体芯片C4上的方式堆叠在第一半导体晶片W1上，以分别对应于所述多个第四半导体芯片C4。随后，通过执行回流工艺或热压缩工艺，每个第五半导体芯片C5可以电连接到对应的第四半导体芯片C4。
第二至第五半导体芯片C2至C5可以是每个包括相同的单独器件的相同种类的半导体芯片。或者，第二至第五半导体芯片C2至C5可以是包括不同的单独器件的不同种类的半导体芯片。尽管在图7中示范性地示出其中第二至第五半导体芯片C2至C5垂直堆叠在第一半导体晶片W1上的五个半导体芯片堆叠结构，但是堆叠在第一半导体晶片W1上的半导体芯片的数量可以改变。
此外，在第一半导体芯片C1和第二半导体芯片C2之间形成第一绝缘材料层142时，第一底填充层例如可以通过毛细底填充工艺由环氧树脂形成。第一底填充层可以与填充物混合，填充物可以包括例如硅石。类似地，可以形成第二至第四底填充层，而不是第二至第四绝缘材料层144、146和148。
参照图8，覆盖第二至第五半导体芯片C2至C5的第一模制层160可以形成在第一半导体晶片W1上。也被描述为包封层的第一模制层160可以围绕第二至第五半导体芯片C2至C5的侧部(例如侧表面)。第一模制层160可以接触第一半导体芯片C1的顶部的一部分。由于第一至第四绝缘材料层142、144、146和148设置在第一至第五半导体芯片C1至C5之间，所以第一模制层160可以围绕第一至第四绝缘材料层142、144、146和148的侧部(例如侧表面)。在示范性实施方式中，第一模制层160可以包括环氧塑封料(EMC)。
如图8中示范性地示出的，在一个实施方式中，第一模制层160不覆盖第五半导体芯片C5的顶部。因此，包括在第五半导体芯片C5中的后保护层536和第五上连接焊盘538可以暴露到第一模制层160的外部。
参照图9，用于评估第一至第五半导体芯片C1至C5中的每个的正常操作或缺陷的电特性测试可以通过使用由第一模制层160暴露的第五半导体芯片C5的第五上连接焊盘538来进行。电特性测试可以是用于测试芯片堆叠的许多已知测试程序之一。
如图9中示范性示出的，第五半导体芯片C5可以包括第五TSV 530，第五上连接焊盘538可以提供在第五半导体芯片C5的第二表面514上。因此，电特性测试可以在第一至第五半导体芯片C1至C5堆叠在第一载体基板10上的状态(即，第一至第五半导体芯片C1至C5没有与第一载体基板10分离的状态)下容易地进行。
通常，由于设置在芯片堆叠的最上部分上的半导体芯片(例如，堆叠中的顶部芯片)不包括TSV(和/或上连接焊盘)，所以为了进行电特性测试，需要半导体芯片的堆叠结构与载体基板分离，并且半导体芯片的堆叠结构被垂直翻转，使得设置在最下部分中的半导体芯片(例如，堆叠中的底部芯片)的堆叠结构面朝上。然而，根据所公开的实施方式，由于第五半导体芯片C5包括第五TSV 530和第五上连接焊盘538，所以为了进行电特性测试，不需要第一至第五半导体芯片C1至C5的堆叠结构与第一载体基板10分离或者垂直地翻转。因此，可以容易地对第一至第五半导体芯片C1至C5进行电特性测试。
参照图10，通过沿着第一划片槽SL1(见图2)切割第一半导体晶片W1(见图9)，第一半导体晶片W1可以被切割成包括彼此对应的第一至第五半导体芯片C1至C5的多个子封装单元M1。每个子封装单元M1(或M2)也可以在这里被描述为部分封装芯片叠层。
子封装单元M1可以具有其中包括第二TSV 230的第二半导体芯片C2、包括第三TSV330的第三半导体芯片C3、包括第四TSV 430的第四半导体芯片C4和包括第五TSV 530的第五半导体芯片C5顺序地堆叠在包括第一TSV 130的第一半导体芯片C1上的结构。第一至第五半导体芯片C1至C5可以是用模制层部分地覆盖的芯片堆叠。例如，芯片堆叠可以包括覆盖第一半导体芯片C1的顶表面的边缘部分并覆盖其余的半导体芯片C2-C5的侧表面的模制层。
在示范性实施方式中，第一至第五半导体芯片C1至C5可以是相同种类的半导体芯片。例如，第一至第五半导体芯片C1至C5可以每个是存储器芯片。在其它实施方式中，第一半导体芯片C1可以不同于第二至第五半导体芯片C2至C5。例如，第一半导体芯片C1可以是逻辑芯片，第二至第五半导体芯片C2至C5可以均是存储器芯片。在其它实施方式中，第一半导体芯片C1可以是缓冲器芯片，第二至第五半导体芯片C2至C5可以均是存储器芯片。然而，本发明构思的技术精神不限于此。根据这里描述的各种实施方式，子封装单元M1(和M2)中的每个半导体芯片C1至C5包括集成电路。例如，集成电路可以形成在由晶片形成的半导体管芯(die)上。
在示范性实施方式中，第二至第五半导体芯片C2至C5可以基本上具有相同的水平横截面面积，并且第一半导体芯片C1的水平横截面面积可以大于第二至第五半导体芯片C2至C5的水平横截面面积。
第一绝缘材料层142可以设置在第一半导体芯片C1和第二半导体芯片C2之间，第二绝缘材料层144可以设置在第二半导体芯片C2和第三半导体芯片C3之间。此外，第三绝缘材料层146可以设置在第三半导体芯片C3和第四半导体芯片C4之间，第四绝缘材料层148可以设置在第四半导体芯片C4和第五半导体芯片C5之间。
第一模制层160可以形成在第一半导体芯片C1的一部分上以围绕第二至第五半导体芯片C2至C5的侧部。第一半导体芯片C1可以具有比第二至第五半导体芯片C2至C5的水平横截面面积大的水平横截面面积，因此，第一半导体芯片C1的侧部可以不被第一模制层160围绕。第一模制层160的侧部可以与第一半导体芯片C1的侧部对准。例如，第一模制层160的侧表面和第一半导体芯片C1的侧表面可以共平面。第一模制层160可以接触第一至第四绝缘材料层142、144、146和148。
第二至第四半导体芯片C2至C4可以通过第二至第四TSV 230、330和430电连接到第一半导体芯片C1和第五半导体芯片C5。由于第二至第四半导体芯片C2至C4的侧部被第一模制层160围绕，所以第二至第四半导体芯片C2至C4可以不暴露到子封装单元M1的外部，并且第一半导体芯片C1的第一连接凸块134和第五半导体芯片C5的第五上连接焊盘538可以暴露到子封装单元M1的外部。在其它实施方式中，可以不提供第五上连接焊盘538，在这种情况下，第五TSV 530可以暴露到子封装单元M1的外部。
第一半导体芯片C1可以不包括再分布布线层。因此，第一TSV 130的节距(或相邻的第一TSV 130之间的间隔)可以与第一连接凸块134的节距(或相邻的第一连接凸块134之间的间隔)基本上相同。此外，第一TSV 130可以沿着垂直于第一半导体芯片C1的顶部的方向与第一连接凸块134对准，并可以沿着垂直于第一半导体芯片C1的顶部的方向与第二至第五TSV 230、330、430和530对准。这里，第一TSV 130沿着垂直方向与第一连接凸块134对准可以表示，当从子封装单元M1的最上表面观看时(例如，当在俯视图中观看时)，第一TSV130与第一连接凸块134交叠。由于第一TSV 130沿着垂直方向与第二至第五TSV 230、330、430和530对准，所以第一连接凸块134和第五上连接焊盘538可以沿着垂直方向彼此对准。因此，子封装单元M1可以垂直地堆叠在另一子封装单元M1上(例如，在其间不使用再分布层、封装基板或插入机构基板)。
在上文，已经示范性地描述了子封装单元M1包括垂直堆叠的第一至第五半导体芯片C1至C5的示例，但是本发明构思的技术精神不限于此。例如，子封装单元M1中的堆叠的半导体芯片的数量可以改变。例如，子封装单元M1可以包括两个至四个半导体芯片，或者可以包括六个或更多个半导体芯片。
参照图11，插入机构(interposer)610可以被可选地制备和提供。
插入机构610可以包括基板基底612、提供在基板基底612的顶部上的顶焊盘614和提供在基板基底612的底部上的底焊盘616。在示范性实施方式中，基板基底612可以包括半导体材料，例如可以由硅晶片形成。内布线(未示出)可以形成在基板基底612的顶部、底部或内部上。此外，将顶焊盘614电连接到底焊盘616的TSV(未示出)和再分布布线层(未示出)可以形成在基板基底612中。
例如，插入机构610可以附接在载体基板(未示出)上，子封装单元M1可以设置在插入机构610上。在这种情况下，子封装单元M1可以设置为使得子封装单元M1的第一半导体芯片C1面对插入机构610的顶焊盘614。随后，通过执行回流工艺或热压缩工艺，第一半导体芯片C1的第一连接凸块134可以附接在顶焊盘614上。
在一个实施方式中，随后，底填充层630可以形成在子封装单元M1和插入机构610之间。例如，底填充层630可以通过毛细底填充工艺由环氧树脂形成。底填充层630可以与填充物混合，填充物可以包括例如硅石。在其它实施方式中，绝缘材料层(未示出)可以通过使用绝缘聚合物或非导电膜形成，而不在子封装单元M1和插入机构610之间形成底填充层630。
在一个实施方式中，随后，子封装单元M2可以设置在子封装单元M1上。子封装单元M2可以具有与以上参照图10描述的子封装单元M1的技术特征相同的技术特征。
如图11中示范性示出的，子封装单元M2的第一半导体芯片C1可以设置在子封装单元M1的第五半导体芯片C5上，子封装单元M2的第一半导体芯片C1的第一连接凸块134可以设置在子封装单元M1的第五半导体芯片C5的第五上连接焊盘538上。
第五绝缘材料层640可以设置在子封装单元M1和子封装单元M2之间。第五绝缘材料层640可以包括绝缘聚合物或非导电膜。在一个实施方式中，第五绝缘材料层640可以具有比第一至第四绝缘材料层142、144、146和148的水平横截面面积大的水平横截面面积。因此，第五绝缘材料层640的边缘可以设置在子封装单元M1的第一模制层160和子封装单元M2的第一模制层160之间，并可以具有与子封装单元M1的第一模制层160的侧表面和子封装单元M2的第一模制层160的侧表面共平面的侧表面。
随后，通过执行回流工艺或热压缩工艺，子封装单元M2的第一半导体芯片C1的第一连接凸块134可以附接在子封装单元M1的第五半导体芯片C5的第五上连接焊盘538上，第五绝缘材料层640可以设置在子封装单元M2的第一半导体芯片C1和子封装单元M1的第五半导体芯片C5之间，以围绕第一连接凸块134和第五上连接焊盘538。以这种方式，图11示出在第一子封装单元和第二子封装单元的每个已经形成之后，通过用焊料凸块(例如凸块134)将第一子封装单元的顶连接端子(例如焊盘538或者在其它实施方式中为突出的TSV)连接到第二子封装单元的底连接端子(例如焊盘132或在其它实施方式中为突出的TSV)而将第一子封装单元或部分封装芯片叠层(例如M1)附接到第二子封装单元或部分封装芯片叠层(例如M2)的方法，其中该焊料凸块(例如凸块134)直接连接到顶端子和底端子中的每个的各自的端子。以这种方式，一个子封装单元(例如M2)可以使用焊料凸块直接连接到另一个子封装单元(例如M1)。
在图11中，示范性地示出子封装单元M1和M2堆叠的示例。或者，其它的子封装单元M1和M2可以进一步堆叠在子封装单元M2上。例如，可以基于存储器芯片的期望容量来改变可以堆叠的子封装单元M1和M2的数量。
堆叠在插入机构610上的子封装单元M1和M2的每个可以是其正常操作已经在以上参照图9描述的电特性测试中被验证的子封装单元(例如，已知的良好封装(KGP)单元)。例如，在形成完全连接的芯片堆叠以封装之前，可以在形成子封装单元M1和M2的工艺中筛除在电连接方面有缺陷的半导体芯片，仅正常操作的子封装单元M1和M2可以堆叠在插入机构610上。
参照图12，绝缘构件650可以附接在子封装单元M2上。绝缘构件650可以覆盖暴露于子封装单元M2的外部的第五上连接焊盘538(当没有提供第五上连接焊盘538时，可以覆盖第五TSV 530)。绝缘构件650可以是例如绝缘材料的层。
参照图13，围绕子封装单元M1和M2的侧部的第二模制层660可以形成在插入机构610上。第二模制层660可以围绕第一模制层160的侧部和第一半导体芯片C1的侧部，并可以设置在插入机构610的顶部的一部分中。设置在子封装单元M1和M2之间的第五绝缘材料层640也可以接触第二模制层660。在一个实施方式中，第二模制层660具有与插入机构610的各自的侧表面共平面的外侧表面。然而，实施方式不必限于该配置。
如图13中示范性示出的，第二模制层660和第一模制层160之间的界面可以与第二模制层660和第五绝缘材料层640之间的界面对准。例如，第二模制层660可以包括在第一模制层160和第五绝缘材料层640之间的边界附近基本上是平的且连续的侧表面。第二模制层660的内侧表面可以是平的。
插入机构连接端子670可以附接在插入机构610的底部上。插入机构连接端子670可以附接在例如底焊盘616上。插入机构连接端子670可以是例如焊球或凸块。
在示范性实施方式中，插入机构连接端子670可以在插入机构610的底部包括设置在底焊盘616上的下凸块金属(UBM)(未示出)和设置在UBM上的焊球(未示出)。插入机构连接端子670还可以包括设置在UBM和焊球之间的外部连接柱(未示出)，外部连接柱可以包括例如铜。
随后，可以提供PCB 710。
PCB 710可以包括基板基底720、提供在基板基底720的顶部上的顶焊盘(未示出)和提供在基板基底720的底部上的底焊盘(未示出)。顶焊盘和底焊盘可以通过覆盖基板基底720的顶部和底部的阻焊层(未示出)暴露。基板基底720可以由酚醛树脂、环氧树脂和聚酰亚胺中的至少一种形成。例如，基板基底720可以包括从FR4、四官能环氧树脂、聚苯醚、环氧树脂/聚苯醚氧化物、双马来酰亚胺三嗪(BT)、、氰酸酯、聚酰亚胺和液晶聚合物当中选择的至少一种材料。顶焊盘和底焊盘可以均由Cu、Ni、不锈钢、铍铜和/或类似物形成。电连接到顶焊盘和底焊盘的内部布线(未示出)可以提供在基板基底720中。顶焊盘和底焊盘可以是电路布线的通过阻焊层暴露的部分，电路布线通过图案化涂覆在基板基底720的顶部和底部上的Cu箔而形成。
插入机构610可以设置在PCB 710上，使得插入机构连接端子670位于PCB 710的顶焊盘上，并且底填充层730可以形成在插入机构610和PCB 710之间。外连接端子740可以附接在PCB 710的底焊盘上。例如，外连接端子740可以是焊球或凸块。
尽管与图11至图13相关的各种各样的步骤在以上以特定的顺序被描述并在一个实施方式中以该顺序发生，但是不同部件结合的顺序不需要遵循该顺序。不管该顺序如何，在上文和下文论述的完成的封装的不同元件可以提供为半导体器件的形式，诸如半导体封装，其可以是例如存储器件、逻辑器件或结合的存储器件和逻辑器件。
在一个实施方式中，作为上述步骤的结果，第一子封装单元M1的外侧表面可以与堆叠在其上的第二子封装单元M2的外侧表面共平面。然而，完整的封装单元M1+M2的外侧表面可以不与插入机构610的外侧表面垂直地对准。插入机构610可以是封装基板(例如，其上堆叠半导体芯片)。插入机构610可以是再分布基板。PCB 710也可以是封装基板，并可以被描述为再分布基板。例如，插入机构610和/或PCB 710可以具有用于在封装的外部与完整封装单元M1+M2中的各种各样的芯片C1-C5之间传输信号的主要功能和主要元件。例如，在一些实施方式中，插入机构610和PCB 710都不包括执行逻辑操作或存储操作的集成电路。另一方面，半导体芯片C1至C5中的每个可以包括集成电路，并可以具有执行逻辑操作或存储数据的主要目的。
此外，在上面的描述中，已经示范性地描述了其中插入机构610安装在PCB 710上并且子封装单元M1和M2安装在插入机构610上的结构，但是本发明构思的技术精神不限于此。在其它实施方式中，不同数量的子封装单元M1和M2可以堆叠在封装基板上。这里，术语“封装基板”可以表示根据本发明构思的子封装单元M1和M2能够被堆叠在其上的任意基板，因此，应当理解，封装基板包括各种基板，诸如插入机构610、PCB 710、其组合、陶瓷基板、半导体基板等。与图13所示的不同，子封装单元M1和M2可以安装在插入机构610上，PCB 710可以被省略。或者，子封装单元M1和M2可以直接安装在PCB 710上，插入机构610可以被省略。
半导体封装100可以通过上述工艺完全地形成。
根据制造半导体封装100的方法，包括第一至第五半导体芯片C1至C5的子封装单元M1和M2可以被首先制造，并可以被测试以确保它们没有缺陷。然后，通过根据半导体封装的期望容量堆叠多个子封装单元M1和M2，半导体封装100可以被完全地形成。
通常，在垂直堆叠每个包括TSV的多个半导体芯片的情况下，半导体芯片一个接一个地顺序地堆叠在封装基板上。然而，随着堆叠的半导体芯片的数量增加和/或半导体芯片的TSV的尺寸和节距减小，在堆叠半导体芯片的工艺中容易发生接合缺陷(或互连缺陷)，为此，难以在半导体芯片之间提供高可靠性的电连接。例如，在将半导体芯片一个接一个地堆叠在封装基板上的情况下，通常需要进行与堆叠的半导体芯片的数量相同的多个次数的用于TSV和连接凸块之间的电连接的高温回流工艺或热压缩工艺。因此，由于重复的高温工艺，热/物理损坏被施加到连接凸块和TSV之间的连接部分。此外，在将半导体芯片一个接一个地堆叠在封装基板上的情况下，在制造其中期望数量的半导体芯片全部被堆叠的封装之后，测试封装的缺陷。例如，当封装被确定为其中电连接是有缺陷的封装(例如，即使可能只有一个有缺陷的半导体芯片)时，整个封装会被丢弃，使得包括在该封装中的所有半导体芯片都不能被使用。为此，在半导体封装工艺中半导体芯片的损失增加(或者半导体芯片的产率降低)。
然而，根据制造半导体封装件100的上述方法，可以首先制造在其中一定数量的半导体芯片C1至C5被堆叠的子封装单元M1和M2，然后所述多个子封装单元M1和M2可以堆叠在封装基板上，从而获得半导体封装100，其中半导体芯片C1至C5通过TSV 130、230、330、430和530彼此连接。因此，包括在子封装单元M1和M2中的半导体芯片C1至C5被暴露到执行较少次数的高温工艺，从而防止由于高温工艺施加到连接凸块或施加到连接凸块和TSV之间的连接部分的热/物理损坏。因此，半导体封装100具有高可靠性。
此外，在子封装单元M1和M2堆叠在封装基板上之前，可以测试子封装单元M1和M2的每个的缺陷。因此，由于在制造子封装单元M1和M2的工艺中预先筛除了在电连接方面有缺陷的半导体芯片，所以减小了半导体封装100的缺陷率。两个子封装单元M1和M2可以例如共用相同的封装基板，使得顶部子封装单元或部分封装芯片叠层M2堆叠在底部子封装单元或部分封装芯片叠层M1上，而没有任何封装基板在其间。因而，所述两个子封装单元M1和M2可以以上述方式中的一种或多种结合从而形成单个封装(例如，半导体封装100可以被认为是具有单个封装基板的单个封装，而不是包括多个封装基板的层叠封装装置)。
图14至图18是示出根据示范性实施方式的制造半导体封装100A的方法的剖视图。在图14至图18中，图1至图13中示出的相同的附图标记指代相同的元件。
首先，通过执行参照图1至图4在以上描述的工艺，可以制备其中第一半导体芯片C1A彼此连接的第一半导体晶片W1(见图4)。
参照图14，第一半导体芯片C1A可以通过切割第一半导体晶片W1来制备。例如，第一半导体晶片W1可以在附接在第一载体基板10上的状态下被切割成第一半导体芯片C1A(例如多个第一半导体芯片C1A)。
参照图15，在彼此分离的第一半导体晶片W1附接在第一载体基板10上的状态下，第二半导体芯片C2可以设置在第一半导体芯片C1A上。关于第二半导体芯片C2的详细描述类似于参照图5进行的描述。
第一半导体芯片C1A和第二半导体芯片C2可以是包括相同种类的单独器件的相同种类的半导体芯片。例如，第一半导体芯片C1A和第二半导体芯片C2可以均是存储器芯片。此外，第一半导体芯片C1A和第二半导体芯片C2可以基本上具有相同的水平横截面面积。然而，本发明构思的技术精神不限于此，第二半导体芯片C2可以是包括与第一半导体芯片C1A的单独器件不同的单独器件的不同种类的半导体芯片。
通过与以上参照图5至图7描述的工艺类似的工艺，第三半导体芯片C3可以堆叠在第二半导体芯片C2上，第四半导体芯片C4可以堆叠在第三半导体芯片C3上。
参照图16，覆盖第一至第四半导体芯片C1A和C2至C4的侧部的第一模制层160可以形成在载体基板10上。第一模制层160可以围绕设置在第一至第四半导体芯片C1A和C2至C4之间的第一至第三绝缘材料层142、144和146的侧部。此外，第一模制层160可以不覆盖第四半导体芯片C4的第二表面(或第四半导体芯片C4的顶部)。
随后，用于评估第一至第四半导体芯片C1A和C2至C4中的每个的缺陷的电特性测试可以通过第四半导体芯片C4的没有被第一模制层160覆盖的第四上连接焊盘438进行。
参照图17，通过第一模制层160彼此连接的第一至第四半导体芯片C1A和C2至C4的堆叠结构可以沿着第二划片槽SL2(见图16)切割，因此，堆叠结构可以被切割成包括彼此对应的第一至第四半导体芯片C1A和C2至C4的子封装单元M1A。此外，可以移除载体基板10。
子封装单元M1A可以包括具有相同水平横截面面积的第一至第四半导体芯片C1A和C2至C4。第一模制层160可以围绕第一至第四半导体芯片C1A和C2至C4的侧部。第一半导体芯片C1的第一连接凸块134可以暴露到子封装单元M1A的外部而没有被第一模制层160覆盖，并且不被任何模制层直接覆盖。如果省略第四半导体芯片C4的第四上连接焊盘438，则第四TSV 430可以暴露到子封装单元M1A的外部而没有被第一模制层160覆盖，并且不被任何模制层直接覆盖。
随后，图18中示出的半导体封装100A可以通过以上参照图11至图13描述的工艺完整地形成。
半导体封装100A可以包括垂直堆叠的子封装单元M1A和M2A、设置在子封装单元M1A和M2A之间的第五绝缘材料层640、以及围绕子封装单元M1A和M2A以及第五绝缘材料层640的侧部的第二模制层660。第五绝缘材料层640的一部分(例如，第五绝缘材料层640的边缘)可以设置在子封装单元M1A的第一模制层160和子封装单元M2A的第一模制层160之间。第五绝缘材料层640可以具有比第一至第三绝缘材料层142、144和146的水平横截面面积大的水平横截面面积。
由于第一至第四半导体芯片C1A和C2至C4具有基本上相同的水平横截面面积并且第一至第四半导体芯片C1A和C2至C4的侧部被第一模制层160围绕，所以第一至第四半导体芯片C1A和C2至C4可以不接触第二模制层640。
根据制造半导体封装100A的上述方法，包括在子封装单元M1A和M2A中的第一至第四半导体芯片C1A和C2至C4可以暴露于执行较少次数的高温工艺，因此减少或防止了由于高温工艺而施加到连接凸块或连接凸块和TSV之间的连接部分的热/物理损坏。因此，半导体封装100A具有高可靠性。由于在制造子封装单元M1A和M2A的工艺中可以预先筛除在电连接方面有缺陷的半导体芯片，所以半导体封装100A的缺陷率降低。
图19是示出根据示范性实施方式的半导体封装100B的剖视图。在图19中，图1至图18中示出的相同的附图标记表示相同的元件。除了第一至第五绝缘材料层142A、144A、146A、148A和640A之外，半导体封装100B可以与以上参照图1至图13描述的半导体封装100基本上相同。
参照图19，第一至第四绝缘材料层142A、144A、146A和148A可以具有相对于第二至第五半导体芯片C2至C5凸地突出的形状。在示范性实施方式中，第一至第四绝缘材料层142A、144A、146A和148A可以通过附接NCF形成。例如，在制造子封装单元M1和M2的过程中，在第二半导体芯片C2正被附接以连接到第一半导体芯片C1的第一TSV 130的同时，施加压力，因此第一绝缘材料层142A可以具有凸地突出的形状。
第五绝缘材料层640A可以具有相对于第一半导体芯片C1的侧部或第一模制层160的侧部凸地突出的形状。第五绝缘材料层640A可以通过附接NCF形成。例如，第五绝缘材料层640A可以附接在子封装单元M1上，以使子封装单元M2的第一TSV 130电连接到子封装单元M1的第五TSV 530，并且子封装单元M2可以附接在第五绝缘材料层640A上(或者第五绝缘材料层640A可以首先附接在子封装单元M2的底部上，然后子封装单元M2可以附接在子封装单元M1上，以使第五绝缘材料层640A接触子封装单元M1)。在这种情况下，在附接工艺中，压力可以被施加到第五绝缘材料层640A，因此，第五绝缘材料层640A可以具有相对于第一半导体芯片C1的侧部或第一模制层的侧部凸地突出的形状。
在图19中，示范性地示出第五绝缘材料层640A具有凸地突出的形状的示例，但是第五绝缘材料层640A可以通过毛细底填充工艺由环氧树脂形成，而不是通过附接NCF形成。在这种情况下，第五绝缘材料层640A可以具有在向下方向上膨胀的形状，以使其下部宽度比其上部宽度宽。
图20是示出根据示范性实施方式的半导体封装100C的剖视图。在图20中，图1至图19中示出的相同附图标记指代相同的元件。除了形成第五绝缘材料层640和底填充材料层630的工艺之外，半导体封装100C可以与以上参照图1至图13描述的半导体封装100基本上相同。
参照图20，子封装单元M1可以附接在插入机构610上，子封装单元M2可以附接在子封装单元M1上。随后，底填充材料层630A可以在形成第二模制层660的工艺中形成在插入机构610和子封装单元M1之间的空间中，并且底填充材料层640B可以形成在子封装单元M1和子封装单元M2之间的空间中。在示范性实施方式中，底填充材料层630A和640B可以是第二模制层660的通过模制底填充(MUF)工艺形成的部分。
图21是示出根据示范性实施方式的半导体封装100D的剖视图。在图21中，图1至图20中示出的相同附图标记表示相同的元件。
参照图21，子封装单元M1和M2可以堆叠在插入机构610的一部分上，并且主半导体芯片800可以设置在插入机构610的另一部分上。
主半导体芯片800可以是例如处理器单元。主半导体芯片800可以是例如微处理器单元(MPU)或图形处理器单元(GPU)。在一些实施方式中，主半导体芯片800可以是其正常操作已经被验证的封装(例如KGP)。
主连接端子810可以附接在主半导体芯片800的底部上。主半导体芯片800可以通过主连接端子810电连接到插入机构610。围绕主连接端子810的底填充材料层820可以进一步形成在主半导体芯片800和插入机构610之间。底填充材料层820可以包括例如环氧树脂。在一些实施方式中，底填充材料层820可以是通过MUF工艺形成的第二模制层660的一部分。
在图21中，公开了两个子封装单元M1和M2堆叠在插入机构610的一部分上的结构，但是垂直堆叠的子封装单元M1和M2的数量不限于此。例如，三个或四个子封装单元M1和M2可以垂直地堆叠。此外，垂直堆叠的子封装单元M1和M2的堆叠结构可以另外地设置在插入机构610的另一部分上。例如，与图21中示范性示出的不同，主半导体芯片800可以设置在插入机构610的中部，并且子封装单元M1和M2堆叠的结构可以在主半导体芯片800附近提供为多个并可以彼此间隔开(例如，可以以90°的特定角度设置等)。
此外，在图21中，第二模制层660被示范性地示出为形成至主半导体芯片800的整个高度或更高以覆盖主半导体芯片800的整个顶部和侧部，但是本发明构思的技术精神不限于此。与图21中示范性示出的不同，第二模制层660可以形成为仅覆盖主半导体芯片800的侧部的一部分(例如，形成至从主半导体芯片800的底部起一定高度)，或者可以形成为既完全覆盖主半导体芯片800(如所示的)的顶部又完全覆盖包括子封装单元M1和M2的完成的封装单元的顶部。
在其它实施方式中，主半导体芯片800可以包括TSV(未示出)，并且子封装单元M1和M2的堆叠结构可以设置在主半导体芯片800上。在这种情况下，第一至第五半导体芯片C1至C5(见图10)的TSV 130、230、330、430和530可以电连接到与其对应的主半导体芯片800的TSV，并且第一至第五半导体芯片C1至C5可以通过主连接端子810电连接到插入机构610和/或PCB 710。
尽管已经参照其实施方式具体示出和描述了本发明构思的各个方面，但是将理解，可以在其中进行形式和细节上的各种改变，而没有脱离权利要求书的精神和范围。
本申请要求于2016年6月30日在韩国知识产权局提交的韩国专利申请第10-2016-0082973号的优先权的权益，其公开通过引用整体地合并于此。

Claims (22)

1.一种制造半导体封装的方法，包括：
提供第一子封装单元，所述第一子封装单元包括垂直堆叠的至少两个第一半导体芯片和围绕所述至少两个第一半导体芯片的侧表面的第一模制层；和
提供第二子封装单元，所述第二子封装单元包括垂直堆叠的至少两个第二半导体芯片以及围绕所述至少两个第二半导体芯片的侧表面并与所述第一模制层垂直地间隔开的第二模制层，所述第二子封装单元设置在所述第一子封装单元上，
其中所述至少两个第一半导体芯片和所述至少两个第二半导体芯片均包括基板通孔，并且
其中所述至少两个第一半导体芯片中的最上面的第一半导体芯片电连接到所述至少两个第二半导体芯片中的最下面的第二半导体芯片，而在其间没有封装基板；以及
提供封装基板，其中所述至少两个第一半导体芯片和所述至少两个第二半导体芯片垂直堆叠在所述封装基板上以形成半导体封装。
2.根据权利要求1所述的方法，还包括：
提供上连接焊盘，所述上连接焊盘在所述至少两个第二半导体芯片当中的设置在最上部分中的第二半导体芯片的顶表面上并且电连接到所述第二半导体芯片的所述基板通孔。
3.根据权利要求1所述的方法，还包括：
提供绝缘构件，所述绝缘构件提供在所述至少两个第二半导体芯片当中的设置在最上部分中的第二半导体芯片的顶表面上。
4.根据权利要求1所述的方法，还包括：
在所述第一子封装单元的所述至少两个第一半导体芯片之间提供第一底填充构件，以及
在所述第二子封装单元的所述至少两个第二半导体芯片之间提供第二底填充构件。
5.根据权利要求4所述的方法，还包括：
在所述第一子封装单元和所述第二子封装单元之间提供第三底填充构件，所述第三底填充构件接触所述第一模制层的顶表面和/或所述第二模制层的底表面。
6.根据权利要求5所述的方法，其中所述第三底填充构件的一部分设置在所述第一模制层和所述第二模制层之间。
7.根据权利要求5所述的方法，其中所述第三底填充构件具有比所述第一底填充构件或所述第二底填充构件的水平横截面面积大的水平横截面面积。
8.根据权利要求1所述的方法，其中所述至少两个第一半导体芯片具有相同的水平横截面面积，和/或所述至少两个第二半导体芯片具有相同的水平横截面面积。
9.根据权利要求1所述的方法，还包括：
在所述第一子封装单元中提供设置在所述至少两个第一半导体芯片下面的第三半导体芯片，
其中所述第三半导体芯片具有比所述至少两个第一半导体芯片中的每个的水平横截面面积大的水平横截面面积，并且所述第一模制层设置在所述第三半导体芯片的顶表面的一部分上；以及
在所述第二子封装单元中提供设置在所述至少两个第二半导体芯片下面的第四半导体芯片，
其中所述第四半导体芯片具有比所述至少两个第二半导体芯片中的每个的水平横截面面积大的水平横截面面积，并且所述第二模制层设置在所述第四半导体芯片的顶表面的一部分上。
10.根据权利要求1所述的方法，还包括：
提供围绕所述第一子封装单元的侧表面和所述第二子封装单元的侧表面的第三模制层，
其中所述第三模制层包围所述第一模制层的侧表面和所述第二模制层的侧表面。
11.根据权利要求10所述的方法，还包括：
在所述第一子封装单元和所述第二子封装单元之间提供第一底填充构件，
其中所述第三模制层围绕所述第一底填充构件的侧表面。
12.根据权利要求1所述的方法，还包括：
在所述第一子封装单元上设置所述第二子封装单元之前，测试所述第一子封装单元和所述第二子封装单元的每个。
13.根据权利要求1所述的方法，还包括：
在所述第一子封装单元和所述第二子封装单元的每个已经形成之后，通过用焊料凸块将所述第一子封装单元的顶连接端子连接到所述第二子封装单元的底连接端子，将所述第一子封装单元附接到所述第二子封装单元，其中该焊料凸块直接连接到所述顶连接端子和所述底连接端子的每个的各自的端子。
14.一种制造半导体封装的方法，所述方法包括：
提供封装基板；
通过首先在所述封装基板上堆叠第一子封装单元以及随后在所述第一子封装单元上堆叠第二子封装单元，沿着垂直于所述封装基板的顶表面的方向在所述封装基板上堆叠多个子封装单元，
其中所述多个子封装单元的每个包括：
第一缓冲器芯片或逻辑芯片；
第一存储器芯片，设置在所述第一缓冲器芯片或逻辑芯片上；
第二存储器芯片，设置在所述第一存储器芯片上；和
对于每个子封装单元，围绕所述第一存储器芯片和所述第二存储器芯片中的每个的侧表面的第一模制层，其中所述第一缓冲器芯片或逻辑芯片、所述第一存储器芯片和所述第二存储器芯片中的每个包括基板通孔；以及
执行回流工艺以将所述第一子封装单元直接电连接到所述第二子封装单元。
15.根据权利要求14所述的方法，其中对于所述多个子封装单元的每个，所述第一模制层接触所述第一缓冲器芯片或逻辑芯片的顶表面，而没有设置在所述第一缓冲器芯片或逻辑芯片的侧表面上。
16.根据权利要求14所述的方法，还包括：
形成围绕所述多个子封装单元的侧表面并接触每个第一缓冲器芯片或逻辑芯片的所述侧表面的第二模制层。
17.根据权利要求14所述的方法，还包括：
在所述多个子封装单元当中的设置在最上部分中的子封装单元的顶表面上形成绝缘构件；以及
在所述多个子封装单元当中的设置在最上部分中的所述子封装单元的所述第二存储器芯片上形成上连接焊盘，该上连接焊盘电连接到所述第二存储器芯片的所述基板通孔，
其中所述绝缘构件覆盖所述上连接焊盘。
18.根据权利要求14所述的方法，其中，对于所述多个子封装单元的每个：
所述第一缓冲器芯片或逻辑芯片不包括再分布布线层，
所述第一缓冲器芯片或逻辑芯片的所述基板通孔与所述第一存储器芯片的所述基板通孔对准，以及
所述第一存储器芯片的所述基板通孔与所述第二存储器芯片的所述基板通孔对准。
19.一种制造半导体封装的方法，所述方法包括：
形成至少两个部分封装芯片叠层，每个部分封装芯片叠层包括每个包含多个基板通孔的至少两个半导体芯片，并包括围绕所述至少两个半导体芯片的侧表面的第一模制层；和
在垂直于所述封装基板的顶表面的方向上在封装基板上顺序地安装所述至少两个部分封装芯片叠层，使得所述至少两个部分封装芯片叠层包括第一部分封装芯片叠层和直接连接到所述第一部分封装芯片叠层的第二部分封装芯片叠层。
20.根据权利要求19所述的方法，其中
形成所述至少两个部分封装芯片叠层包括：对于每个部分封装芯片叠层，将所述至少两个半导体芯片中的一个堆叠在所述至少两个半导体芯片中的另一个上，使第一底填充构件在其间，
安装所述至少两个部分封装芯片叠层包括：将所述至少两个部分封装芯片叠层中的一个堆叠在所述至少两个部分封装芯片叠层中的另一个上，使第二底填充构件在其间，并且
所述第二底填充构件的水平横截面面积大于所述第一底填充构件的水平横截面面积。
21.根据权利要求20所述的方法，其中所述第二底填充构件的一部分设置在所述至少两个部分封装芯片叠层的所述第一模制层之间。
22.根据权利要求19所述的方法，还包括，在安装所述至少两个部分封装芯片叠层之前，测试所述至少两个部分封装芯片叠层的每个的缺陷。
CN201710513118.8A 2016-06-30 2017-06-29 制造半导体封装的方法 Active CN107564894B (zh)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
KR1020160082973A KR102570582B1 (ko) 2016-06-30 2016-06-30 반도체 패키지 및 그 제조 방법
KR10-2016-0082973 2016-06-30

Publications (2)

Publication Number Publication Date
CN107564894A true CN107564894A (zh) 2018-01-09
CN107564894B CN107564894B (zh) 2021-06-15

Family

ID=60807795

Family Applications (1)

Application Number Title Priority Date Filing Date
CN201710513118.8A Active CN107564894B (zh) 2016-06-30 2017-06-29 制造半导体封装的方法

Country Status (4)

Country Link
US (1) US10026724B2 (zh)
KR (1) KR102570582B1 (zh)
CN (1) CN107564894B (zh)
TW (1) TWI743139B (zh)

Cited By (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN110364513A (zh) * 2018-03-26 2019-10-22 三星电子株式会社 半导体芯片和包括半导体芯片的半导体封装
CN110416153A (zh) * 2018-04-30 2019-11-05 爱思开海力士有限公司 层叠半导体晶片的方法
CN110473841A (zh) * 2018-05-10 2019-11-19 美光科技公司 用于制造半导体装置封装的方法、封装和并入有此类封装的系统
CN110675903A (zh) * 2018-07-02 2020-01-10 上海登临科技有限公司 包括绕过物理层的硅通孔（tsv）的可配置随机存取存储器（ram）阵列
CN110690192A (zh) * 2018-07-05 2020-01-14 三星电子株式会社 半导体装置
CN112385036A (zh) * 2018-07-06 2021-02-19 伊文萨思粘合技术公司 模制的直接键合和互连的堆叠
WO2023104092A1 (en) * 2021-12-08 2023-06-15 Tongfu Microelectronics Co., Ltd. Packaging method and packaging structure of multi-layer stacked memory
WO2023138120A1 (zh) * 2022-01-20 2023-07-27 长鑫存储技术有限公司 一种半导体封装结构及其形成方法

Families Citing this family (37)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US10535633B2 (en) 2015-07-02 2020-01-14 Taiwan Semiconductor Manufacturing Company, Ltd. Chip package having die structures of different heights and method of forming same
US9806058B2 (en) * 2015-07-02 2017-10-31 Taiwan Semiconductor Manufacturing Company, Ltd. Chip package having die structures of different heights and method of forming same
US9786619B2 (en) * 2015-12-31 2017-10-10 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor structure and manufacturing method thereof
KR102579876B1 (ko) * 2016-02-22 2023-09-18 삼성전자주식회사 반도체 패키지
US10204893B2 (en) 2016-05-19 2019-02-12 Invensas Bonding Technologies, Inc. Stacked dies and methods for forming bonded structures
KR102521881B1 (ko) 2016-06-15 2023-04-18 삼성전자주식회사 반도체 소자 및 이의 제조 방법
JP6649308B2 (ja) * 2017-03-22 2020-02-19 キオクシア株式会社 半導体装置およびその製造方法
US10854568B2 (en) 2017-04-07 2020-12-01 Taiwan Semiconductor Manufacturing Company, Ltd. Packages with Si-substrate-free interposer and method forming same
DE102017123449B4 (de) 2017-04-10 2023-12-28 Taiwan Semiconductor Manufacturing Co. Ltd. Gehäuse mit Si-substratfreiem Zwischenstück und Ausbildungsverfahren
US10522449B2 (en) 2017-04-10 2019-12-31 Taiwan Semiconductor Manufacturing Company, Ltd. Packages with Si-substrate-free interposer and method forming same
US10879212B2 (en) 2017-05-11 2020-12-29 Invensas Bonding Technologies, Inc. Processed stacked dies
CN109285825B (zh) * 2017-07-21 2021-02-05 联华电子股份有限公司 芯片堆叠结构及管芯堆叠结构的制造方法
JP6981800B2 (ja) * 2017-07-28 2021-12-17 浜松ホトニクス株式会社 積層型素子の製造方法
US10510718B2 (en) * 2017-08-28 2019-12-17 Taiwan Semiconductor Manufacturing Company Ltd. Semiconductor structure and manufacturing method thereof
US10290571B2 (en) 2017-09-18 2019-05-14 Taiwan Semiconductor Manufacturing Company, Ltd. Packages with si-substrate-free interposer and method forming same
US10418255B2 (en) 2017-12-01 2019-09-17 Micron Technology, Inc. Semiconductor device packages and related methods
KR102587976B1 (ko) * 2018-02-06 2023-10-12 삼성전자주식회사 반도체 패키지
US11276676B2 (en) * 2018-05-15 2022-03-15 Invensas Bonding Technologies, Inc. Stacked devices and methods of fabrication
WO2020010136A1 (en) * 2018-07-06 2020-01-09 Invensas Bonding Technologies, Inc. Molded direct bonded and interconnected stack
KR102583127B1 (ko) * 2018-10-30 2023-09-26 삼성전자주식회사 다이스택 구조물과 이를 구비하는 반도체 패키지
KR20210104742A (ko) 2019-01-14 2021-08-25 인벤사스 본딩 테크놀로지스 인코포레이티드 접합 구조체
KR20200112041A (ko) * 2019-03-20 2020-10-05 에스케이하이닉스 주식회사 적층형 반도체 장치 및 그의 테스트 방법
US20200357766A1 (en) * 2019-05-09 2020-11-12 Nanya Technology Corporation Semiconductor packages with adhesion enhancement layers
US11189599B2 (en) * 2019-05-30 2021-11-30 Taiwan Semiconductor Manufacturing Company, Ltd. System formed through package-in-package formation
DE102019128274A1 (de) * 2019-05-30 2020-12-03 Taiwan Semiconductor Manufacturing Co., Ltd. Package-in-Package-gebildetes System
US11189545B2 (en) * 2019-06-20 2021-11-30 Nanya Technology Corporation Semiconductor device and method for manufacturing the same
US11296053B2 (en) 2019-06-26 2022-04-05 Invensas Bonding Technologies, Inc. Direct bonded stack structures for increased reliability and improved yield in microelectronics
US11562983B2 (en) * 2019-06-28 2023-01-24 Taiwan Semiconductor Manufacturing Company, Ltd. Package having multiple chips integrated therein and manufacturing method thereof
KR20210035546A (ko) * 2019-09-24 2021-04-01 삼성전자주식회사 반도체 패키지
KR20220014364A (ko) * 2020-07-23 2022-02-07 삼성전자주식회사 반도체 패키지
KR20220065360A (ko) * 2020-11-13 2022-05-20 삼성전자주식회사 반도체 패키지
KR20220075030A (ko) * 2020-11-26 2022-06-07 삼성전자주식회사 반도체 패키지
KR20220101335A (ko) 2021-01-11 2022-07-19 삼성전자주식회사 복수개의 반도체 칩들을 포함하는 반도체 패키지 및 이의 제조 방법
US11769731B2 (en) * 2021-01-14 2023-09-26 Taiwan Semiconductor Manufacturing Co., Ltd Architecture for computing system package
US11574891B2 (en) 2021-01-26 2023-02-07 Nanya Technology Corporation Semiconductor device with heat dissipation unit and method for fabricating the same
US11854928B2 (en) * 2021-08-27 2023-12-26 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor package and manufacturing method thereof
KR20230032587A (ko) * 2021-08-31 2023-03-07 삼성전자주식회사 반도체 패키지

Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN103165479A (zh) * 2013-03-04 2013-06-19 江苏物联网研究发展中心 多芯片系统级封装结构的制作方法
CN103700633A (zh) * 2012-09-27 2014-04-02 三星电子株式会社 半导体封装件
CN104253056A (zh) * 2013-06-27 2014-12-31 三星电子株式会社 具有穿通电极的半导体封装及其制造方法
US20150102505A1 (en) * 2013-10-16 2015-04-16 Samsung Electronics Co., Ltd Semiconductor package and method of fabricating the same
US20150192633A1 (en) * 2014-01-07 2015-07-09 International Business Machines Corporation 3d chip testing through micro-c4 interface
CN105390464A (zh) * 2014-08-27 2016-03-09 三星电子株式会社 半导体装置和制造半导体装置的方法

Family Cites Families (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100945504B1 (ko) 2007-06-26 2010-03-09 주식회사 하이닉스반도체 스택 패키지 및 그의 제조 방법
JP2010251347A (ja) * 2009-04-10 2010-11-04 Elpida Memory Inc 半導体装置の製造方法
US7816181B1 (en) 2009-06-30 2010-10-19 Sandisk Corporation Method of under-filling semiconductor die in a die stack and semiconductor device formed thereby
KR20110004114A (ko) 2009-07-07 2011-01-13 주식회사 하이닉스반도체 자동 정렬용 지그 및 이를 이용한 반도체 패키지 제조방법
KR101054492B1 (ko) 2009-08-06 2011-09-02 한국기계연구원 적층용 단위 칩의 제조방법과, 단위 칩을 이용한 3차원 적층 칩 및 그 제조방법
US9123552B2 (en) 2010-03-30 2015-09-01 Micron Technology, Inc. Apparatuses enabling concurrent communication between an interface die and a plurality of dice stacks, interleaved conductive paths in stacked devices, and methods for forming and operating the same
KR101692955B1 (ko) * 2010-10-06 2017-01-05 삼성전자 주식회사 반도체 패키지 및 그 제조 방법
KR101215975B1 (ko) 2011-02-28 2012-12-27 에스케이하이닉스 주식회사 반도체 장치 및 이의 제조방법
KR20120123919A (ko) * 2011-05-02 2012-11-12 삼성전자주식회사 칩 적층 반도체 패키지 제조 방법 및 이에 의해 제조된 칩 적층 반도체 패키지
US8552567B2 (en) 2011-07-27 2013-10-08 Micron Technology, Inc. Semiconductor die assemblies, semiconductor devices including same, and methods of fabrication
JP5543567B2 (ja) 2012-10-22 2014-07-09 誠 雫石 半導体素子の製造方法
KR102143518B1 (ko) * 2013-10-16 2020-08-11 삼성전자 주식회사 칩 적층 반도체 패키지 및 그 제조 방법
US9404953B2 (en) 2013-10-31 2016-08-02 International Business Machines Corporation Structures and methods for monitoring dielectric reliability with through-silicon vias

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN103700633A (zh) * 2012-09-27 2014-04-02 三星电子株式会社 半导体封装件
CN103165479A (zh) * 2013-03-04 2013-06-19 江苏物联网研究发展中心 多芯片系统级封装结构的制作方法
CN104253056A (zh) * 2013-06-27 2014-12-31 三星电子株式会社 具有穿通电极的半导体封装及其制造方法
US20150102505A1 (en) * 2013-10-16 2015-04-16 Samsung Electronics Co., Ltd Semiconductor package and method of fabricating the same
US20150192633A1 (en) * 2014-01-07 2015-07-09 International Business Machines Corporation 3d chip testing through micro-c4 interface
CN105390464A (zh) * 2014-08-27 2016-03-09 三星电子株式会社 半导体装置和制造半导体装置的方法

Cited By (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN110364513A (zh) * 2018-03-26 2019-10-22 三星电子株式会社 半导体芯片和包括半导体芯片的半导体封装
CN110364513B (zh) * 2018-03-26 2023-07-04 三星电子株式会社 半导体芯片和包括半导体芯片的半导体封装
CN110416153A (zh) * 2018-04-30 2019-11-05 爱思开海力士有限公司 层叠半导体晶片的方法
CN110473841A (zh) * 2018-05-10 2019-11-19 美光科技公司 用于制造半导体装置封装的方法、封装和并入有此类封装的系统
CN112736044A (zh) * 2018-05-10 2021-04-30 美光科技公司 用于制造半导体装置封装的方法、封装和并入有此类封装的系统
CN110675903A (zh) * 2018-07-02 2020-01-10 上海登临科技有限公司 包括绕过物理层的硅通孔（tsv）的可配置随机存取存储器（ram）阵列
CN110675903B (zh) * 2018-07-02 2022-02-25 上海登临科技有限公司 包括绕过物理层的硅通孔(tsv)的可配置随机存取存储器(ram)阵列
CN110690192A (zh) * 2018-07-05 2020-01-14 三星电子株式会社 半导体装置
CN112385036A (zh) * 2018-07-06 2021-02-19 伊文萨思粘合技术公司 模制的直接键合和互连的堆叠
WO2023104092A1 (en) * 2021-12-08 2023-06-15 Tongfu Microelectronics Co., Ltd. Packaging method and packaging structure of multi-layer stacked memory
WO2023138120A1 (zh) * 2022-01-20 2023-07-27 长鑫存储技术有限公司 一种半导体封装结构及其形成方法

Also Published As

Publication number Publication date
KR20180003317A (ko) 2018-01-09
CN107564894B (zh) 2021-06-15
TWI743139B (zh) 2021-10-21
TW201820585A (zh) 2018-06-01
US10026724B2 (en) 2018-07-17
US20180006006A1 (en) 2018-01-04
KR102570582B1 (ko) 2023-08-24

Similar Documents

Publication Publication Date Title
CN107564894A (zh) 制造半导体封装的方法
US11476125B2 (en) Multi-die package with bridge layer
US8816407B2 (en) Semiconductor package
CN108074919A (zh) 堆叠式半导体封装件
TWI436469B (zh) 多晶片模組的改良電性連接
CN108091615A (zh) 半导体封装件
US11664348B2 (en) Substrate assembly semiconductor package including the same and method of manufacturing 1HE semiconductor package
KR20170075125A (ko) 반도체 패키지 및 제조 방법
US9299685B2 (en) Multi-chip package having a logic chip disposed in a package substrate opening and connecting to an interposer
CN102130025A (zh) 晶片及其处理方法和制造半导体装置的方法
KR20210090522A (ko) 인터포즈 브리지를 가진 모듈들이 스택된 반도체 패키지
US20220102315A1 (en) Semiconductor package
US11587912B2 (en) High density pillar interconnect conversion with stack to substrate connection
KR102506697B1 (ko) 관통 몰드 볼 커넥터를 포함하는 반도체 패키지
TWI441312B (zh) 具有打線結構之三維立體晶片堆疊封裝結構
US11631644B2 (en) High density pillar interconnect conversion with stack to substrate connection
KR20110004120A (ko) 반도체 패키지 및 그 제조방법
US11018056B1 (en) Encapsulated solder TSV insertion interconnect
US11721686B2 (en) Semiconductor package structure and packaging method thereof
CN118173531A (zh) 芯片及其制作方法、多芯片堆叠封装及电子设备
KR20130028352A (ko) 반도체 패키지 및 반도체 패키지 방법

Legal Events

Date Code Title Description
PB01 Publication
PB01 Publication
SE01 Entry into force of request for substantive examination
SE01 Entry into force of request for substantive examination
GR01 Patent grant
GR01 Patent grant