TWI743139B - 製造半導體封裝的方法 - Google Patents
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- TWI743139B TWI743139B TW106120522A TW106120522A TWI743139B TW I743139 B TWI743139 B TW I743139B TW 106120522 A TW106120522 A TW 106120522A TW 106120522 A TW106120522 A TW 106120522A TW I743139 B TWI743139 B TW I743139B
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Abstract
一種製造半導體封裝的方法包括:形成至少兩個局部封
裝晶片堆疊,所述局部封裝晶片堆疊中的每一者包括至少兩個半導體晶片且包括第一模具層,所述至少兩個半導體晶片各自包括多個基板穿孔(TSV),所述第一模具層環繞所述至少兩個半導體晶片的側表面;以及在與封裝基板的頂表面垂直的方向上將所述至少兩個局部封裝晶片堆疊依序安裝於所述封裝基板上,使得所述至少兩個局部封裝晶片堆疊包括第一局部封裝晶片堆疊及直接連接至所述第一局部封裝晶片堆疊的第二局部封裝晶片堆疊。
Description
本申請案主張於2016年6月30日在韓國智慧財產局提出申請的韓國專利申請案第10-2016-0082973號的優先權,所述韓國專利申請案的揭露內容全文併入本案供參考。
本發明是有關於一種半導體封裝及其製造方法,且更具體而言是有關於一種包括基板穿孔(through substrate via,TSV)的半導體封裝及其製造方法。
隨著電子行業的急速發展及使用者需求的增大,電子裝置正變得越來越微型化及多功能化。因此,已提出其中各自包括基板穿孔的多個半導體晶片在垂直方向上進行堆疊的半導體封裝。
各種所揭露的實施例提供可靠性得到改善的半導體封裝。
一些所揭露的實施例亦提供一種減少在堆疊半導體晶片
的製程中出現的缺陷的製造半導體封裝的方法。
在一些實施例中,一種製造半導體封裝的方法包括:提供第一子封裝單元,所述第一子封裝單元包括至少兩個第一半導體晶片以及第一模具層,所述至少兩個第一半導體晶片垂直地堆疊,所述第一模具層環繞所述至少兩個第一半導體晶片的側表面;以及提供第二子封裝單元,所述第二子封裝單元包括至少兩個第二半導體晶片以及第二模具層,所述至少兩個第二半導體晶片垂直地堆疊,所述第二模具層環繞所述至少兩個第二半導體晶片的側表面且與所述第一模具層垂直地間隔開。所述第二子封裝單元安置於所述第一子封裝單元上。所述至少兩個第一半導體晶片及所述至少兩個第二半導體晶片各自包括基板穿孔(TSV)。另外,所述至少兩個第一半導體晶片的最頂部半導體晶片電性連接至所述至少兩個第二半導體晶片的最底部半導體晶片且所述至少兩個第一半導體晶片的所述最頂部半導體晶片與所述至少兩個第二半導體晶片的所述最底部半導體晶片之間不存在封裝基板。提供封裝基板,所述至少兩個第一半導體晶片與所述至少兩個第二半導體晶片在所述封裝基板上垂直地堆疊以形成半導體封裝。
在一個實施例中,所述方法可在所述至少兩個第二半導體晶片中安置在最上部的第二半導體晶片的頂表面上提供上部連接墊,且所述上部連接墊可電性連接至所述第二半導體晶片的所述基板穿孔。
在一個實施例中,所述方法可提供絕緣構件,所述絕緣
構件設置於所述至少兩個第二半導體晶片中安置於最上部的第二半導體晶片的頂表面上。
在一個實施例中,所述方法可在所述第一子封裝單元的所述至少兩個第一半導體晶片之間提供第一底部填充構件。所述方法可在所述第二子封裝單元的所述至少兩個第二半導體晶片之間提供第二底部填充構件。
在一個實施例中,所述方法可在所述第一子封裝單元與所述第二子封裝單元之間提供第三底部填充構件,所述第三底部填充構件可接觸所述第一模具層的頂表面及/或所述第二模具層的底表面。
在一個實施例中,所述第三底部填充構件的一部分可安置於所述第一模具層與所述第二模具層之間。
在一個實施例中,所述第三底部填充構件可具有較所述第一底部填充構件或所述第二底部填充構件的水平橫截面積大的水平橫截面積。
在一個實施例中,所述至少兩個第一半導體晶片可具有相同的水平橫截面積,及/或所述至少兩個第二半導體晶片可具有相同的水平橫截面積。
在一個實施例中,所述方法可在所述第一子封裝單元中提供第三半導體晶片,所述第三半導體晶片安置於所述至少兩個第一半導體晶片之下。所述第三半導體晶片可具有較所述至少兩個第一半導體晶片中的每一者的水平橫截面積大的水平橫截面
積,且所述第一模具層可安置於所述第三半導體晶片的頂表面的一部分上。所述方法可在所述第二子封裝單元中提供第四半導體晶片,所述第四半導體晶片安置於所述至少兩個第二半導體晶片之下。所述第四半導體晶片可具有較所述至少兩個第二半導體晶片中的每一者的水平橫截面積大的水平橫截面積,且所述第二模具層可安置於所述第四半導體晶片的頂表面的一部分上。
在一個實施例中,所述方法可提供第三模具層,所述第三模具層環繞所述第一子封裝單元的側表面及所述第二子封裝單元的側表面。所述第三模具層可環繞所述第一模具層的側表面及所述第二模具層的側表面。
在一個實施例中,所述方法可在所述第一子封裝單元與所述第二子封裝單元之間提供第一底部填充構件。所述第三模具層可環繞所述第一底部填充構件的側表面。
在一個實施例中,所述方法可在將所述第二子封裝單元安置於所述第一子封裝單元上之前,測試所述第一子封裝單元及所述第二子封裝單元中的每一者。
在一個實施例中,所述方法可在已形成所述第一子封裝單元及所述第二子封裝單元中的每一者之後,藉由利用焊料凸塊將所述第一子封裝單元的頂部連接端子連接至所述第二子封裝單元的底部連接端子而將所述第一子封裝單元貼合至所述第二子封裝單元,所述焊料凸塊分別直接連接至所述頂部端子及所述底部端子中的每一者。
在一些實施例中,一種製造半導體封裝的方法包括:提供封裝基板;以及藉由首先將第一子封裝單元堆疊於所述封裝基板上且接著將第二子封裝單元堆疊於所述第一子封裝單元上而沿與所述封裝基板的頂表面垂直的方向將多個子封裝單元堆疊於所述封裝基板上。所述多個子封裝單元中的每一者包括:第一緩衝器晶片或邏輯晶片;第一記憶體晶片,安置於所述第一緩衝器晶片或邏輯晶片上;第二記憶體晶片,安置於所述第一記憶體晶片上;以及第一模具層,在所述多個子封裝單元的每一者中,所述第一模具層環繞所述第一記憶體晶片及所述第二記憶體晶片中的每一者的側表面,其中所述第一緩衝器晶片、所述第一記憶體晶片、及所述第二記憶體晶片中的每一者包括基板穿孔(TSV)。所述方法更包括執行回流製程,以將所述第一子封裝單元直接電性連接至所述第二子封裝單元。
在一個實施例中,在所述多個子封裝單元中的每一者中,所述第一模具層可接觸所述第一緩衝器晶片的頂表面且可不安置於所述第一緩衝器晶片的側表面上。
在一個實施例中,所述製造半導體封裝的方法可形成第二模具層,所述第二模具層環繞所述多個子封裝單元的側表面且接觸所述第一緩衝器晶片中的每一者的所述側表面。
在一個實施例中,所述製造半導體封裝的方法可在所述多個子封裝單元中安置於最上部的子封裝單元的頂表面上形成絕緣構件。所述製造半導體封裝的方法可在所述多個子封裝單元中
安置於所述最上部的所述子封裝單元的所述第二記憶體晶片上形成上部連接墊,且所述上部連接墊電性連接至所述第二記憶體晶片的所述基板穿孔。所述絕緣構件可覆蓋所述上部連接墊。
在一個實施例中,在所述多個子封裝單元中的每一者中,所述第一緩衝器晶片可不包括重佈線配線層,所述第一緩衝器晶片的所述基板穿孔可與所述第一記憶體晶片的所述基板穿孔對齊,且所述第一記憶體晶片的所述基板穿孔可與所述第二記憶體晶片的所述基板穿孔對齊。
在一些實施例中,一種製造半導體封裝的方法包括:形成至少兩個局部封裝晶片堆疊,所述局部封裝晶片堆疊中的每一者包括至少兩個半導體晶片且包括第一模具層,所述至少兩個半導體晶片各自包括多個基板穿孔(TSV),所述第一模具層環繞所述至少兩個半導體晶片的各個側;以及在與封裝基板的頂表面垂直的方向上將所述至少兩個局部封裝晶片堆疊依序安裝於所述封裝基板上,使得所述至少兩個局部封裝晶片堆疊包括第一局部封裝晶片堆疊及直接連接至所述第一局部封裝晶片堆疊的第二局部封裝晶片堆疊。
在一個實施例中,所述形成所述至少兩個局部封裝晶片堆疊可包括:在所述局部封裝晶片堆疊中的每一者中,將所述至少兩個半導體晶片中的一者堆疊於所述至少兩個半導體晶片中的另一者上,所述至少兩個半導體晶片中的所述一者與所述至少兩個半導體晶片中的所述另一者之間具有第一底部填充構件。所述
安裝所述至少兩個局部封裝晶片堆疊可包括將所述至少兩個局部封裝晶片堆疊中的一者堆疊於所述至少兩個局部封裝晶片堆疊中的另一者上,所述至少兩個局部封裝晶片堆疊中的所述一者與所述至少兩個局部封裝晶片堆疊中的所述另一者之間具有第二底部填充構件。所述第二底部填充構件的水平橫截面積可大於所述第一底部填充構件的水平橫截面積。
在一個實施例中,所述第二底部填充構件的一部分可安置於所述至少兩個局部封裝晶片堆疊的所述第一模具層之間。
在一個實施例中,所述製造半導體封裝的方法可更包括:在所述安裝所述至少兩個局部封裝晶片堆疊之前,測試所述至少兩個局部封裝晶片堆疊中的每一者的缺陷。
10:第一載體基板
12:第一支撐基板
14:第一膠層
20:第二載體基板
22:第二支撐基板
24:第二膠層
100、100A、100B、100C、100D:半導體封裝
110:第一半導體基板
112、212:第一表面
114、114a、214、514:第二表面
120:第一半導體裝置層
130:第一基板穿孔
132:第一連接墊
134:第一連接凸塊
136:第一後保護層
138:第一上部連接墊
142、142A:第一絕緣材料層
144、144A:第二絕緣材料層
146、146A:第三絕緣材料層
148、148A:第四絕緣材料層
160:第一模具層
210:第二半導體基板
220:第二半導體裝置層
230:第二基板穿孔
232:第二連接墊
234:第二連接凸塊
236:第二後保護層
238:第二上部連接墊
330:第三基板穿孔
430:第四基板穿孔
438:第四上部連接墊
530:第五基板穿孔
536:後保護層
538:第五上部連接墊
610:插入器
612、720:基板基底
614:頂部墊
616:底部墊
630、730:底部填充層
630A、640B、820:底部填充材料層
640、640A:第五絕緣材料層
650:絕緣構件
660:第二模具層
670:插入器連接端子
710:印刷電路板
740:外部連接端子
800:主半導體晶片
810:主連接端子
C1:第一半導體晶片
C1A:第一半導體晶片
C2:第二半導體晶片
C3:第三半導體晶片
C4:第四半導體晶片
C5:第五半導體晶片
M1:子封裝單元
M1A、M2A:子封裝單元
M2:子封裝單元
SL1:第一切割道
SL2:第二切割道
W1:第一半導體晶圓
W2:第二半導體晶圓
藉由結合附圖閱讀以下詳細說明將更清晰地理解本發明概念的實施例,在附圖中:圖1至圖13是說明根據示例性實施例的製造半導體封裝的方法的剖視圖。
圖14至圖18是說明根據示例性實施例的製造半導體封裝的方法的剖視圖。
圖19是說明根據示例性實施例的半導體封裝的剖視圖。
圖20是說明根據示例性實施例的半導體封裝的剖視圖。
圖21是說明根據示例性實施例的半導體封裝的剖視圖。
在下文中,將參照附圖來詳細闡述實施例。在圖式中,為清晰起見,可誇大層及區的大小及相對大小。通篇中相同的編號指代相同的元件。儘管不同的圖示出示例性實施例的各種變型,然而該些圖未必旨在彼此互斥。確切而言,如將自以下詳細說明的上下文中看出,當將各圖及其說明作為整體來考量時,在不同的圖中所繪示及闡述的一些特徵可與來自其他圖的其他特徵加以組合以得到各種實施例。
儘管可使用例如「一個實施例」或「一些實施例」等語言來提及本文所述各圖,然而該些圖及其對應說明並非旨在與其他圖或說明互斥,除非上下文明確如此指示。因此,來自一些圖的一些態樣可與其他圖中的一些特徵相同,及/或一些圖可為特定示例性實施例的不同表示形式或不同部分。
應理解,儘管本文中可能使用「第一」、「第二」、「第三」等用語來闡述各種元件、組件、區、層、及/或區段,然而該些元件、組件、區、層、及/或區段不應受到該些用語限制。除非上下文另有指示,否則該些用語僅用於區分各個元件、組件、區、層、或區段(例如,作為命名約定)。因此,以下在本說明書的一個章節中論述的第一元件、組件、區、層、或區段可在本說明書的另一章節或申請專利範圍中被稱作第二元件、組件、區、層、或區段,而此並不背離本發明的教示內容。另外,在一些情形中,即便未使用「第一」、「第二」等來闡述用語,在本說明書中,仍可在聲明中提及「第一」或「第二」以將不同的所聲明元件彼此區
分。
應理解,當稱一元件「連接」至或「耦合」至另一元件或者「位於」另一元件「上」時,所述元件可直接連接至或直接耦合至所述另一元件或直接位於所述另一元件上,抑或可存在中間元件。相比之下,當稱一元件「直接連接」至或「直接耦合」至另一元件、或者「接觸」另一元件時,則不存在中間元件。用於闡述各元件之間的關係的其他詞語應以相同的方式(例如,「在……之間」相對於「直接位於……之間」、「相鄰於」相對於「直接相鄰於」等)進行解釋。
為易於說明,本文中可能使用例如「之下(beneath)」、「下面(below)」、「下部的(lower)」、「上方(above)」、「上部的(upper)」等空間相對性用語來闡述圖中所示的一個元件或特徵與另一(其他)元件或特徵的關係。應理解,所述空間相對性用語旨在囊括除圖中所繪示定向外裝置在使用或操作中的不同定向。舉例而言,若圖中的裝置被翻轉,則被闡述為「在」其他元件或特徵「下面」或「之下」的元件此時將被定向為「在」所述其他元件或特徵「上方」。因此,用語「在...下面」可同時囊括上方及下方兩種定向。所述裝置可具有其他定向(旋轉90度或處於其他定向)且在本文中所使用的空間相對性描述語將相應地進行解釋。
當本文中在提及取向、佈局、位置、形狀、大小、量、或其他量測方式時使用例如「相同」、「相等」、「平面的」、「共面的」等用語未必意指完全相同的取向、佈局、位置、形狀、大小、
量、或其他量測方式,而是旨在囊括處於可能例如因製造製程而出現的可接收變化內的近似相同的取向、佈局、位置、形狀、大小、量、或其他量測方式。除非上下文或其他陳述另有指示,否則本文中可能使用用語「實質上(substantially)」來強調此含義。舉例而言,被闡述為「實質上相同」、「實質上相等」、或「實質上平面的」用語可為完全相同、完全相等、或完全為平面的,或者可在可例如因製造製程而造成的可接受變化內為相同、相等、或平面的。
例如「約」或「近似」等用語可反映僅以小相對方式(small relative manner)及/或不顯著更改特定元件的運作、功能性、或結構的方式變化的量、大小、定向、或佈局。舉例而言,自「約0.1至約1」的範圍可囊括例如圍繞0.1偏差0%-5%且圍繞1偏差0%至5%的範圍,當此偏差維持的效果與所列範圍相同時尤其如此。
本文中所使用的被闡述為經「電性連接」的項被配置成使得電性訊號可在各個項之間傳遞。因此,實體地連接至被動電性絕緣組件(例如,印刷電路板(printed circuit board,PCB)的預浸體層(pregreg layer)、連接兩個裝置的電性絕緣黏合劑、電性絕緣底部填充物或模具層等)的被動電性導電組件(例如,導線、墊、內部電線等)並不電性連接至所述組件。此外,彼此「直接電性連接」的項是藉由一或多個被動元件例如(舉例而言,導線、墊、內部電線、穿孔(through via)等)來進行電性連接。如此一來,經直接電性連接的組件不包括藉由例如電晶體或二極體
等主動元件而電性連接的組件。經直接電性連接的元件可為直接實體連接的及直接電性連接的。
圖1至圖13是說明根據示例性實施例的製造半導體封裝100的方法的剖視圖。
參照圖1,可製備第一半導體晶圓W1。第一半導體晶圓W1可包括多個第一半導體晶片C1,所述多個第一半導體晶片C1藉由第一切割道SL1而彼此區分開。所述多個第一半導體晶片C1可各自包括第一半導體基板110、第一半導體裝置層120、及第一基板穿孔(TSV)130。第一半導體基板110可包括彼此相對的第一表面112與第二表面114a。可在第一半導體基板110的第一表面112上形成第一半導體裝置層120。可將基板穿孔130形成為自第一半導體基板110的第一表面112穿過第一半導體裝置層120延伸至第一半導體基板110的內部。
第一半導體裝置層120可包括各種多個各別裝置,且可為例如積體電路裝置。所述多個各別裝置可包括例如以下等各種微電子裝置:例如互補金屬氧化物半導體(complementary metal-oxide-semiconductor,CMOS)等金屬氧化物半導體場效電晶體(metal-oxide-semiconductor field effect transistor,MOSFET)、系統大規模積體裝置(system large scale integration,LSI)、例如互補金屬氧化物半導體成像感測器(CMOS imaging sensor,CIS)等影像感測器、微機電系統(micro-electro-mechanical system,MEMS)、主動裝置、被動裝置等。第一半導體裝置層120
可包括多個配線結構,所述多個配線結構用於將所述多個各別裝置連接至形成於第一半導體基板110上的其他配線。然而,第一半導體裝置層120中所包括的所述多個各別裝置的種類並非僅限於以上所述者。
第一基板穿孔130可自第一半導體基板110的第一表面112延伸至第一半導體基板110的內部。第一基板穿孔130的至少一部分可為柱形狀。第一基板穿孔130可包括具有柱形狀的隱埋式導電層、及被形成為環繞所述隱埋式導電層的側表面的障壁層。可在第一半導體基板110與第一基板穿孔130之間安置通孔絕緣層(via insulation layer)(圖中未示出)。第一基板穿孔130可包含氧化物、氮化物、碳化物、聚合物、或其組合。
在後續製程中,可移除第一半導體基板110的一部分,且第一基板穿孔130可包含經過被移除所述一部分的第一半導體基板110的導電材料。舉例而言,第一基板穿孔130可包括障壁層及填充所述障壁層內部的埋置式導電層。作為另一選擇,舉例而言,第一基板穿孔130可包括障壁層、填充所述障壁層內部的埋置式導電層、及金屬配線層的一部分及/或通孔插塞(via plug)的一部分。基板穿孔亦可經過第一半導體裝置層120且可連接至第一半導體裝置層120內的電路系統(例如,連接至第一半導體裝置層120的積體電路)。
參照圖2,可在第一半導體基板110上形成電性連接至第一基板穿孔130的第一連接墊132,且可在第一連接墊132上形成
第一連接凸塊134。
儘管圖中未示出,然而第一連接凸塊134可包括柱層(圖中未示出)及安置於所述柱層上的焊料層(圖中未示出)。舉例而言,可在第一半導體裝置層120上形成包括暴露出第一連接墊132的一部分的開口(圖中未示出)的遮罩圖案(圖中未示出)。接著,可將柱層及焊料層依序堆疊於第一連接墊132的被遮罩圖案暴露出的所述一部分上。舉例而言,可藉由執行電鍍製程來形成柱層及焊料層。接著,可移除遮罩圖案,且可藉由熱處理對焊料層進行回流來形成具有凸形狀的焊料層。儘管在圖2中將第一連接凸塊134示意性地示為具有凸形狀,然而第一連接凸塊134的形狀並非僅限於以上所述者。舉例而言,可將第一連接凸塊134形成為使得柱層具有圓柱形狀,所述圓柱形狀包括與第一半導體裝置層120的頂部垂直的側壁,且焊料層在所述柱層上實質上具有半球形狀。此外,可將柱層形成為其中堆疊有包含不同金屬材料的多個金屬層的結構。
在示例性實施例中,第一連接凸塊134可具有約20微米(μm)至約100微米的水平寬度(例如,在平行於第一半導體晶圓W1的頂部的方向上的寬度),但並非僅限於此。在一些實施例中,第一連接凸塊134可具有約20微米至約60微米的水平寬度。
參照圖3,可將上面形成有第一連接凸塊134的第一半導體晶圓W1貼合於第一載體基板10上。第一載體基板10可包括第一支撐基板12及第一膠層14。可將第一半導體晶圓W1貼合於
第一載體基板10上且使第一連接凸塊134面對第一載體基板10。第一膠層14可環繞第一連接凸塊134。第一半導體基板110的第一表面112的因未被第一連接凸塊134覆蓋而暴露出的一部分可接觸第一膠層14。
參照圖4,可藉由移除第一半導體基板110的一部分來暴露出第一基板穿孔130。可將第一基板穿孔130暴露至第一半導體基板110的第二表面114。由於第一基板穿孔130被暴露至第一半導體基板110的第二表面114,因此第一基板穿孔130可具有穿過第一半導體基板110的形狀。另外,在一些實施例中,可移除第一半導體基板110的一部分以使第一基板穿孔130相對於第二表面114進一步突出,且因此延伸超過第二表面114。
舉例而言,為暴露出第一基板穿孔130,可藉由化學機械研磨(chemical mechanical polishing,CMP)製程、回蝕製程(etch-back process)或其組合來移除第一半導體基板110的一部分。
接著,可形成覆蓋第一半導體晶圓W1的被暴露出的表面(例如,第一半導體基板110的第二表面114)的第一後保護層136。可藉由例如旋塗製程(spin coating process)或噴射製程(spray process)等來形成第一後保護層136。第一後保護層136可包含例如絕緣聚合物。為形成第一後保護層136,可形成覆蓋被暴露出的第一半導體基板110的第二表面114及第一基板穿孔130的絕緣聚合物層,且然後可藉由回蝕製程對所述絕緣聚合物層的一部分
進行移除來暴露出第一基板穿孔130。
可形成電性連接至第一基板穿孔130的被第一後保護層136暴露出的一部分的第一上部連接墊138。視需要,可省略第一上部連接墊138。
參照圖5,可製備第二半導體晶片C2。為製備第二半導體晶片C2,可以與圖1至圖4所示第一半導體晶圓W1相似的方式來加工第二半導體晶圓(圖中未示出),且然後,可藉由對所述第二半導體晶圓進行單體化或切割來製備第二半導體晶片C2。
第二半導體晶片C2可包括第二半導體基板210及形成於第二半導體基板210上的第二半導體裝置層220。第二半導體裝置層220可形成積體電路,且可包括多個各別裝置,所述多個各別裝置包括系統大規模積體裝置、快閃記憶體、動態隨機存取記憶體(dynamic random access memory,DRAM)、靜態隨機存取記憶體(static random access memory,SRAM)、電可抹除可程式化唯讀記憶體(electrical erasable programmable read only memory,EEPROM)、相變隨機存取記憶體(phase-change random access memory,PRAM)、磁阻式隨機存取記憶體(magnetoresistive random access memory,MRAM)、或電阻式隨機存取記憶體(resistive random access memory,RRAM)。
在示例性實施例中,第二半導體晶圓可為包括藉由與形成第一半導體晶圓W1的製程不同的製程而形成的不同種類的各別裝置的半導體晶圓。因此,第二半導體晶片C2可為包括與第一
半導體晶片C1中所包括的各別裝置不同的各別裝置的不同種類的半導體晶片。舉例而言,第一半導體晶圓W1可包括包含系統大規模積體裝置的第一半導體晶片C1,且第二半導體晶片C2可包括動態隨機存取記憶體。第一半導體晶片C1可為邏輯晶片,且第二半導體晶片C2可為記憶體晶片。
在其他實施例中,第二半導體晶圓可為包括藉由與形成第一半導體晶圓W1的製程相同的製程而形成的相同種類的各別裝置的半導體晶圓。第二半導體晶片C2可為包括與第一半導體晶片C1中所包括的各別裝置相同的各別裝置的相同種類的半導體晶片。舉例而言,第一半導體晶圓W1可包括包含動態隨機存取記憶體晶片的第一半導體晶片C1,且第二半導體晶片C2可包括動態隨機存取記憶體。
可設置多個第二半導體晶片C2。第二載體基板20可包括第二支撐基板22及第二膠層24。可將所述多個第二半導體晶片C2以其中所述多個第二半導體晶片C2彼此連接的第二半導體晶圓W2的形式貼合於第二載體基板20上,且然後,可將所述第二半導體晶圓切割成所述多個第二半導體晶片C2。所述多個第二半導體晶片C2可各自包括第二半導體基板210、第二半導體裝置層220、及第二貫穿電極(第二基板穿孔230)。第二半導體基板210可包括彼此相對的第一表面212與第二表面214。第二貫穿電極(第二基板穿孔230)可經過第二半導體基板210。
所述多個第二半導體晶片C2可各自包括第二連接墊
232、第二連接凸塊234、第二後保護層236及第二上部連接墊238。關於第二連接墊232、第二連接凸塊234、第二後保護層236、及第二上部連接墊238的詳細說明相似於以上參照圖2所述的第一連接墊132、第一連接凸塊134、第一後保護層136及第一上部連接墊138。
參照圖6,可使所述多個第二半導體晶片C2與圖5中所示第二載體基板20分離開且可將所述多個第二半導體晶片C2堆疊於圖6中所示第一半導體晶圓W1上。可將所述多個第二半導體晶片C2堆疊於第一半導體晶圓W1上以分別對應於第一半導體晶圓W1中所包括的所述多個第一半導體晶片C1。舉例而言,可將所述多個第二半導體晶片C2堆疊於所述多個第一半導體晶片C1上以分別對應於第一半導體晶片C1。
在示例性實施例中,可將第二半導體晶片C2中的每一者貼合於對應的第一半導體晶片C1上,第二半導體晶片C2中的所述每一者與對應的第一半導體晶片C1之間具有第一絕緣材料層142。舉例而言,在將所述多個第二半導體晶片C2以其中所述多個第二半導體晶片C2彼此連接的第二半導體晶圓W2的形式貼合於第二載體基板20(圖5)上之前,可在第二半導體晶圓W2與第二載體基板20(圖5)之間安置第一絕緣材料層142。接著,可將第二半導體晶圓W2切割成所述多個第二半導體晶片C2,且可將第一絕緣材料層142以貼合於第二半導體晶片C2中的每一者上的狀態定位於第一半導體晶片C1上。
可將第二半導體晶片C2中的每一者堆疊於對應的第一半導體晶片C1上以使第一貫穿電極(第一基板穿孔130)電性連接至第二貫穿電極(第二基板穿孔230)。為使第一貫穿電極(第一基板穿孔130)電性連接至第二貫穿電極(第二基板穿孔230),可將第二半導體晶片C2中的每一者堆疊於對應的第一半導體晶片C1上以使對應的第二半導體晶片C2的第二連接凸塊234接觸第一連接凸塊134。若未形成第一連接凸塊134,則第二連接凸塊234可接觸第一貫穿電極(第一基板穿孔130)。
在將第二半導體晶片C2分別堆疊於第一半導體晶片1上之後,可藉由執行回流製程或熱壓縮製程(thermal compression process)來增大第二連接凸塊234與第一連接凸塊134之間的或第二連接凸塊234與第一貫穿電極(第一基板穿孔130)之間的黏合力,藉此減小接觸電阻。
如圖6中所示例性地說明,可將第一絕緣材料層142安置於第一半導體晶片C1與第二半導體晶片C2之間以環繞第一上部連接墊138及第二連接凸塊234且環繞多個第一上部連接墊138及第二連接凸塊234。舉例而言,第一絕緣材料層142可環繞且覆蓋安置於第一半導體晶片C1與第二半導體晶片C2之間且將第一半導體晶片C1連接至第二半導體晶片C2的第一上部連接墊138及第二連接凸塊234中的所有者。在示例性實施例中,第一絕緣材料層142可為絕緣聚合物。舉例而言,可藉由貼合非導電膜(nonconductive film,NCF)來形成第一絕緣材料層142。第一絕
緣材料層142可為底部填充構件,所述底部填充構件密封第一半導體晶片C1與第二半導體晶片C2之間的連接部分且填充第一半導體晶片C1與第二半導體晶片C2之間的空間。
此處,用語「底部填充構件」可未必表示藉由特定製造方法形成的或由特定材料形成的元件,但可表示填充半導體晶片之間的空間、半導體晶片與插入器(interposer)之間的空間、或插入器與印刷電路板(PCB)之間的空間的材料層。舉例而言,應理解,底部填充構件表示本文所述絕緣材料層,或以下欲闡述的底部填充層或底部填充材料層。
參照圖7,藉由重複以上參照圖5及圖6所述的製程,可在第一半導體晶圓W1上堆疊多個第三半導體晶片C3以分別對應於所述多個第二半導體晶片C2,第一半導體晶圓W1與所述多個第三半導體晶片C3之間、所述多個第二半導體晶片C2上具有第二絕緣材料層144。接著,藉由執行回流製程或熱壓縮製程,可將第三半導體晶片C3中的每一者電性連接至對應的第二半導體晶片C2。相似地,可在第一半導體晶圓W1上堆疊多個第四半導體晶片C4以分別對應於所述多個第三半導體晶片C3,第一半導體晶圓W1與所述多個第四半導體晶片C4之間、所述多個第三半導體晶片C3上具有第三絕緣材料層146。接著,藉由執行回流製程或熱壓縮製程,可將第四半導體晶片C4中的每一者電性連接至對應的第三半導體晶片C3。此外,可在第一半導體晶圓W1上堆疊多個第五半導體晶片C5以分別對應於所述多個第四半導體晶片
C4,第一半導體晶圓W1與所述多個第五半導體晶片C5之間、所述多個第四半導體晶片C4上具有第四絕緣材料層148。接著,藉由執行回流製程或熱壓縮製程,可將第五半導體晶片C5中的每一者電性連接至對應的第四半導體晶片C4。
第二半導體晶片C2至第五半導體晶片C5可為各自包括相同各別裝置的相同種類的半導體晶片。作為另一選擇,第二半導體晶片C2至第五半導體晶片C5可為包括不同各別裝置的不同種類的半導體晶片。儘管在圖7中,示例性地說明其中第二半導體晶片C2至第五半導體晶片C5垂直地堆疊於第一半導體晶圓W1上的五半導體晶片堆疊結構(five-semiconductor chip stacked structure),然而可改變堆疊於第一半導體晶圓W1上的半導體晶片的數目。
此外,在第一半導體晶片C1與第二半導體晶片C2之間形成第一絕緣材料層142時,可例如藉由毛細底部填充製程(capillary under-fill process)以環氧樹脂(epoxy resin)形成第一底部填充層。第一底部填充層可與填料混合,且所述填料可包含例如二氧化矽。相似地,可形成第二底部填充層至第四底部填充層而非形成第二絕緣材料層144、第三絕緣材料層146及第四絕緣材料層148。
參照圖8,可在第一半導體晶圓W1上形成覆蓋第二半導體晶片C2與第五半導體晶片C5的第一模具層160。第一模具層160(亦被闡述為包封層(encapsulation layer))可環繞第二半導
體晶片C2至第五半導體晶片C5的各個側(例如,側表面)。第一模具層160可接觸第一半導體晶片C1的頂部的一部分。由於將第一絕緣材料層142、第二絕緣材料層144、第三絕緣材料層146及第四絕緣材料層148安置於第一半導體晶片C1至第五半導體晶片C5之間,因此第一模具層160可環繞第一絕緣材料層142、第二絕緣材料層144、第三絕緣材料層146、及第四絕緣材料層148的各個側(例如,側表面)。在示例性實施例中,第一模具層160可包含環氧模具化合物(epoxy mold compound,EMC)。
如圖8中所示例性地說明,在一個實施例中,第一模具層160不覆蓋第五半導體晶片C5的頂部(例如,第二表面514)。因此,可使第五半導體晶片C5中所包括的後保護層536及第五上部連接墊538暴露至第一模具層160的外部。
參照圖9,可使用第五半導體晶片C5的被第一模具層160暴露出的第五上部連接墊538來執行用於評估第一半導體晶片C1至第五半導體晶片C5中的每一者的正常運作或缺陷的電性特性測試(electrical characteristic test)。所述電性特性測試可為用於測試晶片堆疊的諸多習知測試過程中的一者。
如圖9中所示例性地說明,第五半導體晶片C5可包括第五基板穿孔530,且可在第五半導體晶片C5的第二表面514上設置第五上部連接墊538。因此,可在其中第一半導體晶片C1至第五半導體晶片C5堆疊於第一載體基板10上的狀態(即,其中第一半導體晶片C1至第五半導體晶片C5不與第一載體基板10分離
開的狀態)中容易地執行電性特性測試。
大體而言,由於安置於晶片堆疊的最上部(例如,堆疊中的頂部晶片)上的半導體晶片不包括基板穿孔(及/或上部連接墊),因此為執行電性特性測試,需要將半導體晶片的堆疊結構與載體基板分離開,且將半導體晶片的所述堆疊結構垂直地倒轉以使半導體晶片的堆疊結構面朝上安置於最下部(例如,堆疊中的底部晶片)中。然而,根據所揭露的實施例,由於第五半導體晶片C5包括第五基板穿孔530及第五上部連接墊538,因此執行電性特性測試不需要將第一半導體晶片C1至第五半導體晶片C5的堆疊結構與第一載體基板10分離開或垂直地倒轉。因此,可容易地對第一半導體晶片C1至第五半導體晶片C5執行電性特性測試。
參照圖10,藉由沿第一切割道SL1(參見圖2)切割第一半導體晶圓W1(參見圖9),第一半導體晶圓W1可被切割成包括彼此對應的第一半導體晶片C1至第五半導體晶片C5的多個子封裝單元M1。在本文中亦可將每一子封裝單元M1(或M2)稱作局部封裝晶片堆疊。
子封裝單元M1可具有其中包括第二基板穿孔230的第二半導體晶片C2、包括第三基板穿孔330的第三半導體晶片C3、包括第四基板穿孔430的第四半導體晶片C4、及包括第五基板穿孔530的第五半導體晶片C5依序堆疊於包括第一基板穿孔130的第一半導體晶片C1上的結構。第一半導體晶片C1至第五半導體晶片C5可為局部地覆蓋有模具層的晶片堆疊。舉例而言,晶片堆疊
可包括模具層,所述模具層覆蓋第一半導體晶片C1的頂表面的邊緣部分且覆蓋其餘第二半導體晶片C2至第五半導體晶片C5的側表面。
在示例性實施例中,第一半導體晶片C1至第五半導體晶片C5可為相同種類的半導體晶片。舉例而言,第一半導體晶片C1至第五半導體晶片C5可各自為記憶體晶片。在其他實施例中,第一半導體晶片C1可不同於第二半導體晶片C2至第五半導體晶片C5。舉例而言,第一半導體晶片C1可為邏輯晶片,且第二半導體晶片C2至第五半導體晶片C5可各自為記憶體晶片。在其他實施例中,第一半導體晶片C1可為緩衝器晶片,且第二半導體晶片C2至第五半導體晶片C5可各自為記憶體晶片。然而,本發明概念的技術精神並非僅限於此。根據本文所述的各種實施例,子封裝單元M1(及子封裝單元M2)中的每一第一半導體晶片C1至第五半導體晶片C5包括積體電路。舉例而言,可將所述積體電路形成於由晶圓形成的半導體晶粒上。
在示例性實施例中,第二半導體晶片C2至第五半導體晶片C5可實質上具有相同的水平橫截面積,且第一半導體晶片C1的水平橫截面積可大於第二半導體晶片C2至第五半導體晶片C5的水平橫截面積。
可將第一絕緣材料層142安置於第一半導體晶片C1與第二半導體晶片C2之間,可將第二絕緣材料層144安置於第二半導體晶片C2與第三半導體晶片C3之間。此外,可將第三絕緣材料
層146安置於第三半導體晶片C3與第四半導體晶片C4之間,且可將第四絕緣材料層148安置於第四半導體晶片C4與第五半導體晶片C5之間。
可將第一模具層160形成於第一半導體晶片C1上的一部分上以環繞第二半導體晶片C2至第五半導體晶片C5的各個側。第一半導體晶片C1可具有較第二半導體晶片C2至第五半導體晶片C5的水平橫截面積大的水平橫截面積,且因此,第一半導體晶片C1的所述側可不被第一模具層160環繞。可將第一模具層160的一側與第一半導體晶片C1的所述側對齊。舉例而言,第一模具層160的側表面與第一半導體晶片C1的側表面可共面。第一模具層160可接觸第一絕緣材料層142、第二絕緣材料層144、第三絕緣材料層146及第四絕緣材料層148。
第二半導體晶片C2至第四半導體晶片C4可經由第二基板穿孔230、第三基板穿孔330及第四基板穿孔430而電性連接至第一半導體晶片C1及第五半導體晶片C5。由於第二半導體晶片C2至第四半導體晶片C4的各個側被第一模具層160環繞,因此第二半導體晶片C2至第四半導體晶片C4可不暴露至子封裝單元M1的外部,且第一半導體晶片C1的第一連接凸塊134及第五半導體晶片C5的第五上部連接墊538可暴露至子封裝單元M1的外部。在其他實施例中,可不提供第五上部連接墊538,且在此種情形中,第五基板穿孔530可暴露至子封裝單元M1的外部。
第一半導體晶片C1可不包括重佈線配線層。因此,第一
基板穿孔130的節距(或相鄰第一基板穿孔130之間的間隔)可與第一連接凸塊134的節距(或相鄰第一連接凸塊134之間的間隔)實質上相同。此外,可將第一基板穿孔130與第一連接凸塊134沿與第一半導體晶片C1的頂部垂直的方向對齊且可將第一基板穿孔130與第二基板穿孔230、第三基板穿孔330、第四基板穿孔430及第五基板穿孔530沿與第一半導體晶片C1的所述頂部垂直的方向對齊。此處,第一基板穿孔130與第一連接凸塊134沿垂直方向對齊可表示當自子封裝單元M1的最上部的表面觀察時(例如,當在平面圖中觀察時)第一基板穿孔130與第一連接凸塊134重疊。由於第一基板穿孔130與第二基板穿孔230、第三基板穿孔330、第四基板穿孔430及第五基板穿孔530沿垂直方向對齊,因此第一連接凸塊134與第五上部連接墊538可沿垂直方向彼此對齊。因此,可將子封裝單元M1垂直地堆疊於另一子封裝單元M1上(例如,不在子封裝單元M1與另一子封裝單元M2之間使用重佈線層、封裝基板、或插入器基板)。
在上文中,已示例性地闡述其中子封裝單元M1包括垂直堆疊的第一半導體晶片C1至第五半導體晶片C5的子封裝單元M1的實例,但本發明概念的技術精神並非僅限於此。舉例而言,可改變子封裝單元M1中的堆疊半導體晶片的數目。舉例而言,子封裝單元M1可包括兩個或四個半導體晶片,或者可包括六個或更多個半導體晶片。
參照圖11,可視需要製備及提供插入器610。
插入器610可包括基板基底(substrate base)612、設置於基板基底612的頂部上的頂部墊614、及設置於基板基底612的底部上的底部墊616。在示例性實施例中,基板基底612可包含半導體材料,且舉例而言,可由矽晶圓形成。可在基板基底612頂部、底部或內部形成內部配線(圖中未示出)。此外,可在基板基底612中形成將頂部墊614電性連接至底部墊616的基板穿孔(圖中未示出)及重佈線配線層(圖中未示出)。
舉例而言,可將插入器610貼合於載體基板(圖中未示出)上,且可在插入器610上安置子封裝單元M1。在此種情形中,可將子封裝單元M1安置成使得子封裝單元M1的第一半導體晶片C1面對插入器610的頂部墊614。接著,藉由執行回流製程或熱壓縮製程,可將第一半導體晶片C1的第一連接凸塊134貼合於頂部墊614上。
在一個實施例中,接著,可在子封裝單元M1與插入器610之間形成底部填充層630。舉例而言,可藉由毛細底部填充製程以環氧樹脂形成底部填充層630。可將底部填充層630與填料進行混合,且所述填料可包括例如二氧化矽。在其他實施例中,可使用絕緣聚合物或非導電膜形成絕緣材料層(圖中未示出)而非在子封裝單元M1與插入器610之間形成底部填充層630。
在一個實施例中,接著,可在子封裝單元M1上安置子封裝單元M2。子封裝單元M2可具有與以上參照圖10所述的子封裝單元M1的技術特徵相同的技術特徵。
如圖11中所示例性地說明,可在子封裝單元M1的第五半導體晶片C5上安置子封裝單元M2的第一半導體晶片C1,且可在子封裝單元M1的第五半導體晶片C5的第五上部連接墊538上安置子封裝單元M2的第一半導體晶片C1的第一連接凸塊134。
可在子封裝單元M1與子封裝單元M2之間安置第五絕緣材料層640。第五絕緣材料層640可包含絕緣聚合物或非導電膜。在一個實施例中,第五絕緣材料層640可具有較第一絕緣材料層142、第二絕緣材料層144、第三絕緣材料層146及第四絕緣材料層148的水平橫截面積大的水平橫截面積。因此,第五絕緣材料層640的邊緣可安置於子封裝單元M1的第一模具層160與子封裝單元M2的第一模具層160之間,且第五絕緣材料層640可具有與子封裝單元M1的第一模具層160的側表面及子封裝單元M2的第一模具層160的側表面共面的側表面。
接著,藉由執行回流製程或熱壓縮製程,可將子封裝單元M2的第一半導體晶片C1的第一連接凸塊134貼合於子封裝單元M1的第五半導體晶片C5的第五上部連接墊538上,且可將第五絕緣材料層640安置於子封裝單元M2的第一半導體晶片C1與子封裝單元M1的第五半導體晶片C5的第五上部連接墊538之間以環繞第一連接凸塊134及第五上部連接墊538。藉由此方式,圖11說明一種在已形成第一子封裝單元及第二子封裝單元中的每一者之後藉由以下方式而將所述第一子封裝單元或局部封裝晶片堆疊(例如,子封裝單元M1)貼合至第二子封裝單元或局部封裝晶
片堆疊(例如,子封裝單元M2)的方法:利用焊料凸塊(例如,第一連接凸塊134)將第一子封裝單元的頂部連接端子(例如,第五上部連接墊538或在其他實施例中,突出的基板穿孔)連接至第二子封裝單元的底部連接端子(例如,第一連接墊132或在其他實施例中,突出的基板穿孔),所述焊料凸塊(例如,第一連接凸塊134)分別直接連接至頂部端子及底部端子中的每一者。藉由此方式,可使用焊料凸塊將一個子封裝單元(例如,子封裝單元M2)直接連接至另一子封裝單元(例如,子封裝單元M1)。
在圖11中,示例性地說明其中堆疊有子封裝單元M1及M2的實例。作為另一選擇,子封裝單元M2上可更堆疊有其他子封裝單元M1及M2。舉例而言,可堆疊的子封裝單元M1及M2的數目可根據記憶體晶片的所期望容量來改變。
堆疊於插入器610上的子封裝單元M1及M2中的每一者可為已在以上參照圖9所述的電性特性測試中被驗證為能夠正常運作的子封裝單元(例如,已知良好封裝(known good package,KGP)單元)。舉例而言,在形成封裝的已完全連接好的晶片堆疊之前,可在形成子封裝單元M1及M2的製程中篩選出在電性連接方面存在缺陷的半導體晶片,且可僅將正常運作的子封裝單元M1及M2堆疊於插入器610上。
參照圖12,可將絕緣構件650貼合於子封裝單元M2上。絕緣構件650可覆蓋暴露至子封裝單元M2外部的第五上部連接墊538(當未提供第五上部連接墊538時覆蓋第五基板穿孔530)。絕
緣構件650可為例如絕緣材料層。
參照圖13,可在插入器610上形成環繞子封裝單元M1及M2的各個側的第二模具層660。第二模具層660可環繞第一模具層160的一側及第一半導體晶片C1的一側且可將第二模具層660安置於插入器610的頂部的一部分中。安置於子封裝單元M1與M2之間的第五絕緣材料層640亦可接觸第二模具層660。在一個實施例中,第二模具層660具有與插入器610的相應側表面共面的外側表面。然而,實施例未必僅限於此構造。
如圖13中所示例性地說明,第二模具層660與第一模具層160之間的介面可與第二模具層660與第五絕緣材料層640之間的介面對齊。舉例而言,第二模具層660可包括實質上平的側表面且所述側表面在第一模具層160與第五絕緣材料層640之間的邊界附近為連續的。第二模具層660的內側表面可為平面的。
可將插入器連接端子670貼合於插入器610的底部上。可將插入器連接端子670貼合於例如底部墊616上。插入器連接端子670可為例如焊料球或凸塊。
在示例性實施例中,在插入器610的底部處,插入器連接端子670可包括安置於底部墊616上的凸塊下金屬(under bump metal,UBM)(圖中未示出)及安置於所述凸塊下金屬上的焊料球(圖中未示出)。插入器連接端子670可更包括安置於凸塊下金屬與焊料球之間的外部連接柱(圖中未示出),且所述外部連接柱可包含例如銅。
接著,可提供印刷電路板710。
印刷電路板710可包括基板基底720、設置於基板基底720的頂部上的頂部墊(圖中未示出)、及設置於基板基底720的底部上的底部墊(圖中未示出)。頂部墊及底部墊可被覆蓋基板基底720的頂部及底部的阻焊層(solder resist layer)(圖中未示出)暴露出。基板基底720可由酚醛樹脂、環氧樹脂及聚醯亞胺中的至少一者形成。舉例而言,基板基底720可包含選自FR4、四官能環氧樹脂(tetrafunctional epoxy)、聚伸苯醚(polyphenylene ether)、環氧/聚苯醚、雙馬來醯亞胺三嗪(bismaleimide triazine,BT)、聚醯胺短纖席材®(Thermount®)、氰酸酯(cyanate ester)、聚醯亞胺、及液晶聚合物(liquid crystal polymer)的至少一種材料。頂部墊與底部墊可各自由Cu、Ni、不銹鋼、鈹銅、及/或類似材料形成。可在基板基底720中提供電性連接至頂部墊及底部墊的內部配線(圖中未示出)。頂部墊及底部墊可為藉由將塗佈於基板基底720的頂部及底部上的Cu箔圖案化而形成的電路配線的被阻焊層暴露出的部分。
插入器610可安置於印刷電路板710上,使得插入器連接端子670位於印刷電路板710的頂部墊上,且可在插入器610與印刷電路板710之間形成底部填充層730。可將外部連接端子740貼合於印刷電路板710的底部墊上。舉例而言,外部連接端子740可為焊料球或凸塊。
儘管以上以特定次序闡述與圖11至圖13相關的各種步
驟且在一個實施例中所述步驟是以此次序進行,然而不同組件進行組合的的次序無需遵循此次序。無論次序如何,在上文中及下文中所論述的已完工的封裝的不同元件均可以半導體裝置(例如,半導體封裝)的形式來提供,所述半導體裝置可為例如記憶體裝置、邏輯裝置、或組合式記憶體與邏輯裝置。
在一個實施例中,作為以上步驟的結果,第一子封裝單元M1的外側表面可與堆疊於第一子封裝單元M1上的第二子封裝單元M2的外側表面共面。然而,完整的封裝單元M1+M2的外側表面可不與插入器610的外側表面垂直地對齊。插入器610可為封裝基板(例如,上面堆疊有半導體晶片)。插入器610可為重佈線基板。印刷電路板710亦可為封裝基板,且可被闡述為重佈線基板。舉例而言,插入器610及/或印刷電路板710可具有用於在封裝外部與完整的封裝單元M1+M2中的各種第一半導體晶片C1至第五半導體晶片C5之間傳遞訊號的主要功能及主要元件。舉例而言,在一些實施例中,插入器610或印刷電路板710不包括執行邏輯操作或儲存操作的積體電路系統。另一方面,第一半導體晶片C1至第五半導體晶片C5中的每一者可包括積體電路且可具有執行邏輯操作或儲存資料的主要目的。
此外,在以上說明中,已示例性地闡述了其中插入器610安裝於印刷電路板710上且子封裝單元M1及M2安裝於插入器610上的結構,但本發明概念的技術精神並非僅限於此。在其他實施例中,封裝基板上可堆疊有不同數目的子封裝單元M1及M2。
此處,用語「封裝基板」可表示可在上面堆疊根據本發明概念的子封裝單元M1及M2的任意基板,且因此,應理解封裝基板包括例如插入器610、印刷電路板710、其組合、陶瓷基板、半導體基板等各種基板。與圖13中所示者不同,可將子封裝單元M1及M2安裝於插入器610上,且可省略印刷電路板710。作為另一選擇,可將子封裝單元M1及M2直接安裝於印刷電路板710上,且可省略插入器610。
可藉由上述製程來完整地形成半導體封裝100。
根據製造半導體封裝100的方法,可首先製造包括第一半導體晶片C1至第五半導體晶片C5的子封裝單元M1及M2,且可測試子封裝單元M1及M2以確保其沒有缺陷。然後,藉由根據半導體封裝的所期望容量來堆疊多個子封裝單元M1及M2,可完整地形成半導體封裝100。
大體而言,在垂直地堆疊各自包括基板穿孔的多個半導體晶片的情形中,逐一地將所述半導體晶片依序堆疊於封裝基板上。然而,隨著堆疊半導體晶片的數目的增大及/或半導體晶片的基板穿孔的大小及節距的減小,在堆疊半導體晶片的製程中容易出現接合缺陷(junction defect)(或內連線缺陷),且因此,難以在半導體晶片之間提供高可靠性電性連接。舉例而言,在逐一地將半導體晶片堆疊於半導體基板上的情形中,經常需要多次執行用於在基板穿孔與連接凸塊之間達成電性連接的高溫回流製程或熱壓縮製程,所述次數與堆疊半導體晶片的數目相等。因此,重
複進行高溫製程會將熱/實體損壞施加至連接凸塊與基板穿孔之間的連接部分。另外,在逐一地將半導體晶片堆疊於封裝基板上的情形中,在製造其中所期望數目的半導體晶片皆已進行堆疊的封裝之後,測試所述封裝的缺陷。舉例而言,當封裝被確定為其中電性連接為有缺陷的封裝(例如,即便可僅存在一個有缺陷的半導體晶片)時,可能捨棄整個封裝,使得所述封裝中所包括的所有半導體晶片無法使用。因此,在半導體封裝製程中半導體晶片的損失增大(或半導體晶片的良率降低)。
然而,根據製造半導體封裝100的上述方法,可首先製造其中堆疊有一定數目的半導體晶片C1至C5的子封裝單元M1及M2,且然後,可在封裝基板上堆疊所述多個子封裝單元M1及M2,藉此獲得其中第一半導體晶片C1至第五半導體晶片C5經由第一基板穿孔130、第二基板穿孔230、第三基板穿孔330、第四基板穿孔430及第五基板穿孔530而彼此連接的半導體封裝100。因此,使子封裝單元M1及M2中所包括的第一半導體晶片C1至第五半導體晶片C5暴露於執行時間縮短的高溫製程,藉此防止因所述高溫製程而施加至連接凸塊或所述連接凸塊與基板穿孔之間的連接部分的熱/實體損壞。因此,半導體封裝100具有高的可靠性。
此外,在封裝基板上堆疊子封裝單元M1及M2之前可測試子封裝單元M1及M2中的每一者的缺陷。因此,由於之前在製造子封裝單元M1及M2的製程中篩選出了在電性連接方面存在缺
陷的半導體晶片,因此半導體封裝100的缺陷率降低。所述兩個子封裝單元M1及M2可共享相同的封裝基板,例如使得頂部子封裝單元M2或局部封裝晶片堆疊堆疊於底部子封裝單元M1或局部封裝晶片堆疊上,且頂部子封裝單元M2或局部封裝晶片堆疊與底部子封裝單元M1或局部封裝晶片堆疊之間不存在任何封裝基板。如此一來,所述兩個子封裝單元M1及M2可以上述方式中的一或多者來加以組合以形成單一封裝(例如,可將半導體封裝100視作具有單一封裝基板的單一封裝而非包括多個封裝基板的疊層封裝裝置(package-on-package device))。
圖14至圖18是說明根據示例性實施例的製造半導體封裝100A的方法的剖視圖。在圖14至圖18中,圖1至圖13中所示相同的參考編號指代相同的元件。
首先,藉由執行以上參照圖1至圖4所述的製程,可製備連接至第一半導體晶片C1A的第一半導體晶圓W1(參見圖4)。
參照圖14,可藉由切割第一半導體晶圓W1來製備第一半導體晶片C1A。舉例而言,可將第一半導體晶圓W1在貼合於第一載體基板10上的狀態下切割成第一半導體晶片C1A(例如,多個第一半導體晶片C1A)。
參照圖15,在其中與第一半導體晶圓W1分離開的第一半導體晶片C1A貼合於第一載體基板10上的狀態中,可在第一半導體晶片C1A上安置第二半導體晶片C2。對第二半導體晶片C2的詳細說明與參照圖5所作的說明相似。
第一半導體晶片C1A與第二半導體晶片C2可為包括相同種類的各別裝置的相同種類的半導體晶片。舉例而言,第一半導體晶片C1A及第二半導體晶片C2可各自為記憶體晶片。此外,第一半導體晶片C1A與第二半導體晶片C2可實質上具有相同的水平橫截面積。然而,本發明概念的技術精神並非僅限於此,且第二半導體晶片C2可為包括與第一半導體晶片C1A的各別裝置不同的各別裝置的不同種類的半導體晶片。
藉由與以上參照圖5至圖7所述的製程相似的製程,可在第二半導體晶片C2上堆疊第三半導體晶片C3,且可在第三半導體晶片C3上堆疊第四半導體晶片C4。
參照圖16,可在載體基板10上形成覆蓋第一半導體晶片C1A、第二半導體晶片C2、第三半導體晶片C3至第四半導體晶片C4的各個側的第一模具層160。第一模具層160可環繞安置於第一半導體晶片C1A、第二半導體晶片C2、第三半導體晶片C3至第四半導體晶片C4之間的第一絕緣材料層142、第二絕緣材料層144至第三絕緣材料層146的各個側。此外,第一模具層160可不覆蓋第四半導體晶片C4的第二表面(或第四半導體晶片C4的頂部)。
接著,可藉由第四半導體晶片C4的未被第一模具層160覆蓋的第四上部連接墊438來執行用於評估第一半導體晶片C1A、第二半導體晶片C2、第三半導體晶片C3至第四半導體晶片C4中的每一者的缺陷的電性特性測試。
參照圖17,可沿第二切割道SL2(參見圖16)切割藉由第一模具層160而彼此連接的第一半導體晶片C1A、第二半導體晶片C2、第三半導體晶片C3至第四半導體晶片C4的堆疊結構,且因此,可將所述堆疊結構切割成包括彼此對應的第一半導體晶片C1A、第二半導體晶片C2、第三半導體晶片C3至第四半導體晶片的子封裝單元M1A。另外,可移除載體基板10。
子封裝單元M1A可包括具有相同水平橫截面積的第一半導體晶片C1A、第二半導體晶片C2、第三半導體晶片C3至第四半導體晶片C4。第一模具層160可環繞第一半導體晶片C1A、第二半導體晶片C2、第三半導體晶片C3至第四半導體晶片C4的各個側。第一半導體晶片C1的第一連接凸塊134可暴露至子封裝單元M1A的外部而不被第一模具層160覆蓋,且不被任何模具層直接覆蓋。若省略第四半導體晶片C4的第四上部連接墊438,則可將第四基板穿孔430暴露至子封裝單元M1A的外部而不被第一模具層160覆蓋,且不被任何模具層直接覆蓋。
接著,可藉由以上參照圖11至圖13所述的製程來完整地形成圖18中所示半導體封裝100A。
半導體封裝100A可包括垂直堆疊的子封裝單元M1A及M2A、安置於子封裝單元M1A與M2A之間的第五絕緣材料層640、以及環繞子封裝單元M1A及M2A的各個側及第五絕緣材料層640的各個側的第二模具層660。可在子封裝單元M1A的第一模具層160與子封裝單元M2A的第一模具層160之間安置第五絕
緣材料層640的一部分(例如,第五絕緣材料層640的邊緣)。第五絕緣材料層640可具有較第一絕緣材料層142、第二絕緣材料層144至第三絕緣材料層146的水平橫截面積大的水平橫截面積。
由於第一半導體晶片C1A、第二半導體晶片C2、第三半導體晶片C3至第四半導體晶片C4具有相同的水平橫截面積且第一半導體晶片C1A、第二半導體晶片C2、第三半導體晶片C3至第四半導體晶片C4的各個側被第一模具層160環繞,因此第一半導體晶片C1A、第二半導體晶片C2、第三半導體晶片C3至第四半導體晶片C4可不接觸第二模具層660。
根據製造半導體封裝100A的上述方法,可使子封裝單元M1A及M2A中所包括的第一半導體晶片C1A、第二半導體晶片C2、第三半導體晶片C3至第四半導體晶片C4暴露於執行時間縮短的高溫製程,且因此減少或防止因所述高溫製程而施加至連接凸塊或所述連接凸塊與基板穿孔之間的連接部分的熱/實體損壞。因此,半導體封裝100A具有高的可靠性。由於之前在製造子封裝單元M1A及M2A的製程中可篩選出在電性連接方面存在缺陷的半導體晶片,因此半導體封裝100A的缺陷率降低。
圖19是說明根據示例性實施例的半導體封裝100B的剖視圖。在圖19中,圖1至圖18中相同的參考編號指代相同的元件。除第一絕緣材料層142A142A、第二絕緣材料層144A、第三絕緣材料層146A、第四絕緣材料層148A及第五絕緣材料層640A以外,半導體封裝100B可與以上參照圖1至圖13所述的半導體
封裝100實質上相同。
參照圖19,第一絕緣材料層142A、第二絕緣材料層144A、第三絕緣材料層146A及第四絕緣材料層148A可具有相對於第二半導體晶片C2至第五半導體晶片C5而以凸的方式突出的形狀。在示例性實施例中,第一絕緣材料層142A、第二絕緣材料層144A、第三絕緣材料層146A及第四絕緣材料層148A可藉由貼合非導電膜來形成。舉例而言,在製造子封裝單元M1及M2的製程中,在將第二半導體晶片C2貼合成連接至第一半導體晶片C1的第一基板穿孔130的同時施加壓力,且因此,第一絕緣材料層142A可具有以凸的方式突出的形狀。
第五絕緣材料層640A可具有相對於第一半導體晶片C1的一側或第一模具層160的一側而以凸的方式突出的形狀。第五絕緣材料層640A可藉由貼合非導電膜來形成。舉例而言,可將第五絕緣材料層640A貼合於子封裝單元M1上以使子封裝單元M2的第一基板穿孔130電性連接至子封裝單元M1的第五基板穿孔530,且可將子封裝單元M2貼合於第五絕緣材料層640A上(或可首先將第五絕緣材料層640A貼合於子封裝單元M2的底部,且然後,可將子封裝單元M2貼合於子封裝單元M1上以使第五絕緣材料層640A接觸子封裝單元M1)。在此種情形中,在貼合製程中,可將壓力施加至第五絕緣材料層640A,且因此,第五絕緣材料層640A可具有相對於第一半導體晶片C1的所述一側或第一模具層160的所述一側而以凸的方式突出的形狀。
在圖19中,示例性地說明其中第五絕緣材料層640A具有以凸的方式突出的形狀的實例,但第五絕緣材料層640A可藉由毛細底部填充製程以環氧樹脂來形成而非藉由貼合非導電膜來形成。在此種情形中,第五絕緣材料層640A可具有在向下方向上膨脹的形狀以使第五絕緣材料層640A的下部寬度寬於第五絕緣材料層640A的上部寬度。
圖20是說明根據示例性實施例的半導體封裝100C的剖視圖。在圖20中,圖1至圖19中所示相同的參考編號指代相同的元件。除形成第五絕緣材料層640及底部填充材料層630的製程以外,半導體封裝100C可與以上參照圖1至圖13所述的半導體封裝100實質上相同。
參照圖20,可在插入器610上貼合子封裝單元M1,且可在子封裝單元M1上貼合子封裝單元M2。接著,可在形成第二模具層660的製程中在插入器610與子封裝單元M1之間的空間中形成底部填充材料層630A,且可在子封裝單元M1與子封裝單元M2之間的空間中形成底部填充材料層640B。在示例性實施例中,底部填充材料層630A及640B可為藉由模製底部填充(molded under-fill,MUF)製程而形成的第二模具層660的一部分。
圖21是說明根據示例性實施例的半導體封裝100D的剖視圖。在圖21中,圖1至圖20中所示相同的參考編號指代相同的元件。
參照圖21,插入器610的一部分上可堆疊有子封裝單元
M1及M2,且插入器610的另一部分上可堆疊有主半導體晶片800。
主半導體晶片800可為例如處理器單元。主半導體晶片800可為例如微處理單元(micro process unit,MPU)或圖形處理器單元(graphic processor unit,GPU)。在一些實施例中,主半導體晶片800可為已被驗證能夠正常運作的封裝(例如,已知良好封裝)。
主半導體晶片800的底部上可貼合有主連接端子810。主半導體晶片800可藉由主連接端子810而電性連接至插入器610。主半導體晶片800與插入器610之間可更形成有環繞主連接端子810的底部填充材料層820。底部填充材料層820可包含例如環氧樹脂。在一些實施例中,底部填充材料層820可為藉由模製底部填充製程而形成的第二模具層660的一部分。
在圖21中,揭露其中在插入器610的一部分上堆疊有兩個子封裝單元M1及M2的結構,但垂直地堆疊的子封裝單元M1及M2的數目並非僅限於此。舉例而言,可垂直地堆疊有三個或四個子封裝單元M1及M2。此外,在插入器610的另一部分上可另外安置有由垂直地堆疊的子封裝單元M1及M2構成的堆疊結構。舉例而言,與圖21中所示例性地說明者不同,主半導體晶片800可安置於插入器610的中心中,且可在主半導體晶片800附近提供多個其中堆疊有子封裝單元M1及M2的結構且所述多個結構可彼此間隔開(例如,可以為90度等的特定角度進行安置)。
此外,在圖21中,將第二模具層660示例性地說明為被
形成至主半導體晶片800的整個高度或大於所述整個高度以覆蓋主半導體晶片800的整個頂部及整個側,但本發明概念的技術精神並非僅限於此。與圖21中所示例性地說明者不同,第二模具層660可被形成為僅覆蓋主半導體晶片800的一側的一部分(例如,覆蓋至相對於主半導體晶片800的底部而言的某一高度),或可被形成為整體地覆蓋主半導體晶片800(如圖所示)與包括子封裝單元M1及M2的已完工的封裝單元二者的頂部。
在其他實施例中,主半導體晶片800可包括基板穿孔(圖中未示出),且子封裝單元M1及M2的堆疊結構可安置於主半導體晶片800上。在此種情形中,第一半導體晶片C1至第五半導體晶片C5的第一基板穿孔130、第二基板穿孔230、第三基板穿孔330、第四基板穿孔430及第五基板穿孔530(參見圖10)可電性連接至與第一半導體晶片C1至第五半導體晶片C5的第一基板穿孔130、第二基板穿孔230、第三基板穿孔330、第四基板穿孔430及第五基板穿孔530對應的主半導體晶片800的基板穿孔,且第一半導體晶片C1至第五半導體晶片C5可藉由主連接端子810而電性連接至插入器610及/或印刷電路板710。
儘管已參照本發明概念的實施例具體示出並闡述了本發明概念的各種態樣,然而應理解,在不背離以下申請專利範圍的精神及範圍的條件下,可作出各種形式及細節上的改變。
100:半導體封裝
130:第一基板穿孔
142:第一絕緣材料層
144:第二絕緣材料層
146:第三絕緣材料層
148:第四絕緣材料層
160:第一模具層
230:第二基板穿孔
330:第三基板穿孔
430:第四基板穿孔
514:第二表面
530:第五基板穿孔
536:後保護層
538:第五上部連接墊
610:插入器
612、720:基板基底
614:頂部墊
616:底部墊
630、730:底部填充層
640:第五絕緣材料層
650:絕緣構件
660:第二模具層
670:插入器連接端子
710:印刷電路板
740:外部連接端子
C1:第一半導體晶片
C2:第二半導體晶片
C3:第三半導體晶片
C4:第四半導體晶片
C5:第五半導體晶片
M1:子封裝單元
M2:子封裝單元
Claims (22)
- 一種製造半導體封裝的方法,包括:提供第一子封裝單元,所述第一子封裝單元包括至少兩個第一半導體晶片以及第三半導體晶片,所述至少兩個第一半導體晶片垂直地堆疊且包括所述第一子封裝單元的最頂部半導體晶片,所述第三半導體晶片配置在所述至少兩個第一半導體晶片下方,提供第一模具層,所述第一模具層環繞所述至少兩個第一半導體晶片的側表面;提供第二子封裝單元,所述第二子封裝單元包括至少兩個第二半導體晶片以及第四半導體晶片,所述至少兩個第二半導體晶片垂直地堆疊且包括所述第二子封裝單元的最頂部半導體晶片,所述第四半導體晶片配置在所述至少兩個第二半導體晶片下方;以及提供第二模具層,所述第二模具層環繞所述至少兩個第二半導體晶片的側表面且與所述第一模具層垂直地間隔開,將所述第二子封裝單元堆疊於所述第一子封裝單元上,其中所述至少兩個第一半導體晶片及所述至少兩個第二半導體晶片各自包括基板穿孔(TSV),且其中在將所述第二子封裝單元堆疊於所述第一子封裝單元上之後,將所述第一子封裝單元的所述最頂部半導體晶片電性連接至所述第二子封裝單元的最底部半導體晶片且所述第一子封裝單元的所述最頂部半導體晶片與所述第二子封裝單元的所述最底部 半導體晶片之間不存在封裝基板;以及提供封裝基板,所述至少兩個第一半導體晶片、所述至少兩個第二半導體晶片、所述第三半導體晶片與所述第四半導體晶片在所述封裝基板上垂直地堆疊以形成半導體封裝;且在將所述第二子封裝單元堆疊於所述第一子封裝單元上之前,測試所述第一子封裝單元及所述第二子封裝單元中的每一者。
- 如申請專利範圍第1項所述的製造半導體封裝的方法,更包括:在所述第二子封裝單元的所述最頂部半導體晶片的頂表面上提供上部連接墊,且所述上部連接墊電性連接至所述第二子封裝單元的所述最頂部半導體晶片的所述基板穿孔。
- 如申請專利範圍第1項所述的製造半導體封裝的方法,更包括:於所述第二子封裝單元的所述最頂部半導體晶片的頂表面上提供絕緣構件。
- 如申請專利範圍第1項所述的製造半導體封裝的方法,更包括:在所述第一子封裝單元的所述至少兩個第一半導體晶片之間提供第一底部填充構件,以及在所述第二子封裝單元的所述至少兩個第二半導體晶片之間提供第二底部填充構件。
- 如申請專利範圍第4項所述的製造半導體封裝的方法, 更包括:在所述第一子封裝單元與所述第二子封裝單元之間提供第三底部填充構件,所述第三底部填充構件接觸所述第一模具層的頂表面及/或所述第二模具層的底表面。
- 如申請專利範圍第5項所述的製造半導體封裝的方法,其中所述第三底部填充構件的一部分安置於所述第一模具層與所述第二模具層之間。
- 如申請專利範圍第5項所述的製造半導體封裝的方法,其中所述第三底部填充構件具有較所述第一底部填充構件或所述第二底部填充構件的水平橫截面積大的水平橫截面積。
- 如申請專利範圍第1項所述的製造半導體封裝的方法,其中所述至少兩個第一半導體晶片具有相同的水平橫截面積,及/或所述至少兩個第二半導體晶片具有相同的水平橫截面積。
- 如申請專利範圍第1項所述的製造半導體封裝的方法,其中所述第三半導體晶片具有較所述至少兩個第一半導體晶片中的每一者的水平橫截面積大的水平橫截面積,且所述第一模具層安置於所述第三半導體晶片的頂表面的一部分上;且其中所述第四半導體晶片具有較所述至少兩個第二半導體晶片中的每一者的水平橫截面積大的水平橫截面積,且所述第二模具層安置於所述第四半導體晶片的頂表面的一部分上。
- 如申請專利範圍第1項所述的製造半導體封裝的方法,更包括: 提供第三模具層,所述第三模具層環繞所述第一子封裝單元的側表面及所述第二子封裝單元的側表面,其中所述第三模具層環繞所述第一模具層的側表面及所述第二模具層的側表面。
- 如申請專利範圍第10項所述的製造半導體封裝的方法,更包括:在所述第一子封裝單元與所述第二子封裝單元之間提供第一底部填充構件,其中所述第三模具層環繞所述第一底部填充構件的側表面。
- 如申請專利範圍第1項所述的製造半導體封裝的方法,更包括:在將所述第二子封裝單元堆疊於所述第一子封裝單元上之前,使用所述第一子封裝單元的所述最頂部半導體晶片的所述基板穿孔測試所述第一子封裝單元及使用所述第二子封裝單元的所述最頂部半導體晶片的所述基板穿孔測試所述第二子封裝單元。
- 如申請專利範圍第1項所述的製造半導體封裝的方法,更包括:在已形成所述第一子封裝單元及所述第二子封裝單元中的每一者之後,藉由利用焊料凸塊將所述第一子封裝單元的頂部連接端子連接至所述第二子封裝單元的底部連接端子而將所述第一子封裝單元貼合至所述第二子封裝單元,所述焊料凸塊分別直接連接至所述頂部連接端子及所述底部連接端子中的每一者。
- 一種製造半導體封裝的方法,所述製造半導體封裝的方法包括:提供封裝基板;藉由首先將第一子封裝單元堆疊於所述封裝基板上且接著將第二子封裝單元堆疊於所述第一子封裝單元上而沿與所述封裝基板的頂表面垂直的方向將多個子封裝單元堆疊於所述封裝基板上,其中所述多個子封裝單元中的每一者包括:第一緩衝器晶片或邏輯晶片;第一記憶體晶片,安置於所述第一緩衝器晶片或所述邏輯晶片上;第二記憶體晶片,安置於所述第一記憶體晶片上;以及第一模具層,在所述多個子封裝單元的每一者中,所述第一模具層環繞所述第一記憶體晶片及所述第二記憶體晶片中的每一者的側表面,其中所述第一緩衝器晶片、所述第一記憶體晶片、及所述第二記憶體晶片中的每一者包括基板穿孔(TSV);以及執行回流製程,以將所述第一子封裝單元直接電性連接至所述第二子封裝單元。
- 如申請專利範圍第14項所述的製造半導體封裝的方法,其中在所述多個子封裝單元中的每一者中,所述第一模具層接觸所述第一緩衝器晶片的頂表面且不安置於所述第一緩衝器晶 片的側表面上。
- 如申請專利範圍第14項所述的製造半導體封裝的方法,更包括:形成第二模具層,所述第二模具層環繞所述多個子封裝單元的側表面且接觸所述第一緩衝器晶片中的每一者的所述側表面。
- 如申請專利範圍第14項所述的製造半導體封裝的方法,更包括:在所述多個子封裝單元中安置於最上部的子封裝單元的頂表面上形成絕緣構件;以及在所述多個子封裝單元中安置於所述最上部的所述子封裝單元的所述第二記憶體晶片上形成上部連接墊,且所述上部連接墊電性連接至所述第二記憶體晶片的所述基板穿孔,其中所述絕緣構件覆蓋所述上部連接墊。
- 如申請專利範圍第14項所述的製造半導體封裝的方法,其中在所述多個子封裝單元中的每一者中:所述第一緩衝器晶片不包括重佈線配線層,所述第一緩衝器晶片的所述基板穿孔與所述第一記憶體晶片的所述基板穿孔對齊,且所述第一記憶體晶片的所述基板穿孔與所述第二記憶體晶片的所述基板穿孔對齊。
- 一種製造半導體封裝的方法,所述製造半導體封裝的方法包括: 形成至少兩個局部封裝晶片堆疊,所述局部封裝晶片堆疊中的每一者包括至少兩個半導體晶片且包括第一模具層,所述至少兩個半導體晶片各自包括多個基板穿孔(TSV),其中,對於所述局部封裝晶片堆疊中的每一者,所述至少兩個半導體晶片中的一個是所述局部封裝晶片堆疊中的最頂部半導體晶片,所述第一模具層環繞所述至少兩個半導體晶片的側表面;在與封裝基板的頂表面垂直的方向上將所述至少兩個局部封裝晶片堆疊依序安裝於所述封裝基板上,使得所述至少兩個局部封裝晶片堆疊包括第一局部封裝晶片堆疊及直接連接至所述第一局部封裝晶片堆疊的第二局部封裝晶片堆疊,其中,所述至少兩個局部封裝晶片堆疊中的一個包括所述半導體封裝的最頂部半導體晶片;且在將所述至少兩個局部封裝晶片堆疊依序安裝於所述封裝基板上之前,通過所述半導體封裝的所述最頂部半導體晶片的多個基板穿孔測試至少包括所述半導體封裝的所述最頂部半導體晶片的局部封裝晶片堆疊。
- 如申請專利範圍第19項所述的製造半導體封裝的方法,其中所述形成所述至少兩個局部封裝晶片堆疊包括:在所述局部封裝晶片堆疊中的每一者中,將所述至少兩個半導體晶片中的一者堆疊於所述至少兩個半導體晶片中的另一者上,所述至少兩個半導體晶片中的所述一者與所述至少兩個半導體晶片中的所述另 一者之間具有第一底部填充構件,所述安裝所述至少兩個局部封裝晶片堆疊包括將所述至少兩個局部封裝晶片堆疊中的一者堆疊於所述至少兩個局部封裝晶片堆疊中的另一者上,所述至少兩個局部封裝晶片堆疊中的所述一者與所述至少兩個局部封裝晶片堆疊中的所述另一者之間具有第二底部填充構件,且所述第二底部填充構件的水平橫截面積大於所述第一底部填充構件的水平橫截面積。
- 如申請專利範圍第20項所述的製造半導體封裝的方法,其中所述第二底部填充構件的一部分安置於所述至少兩個局部封裝晶片堆疊的所述第一模具層之間。
- 如申請專利範圍第19項所述的製造半導體封裝的方法,其中所述測試是在所述至少兩個局部封裝晶片堆疊於載體基板上並相對於彼此水平設置的情況下進行。
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