CN111799228A - 形成管芯堆叠件的方法及集成电路结构 - Google Patents

形成管芯堆叠件的方法及集成电路结构 Download PDF

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CN111799228A
CN111799228A CN202010250523.7A CN202010250523A CN111799228A CN 111799228 A CN111799228 A CN 111799228A CN 202010250523 A CN202010250523 A CN 202010250523A CN 111799228 A CN111799228 A CN 111799228A
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forming
die
redistribution
memory die
over
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CN111799228B (zh
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余振华
蔡仲豪
王垂堂
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Abstract

方法包括减薄器件管芯的半导体衬底，以露出延伸至半导体衬底中的衬底通孔；以及形成第一再分布结构，形成第一再分布结构包括在半导体衬底上方形成第一多个介电层，以及在第一多个介电层中形成第一多个再分布线。第一多个再分布线电连接至衬底通孔。该方法还包括将第一存储器管芯放置在第一再分布结构上方，以及在第一再分布结构上方形成第一多个金属柱。第一多个金属柱电连接至第一多个再分布线。将第一存储器管芯密封在第一密封剂中。在第一多个金属柱和第一存储器管芯上方形成电连接至第一多个金属柱和第一存储器管芯的第二多个再分布线。本发明的实施例还涉及形成管芯堆叠件的方法及集成电路结构。

Description

形成管芯堆叠件的方法及集成电路结构
技术领域
本发明的实施涉及形成管芯堆叠件的方法及集成电路结构。
背景技术
高性能计算(HPC)系统通常包括接合至逻辑管芯的高带宽存储器(HBM)堆叠件。HBM堆叠件通常包括堆叠在一起的多个存储器管芯，其中，上存储器管芯通过焊料接合或通过微凸块的金属直接接合而接合至下存储器管芯。在存储器管芯中形成硅通孔(TSV)，使得上管芯可以通过TSV电连接至逻辑管芯。
发明内容
根据本发明的实施例提供一种形成管芯堆叠件的方法，该方法包括形成存储器管芯堆叠件。所述形成存储器管芯堆叠件包括：将第一存储器管芯放置在下介电层上；在所述下介电层上方形成第一多个金属柱；将所述第一存储器管芯密封在第一密封剂中；形成第一再分布结构，所述形成第一再分布结构包括在所述第一密封剂上方形成第一多个介电层，以及在所述第一多个介电层中形成第一多个再分布线，其中，所述第一多个再分布线电连接至所述第一多个金属柱和所述第一存储器管芯；将第二存储器管芯放置在所述第一再分布结构上方；在所述第一再分布结构上方形成第二多个金属柱，其中，所述第二多个金属柱电连接至所述第一多个金属柱；将所述第二存储器管芯密封在第二密封剂中；形成第二再分布结构，所述形成第二再分布结构包括在所述第二密封剂上方形成第二多个介电层，以及在所述第二多个介电层中形成第二多个再分布线，其中，所述第二多个再分布线电连接至所述第二多个金属柱和所述第二存储器管芯。
本发明的又一实施例提供一种形成管芯堆叠件的方法，包括：减薄器件管芯的半导体衬底，以露出延伸至半导体衬底中的衬底通孔；形成第一再分布结构，所述形成第一再分布结构包括在所述半导体衬底上方形成第一多个介电层，以及在所述第一多个介电层中形成第一多个再分布线，其中，所述第一多个再分布线电连接至所述衬底通孔；将第一存储器管芯放置在所述第一再分布结构上方；在所述第一再分布结构上方形成第一多个金属柱，其中，所述第一多个金属柱电连接至所述第一多个再分布线；将所述第一存储器管芯密封在第一密封剂中；以及在所述第一多个金属柱和所述第一存储器管芯上方形成电连接至所述第一多个金属柱和所述第一存储器管芯的第二多个再分布线。
本发明的再一实施例提供一种集成电路结构，包括：器件管芯，器件管芯包括半导体衬底，多个衬底通孔，穿透所述半导体衬底，以及互连结构，互连结构位于所述半导体衬底的侧上；第一再分布结构，第一再分布结构位于所述器件管芯上方并且包括第一多个介电层，以及第一多个再分布线，第一多个再分布线位于所述第一多个介电层中，其中，所述第一多个再分布线电连接至所述器件管芯；第一存储器管芯，第一存储器管芯位于所述第一再分布结构上方；第一多个金属柱，第一多个金属柱位于所述第一再分布结构上方，其中，所述第一多个金属柱电连接至所述第一多个再分布线；第一密封剂，所述第一密封剂中密封所述第一存储器管芯和所述第一多个金属柱；以及第二多个再分布线，位于所述第一密封剂上方并且电连接至所述第一多个金属柱。
附图说明
当结合附图进行阅读时，从以下详细描述可最佳理解本发明的各个方面。应该指出，根据工业中的标准实践，各个部件未按比例绘制。实际上，为了清楚的讨论，各个部件的尺寸可以任意地增大或减小。
图1至图8示出了根据一些实施例的附接至逻辑管芯的前侧的存储器管芯堆叠件的形成中的中间阶段的截面图。
图9、图10、图11A和图11B示出了根据一些实施例的管芯堆叠件的截面图。
图12至图18示出了根据一些实施例的附接至逻辑管芯的背侧的存储器管芯堆叠件的形成中的中间阶段的截面图。
图19至图25示出了根据一些实施例的附接至逻辑管芯的背侧的存储器管芯堆叠件的形成中的中间阶段的截面图。
图26和图27示出了根据一些实施例的在形成至硅通孔(TSV)的连接件之前和之后的示例性逻辑管芯的截面图。
图28示出了根据一些实施例的示例性存储器管芯的截面图。
图29至图32示出了根据一些实施例的图8中的结构的一部分的一些细节。
图33示出了根据一些实施例的用于形成管芯堆叠件的工艺流程。
具体实施方式
以下公开内容提供了许多用于实现本发明的不同特征的不同实施例或实例。下面描述了部件和布置的具体实例以简化本发明。当然，这些仅仅是实例，而不旨在限制本发明。例如，以下描述中，在第二部件上方或者上形成第一部件可以包括第一部件和第二部件直接接触形成的实施例，并且也可以包括在第一部件和第二部件之间可以形成额外的部件，从而使得第一部件和第二部件可以不直接接触的实施例。此外，本发明可在各个实施例中重复参考标号和/或字符。该重复是为了简单和清楚的目的，并且其本身不指示所讨论的各个实施例和/或配置之间的关系。
而且，为便于描述，在此可以使用诸如“在…之下”、“在…下方”、“下部”、“在…之上”、“上部”等空间相对术语，以描述如图所示的一个元件或部件与另一个(或另一些)元件或部件的关系。除了图中所示的方位外，空间相对术语旨在包括器件在使用或操作中的不同方位。装置可以以其它方式定向(旋转90度或在其它方位上)，而本文使用的空间相对描述符可以同样地作出相应的解释。
根据各个实施例提供了包括存储器管芯的管芯堆叠件及其形成方法。根据一些实施例示出了管芯堆叠件的形成中的中间阶段。讨论了一些实施例的一些变型。贯穿各个视图和示例性实施例，相同的参考标号用于表示相同的元件。根据本发明的一些实施例，管芯堆叠件包括接合至诸如逻辑管芯的器件管芯的存储器管芯堆叠件。在密封剂(诸如模塑料)中形成介电通孔(而不是在存储器管芯中形成硅通孔)以密封存储器管芯，并且TSV用于将存储器管芯连接至逻辑管芯。如果在存储器管芯的半导体衬底中形成TSV，则由于TSV和半导体衬底之间的寄生电容，将导致半导体衬底对TSV产生不利负载。根据本发明的一些实施例，由于在介电密封剂中形成介电通孔，因此没有负载。由于负载可能导致信号衰减，因此通过形成介电通孔，避免了信号衰减。
应当理解，将参照特定上下文来描述实施例，即，包括接合至器件管芯的存储器管芯的管芯堆叠件。所讨论的实施例的概念还可以应用于其它结构的结构和工艺，包括但不限于逻辑管芯堆叠件、IO管芯堆叠件或具有混合逻辑管芯、IO管芯、存储器管芯等的管芯堆叠件的形成。本文讨论的实施例是提供能够制成或使用本发明主题的实例，并且本领域普通技术人员将容易理解，可以作出的修改仍保持在不同实施例的预期范围内。以下附图中相同的参考标号和字符表示相同的部件。虽然可以将方法实施例讨论为以特定顺序实施，但是可以以任何逻辑顺序实施其它方法实施例。
图1至图8示出了根据本发明的一些实施例的管芯堆叠件的形成中的中间阶段的截面图。相应的工艺也示意性地反映在图33中所示的工艺流程300中。
参照图1，提供载体30，并且在载体30上形成释放膜32。载体30由透明材料形成，并且可以是玻璃载体、陶瓷载体、有机载体等。载体30可以具有俯视时呈圆形的形状，并且可以具有硅晶圆的尺寸。释放膜32形成在载体30上方，并且可以由光热转换(LTHC)涂层材料形成。可以通过涂覆将释放膜32施加到载体30上。根据本发明的一些实施例，由于释放膜32能够在光/辐射(诸如激光束)的热量下分解，并且因此能够从形成在其上的结构释放载体30。
器件晶圆20放置在释放膜32上方。相应的工艺示出为图33中所示的工艺流程中的工艺302。根据一些实施例，器件晶圆20可以是包括多个逻辑管芯20’的逻辑晶圆。因此，器件晶圆20也称为逻辑晶圆，并且器件管芯20’在下文中也称为逻辑管芯。根据可选实施例，器件晶圆20是另一类型的晶圆，诸如输入-输出晶圆、中介层晶圆等。根据本发明的一些示例性实施例，器件管芯20’是中央处理单元(CPU)管芯、图形处理单元(GPU)管芯、移动应用管芯、微控制单元(MCU)管芯、基带(BB)管芯、应用处理器(AP)管芯等。器件管芯20’包括半导体衬底22和形成在半导体衬底22上的互连结构24。
图1中示意性地示出了互连结构24，并且根据一些实例在图26中示出了一些细节。参照图26，器件晶圆20包括衬底22。根据一些实施例，衬底22是半导体衬底，其可以包括或可以是晶体硅衬底，但是它可以包括其它半导体材料，诸如硅锗、硅碳等。根据一些实施例，器件管芯20’包括有源电路220，其包括形成在半导体衬底22的顶面处的诸如晶体管(未示出)的有源器件。根据晶圆20是中介层晶圆的一些实施例，晶圆20的顶面处没有电路。通孔(有时称为衬底通孔(TSV))26可以形成为延伸至衬底22中。当TSV 26形成在硅衬底中时，有时也将TSV 26称为硅通孔。每个TSV 26均可以由隔离衬垫28环绕，隔离衬垫28由诸如氧化硅、氮化硅等的介电材料形成。隔离衬垫28将相应的TSV 26与半导体衬底22隔离。TSV 26和隔离衬垫28从半导体衬底22的顶面延伸至半导体衬底22的顶面和底面之间的中间水平。
互连结构24形成在半导体衬底22上方。互连结构24可以包括多个介电层224。金属线228和通孔226形成在介电层224中，并且电连接至TSV26和电路220。根据一些实施例，介电层224由氧化硅、氮化硅、碳化硅、氮氧化硅、它们的组合和/或它们的多层形成。介电层224可以包括由具有低k值的低k介电材料形成的一个或多个金属间介电(IMD)层，低k值可以例如低于约3.0，或在约2.5和约3.0之间的范围内。
在器件管芯20’的顶面处形成电连接件230。根据一些实施例，电连接件230包括金属柱、金属焊盘、金属凸块(有时称为微凸块)等。电连接件230的材料可以包括非焊料材料，其可以包括并且可以是铜、镍、铝、金、它们的多层、它们的合金等。电连接件230可以通过一些其它导电部件(未示出)以及金属线228和通孔226电连接至集成电路220，一些其它导电部件包括但不限于铝焊盘、后钝化互连(PPI)等。再者，在电连接件230和金属线228之间，可以存在诸如低k介电层的介电层、钝化(非低k)层、聚合物层等。电连接件230可以密封在介电层232中。根据本发明的一些实施例，介电层232是由例如聚苯并恶唑(PBO)、聚酰亚胺、苯并环丁烯(BCB)等形成的聚合物层。
根据一些实施例，也如图26所示，可以形成突出在器件管芯20’(晶圆20)的其余部分之上的金属柱38，而不是具有作为器件管芯20’的顶部导电部件的电连接件230。金属柱38以虚线示出，因此表示它们可以在该阶段形成，或在图3所示的步骤中形成。根据一些实施例，未形成介电层232，并且金属柱38直接形成在金属焊盘233上。当采用这些实施例时，跳过如图3所示的形成金属柱38的工艺。
在整个说明书中，具有有源电路220的半导体衬底22和互连结构24的侧称为半导体衬底22的前侧(或有源侧)，而相对侧称为半导体衬底22的背侧(或无源侧)。同样，半导体衬底22的前侧也称为器件管芯20’(和晶圆20)的前侧(或有源侧)，并且半导体衬底22的背侧也称为器件管芯20’(晶圆20)的背侧(或无源侧)。
回参照图1，晶圆20放置为前侧朝向载体30。未示出互连结构24的细节，并且可以参照图26找到。下一步，如图2所示，在例如化学机械抛光(CMP)工艺或机械抛光工艺中减薄衬底22。因此，暴露TSV 26。相应的工艺示出为图33中所示的工艺流程中的工艺304。
图3示出了再分布结构41(41A)的形成，其包括介电层34(包括34A和34B)和再分布线(RDL)36。相应的工艺示出为图33中所示的工艺流程中的工艺306。根据一些实施例，介电层34由诸如PBO、聚酰亚胺等的聚合物形成。形成方法包括以可流动的形式涂覆介电层34，并且然后固化相应的介电层。根据本发明的可选实施例，介电层34由无机介电材料形成，无机介电材料诸如氮化硅、氧化硅、碳化硅、它们的多层、它们的组合等。形成方法可以包括涂覆、化学汽相沉积(CVD)、原子层沉积(ALD)、等离子体增强化学汽相沉积(PECVD)或其它适用的沉积方法。介电层34可以包括介电层34A和34B，并且可以形成更多的介电层，这取决于布线要求。
RDL 36形成为具有延伸至介电层34A中的通孔部分，以及位于介电层34A上方的迹线部分。形成工艺可以包括图案化介电层34A以形成开口，其中，TSV 26通过该开口暴露，形成毯式金属晶种层(未示出)，形成并且图案化镀掩模(诸如光刻胶)以露出金属晶种层的一些部分，在镀掩模的开口中镀RDL 36，去除镀掩模，以及蚀刻金属晶种层的先前由镀掩模覆盖的部分。根据本发明的一些实施例，金属晶种层包括钛层和位于钛层上方的铜层。金属晶种层的形成可以包括例如PVD。根据本发明的一些实施例，镀材料包括铜或铜合金。镀可以包括电化学镀或化学镀。在整个说明书中，介电层34和其中形成的RDL 36组合称为再分布结构41。
虽然示出了一层RDL 36，但是可以形成多层的RDL。然后形成金属柱38。相应的工艺示出为图33中所示的工艺流程中的工艺308。根据一些实施例，形成工艺包括图案化介电层34B以形成开口，其中，RDL 36的一些焊盘部分通过该开口暴露，形成毯式金属晶种层(未示出)，形成并且图案化另一镀掩模(诸如光刻胶)以露出金属晶种层的一些部分，在镀掩模的开口中镀金属柱38，去除镀掩模，以及蚀刻金属晶种层的先前由镀掩模覆盖的部分以形成金属柱38。通孔40也以与形成金属柱38相同的工艺形成，并延伸至介电层34B中。
图4示出了第一层存储器管芯42的放置。相应的工艺示出为图33中所示的工艺流程中的工艺310。存储器管芯42可以通过管芯附接膜(DAF)44附接至介电层34，管芯附接膜(DAF)44是粘合膜。在将晶圆锯切为存储器管芯42之前，DAF 44可以预先附接在其中具有存储器管芯42的相应晶圆上。存储器管芯42可以包括具有与相应DAF 44物理接触的背面(该面朝下)的半导体衬底(240，图28)。由于载体30处于晶圆级，虽然两个存储器管芯42示出为一组，但是多个相同的存储器组放置在再分布结构41上方，其中，每个组均与一个器件管芯20’重叠。此外，该组中可能存在更多的存储器管芯，诸如4、6、8或更多。
图4中未示出存储器管芯42的细节，并且根据本发明的一些实施例，图28中示出了一些细节。除了存储器管芯42之外，图28还示出了一些其它部分，这将在随后的段落中讨论。存储器管芯42可以包括半导体衬底240、集成电路242，集成电路242可以包括诸如晶体管、二极管等的有源器件。不存在穿透半导体衬底240的通孔。存储器管芯42可以包括诸如动态随机存取存储器(DRAM)、静态随机存取存储器(SRAM)的存储器或其它类型的存储器。例如，图28示出了可以在DRAM中使用的一些堆叠电容器。还示出了顶部金属接触件(CTM)252和底部接触金属250。根据一些实施例，底部接触金属250用作位线，并且字线256可以嵌入在半导体衬底240内。互连结构244形成在衬底240上方，并且可以包括介电层、金属线、通孔等。介电层可以包括低k介电层和/或非低k介电层。根据一些实施例，如图28所示，互连结构244包括多个金属层，诸如M1、M2、M3和M4(或更多)。由非低k介电材料形成的钝化层246形成在互连结构244上方，非低k介电材料诸如未掺杂的硅酸盐玻璃、氧化硅、氮化硅或它们的多层。金属焊盘248(其可以是金属层M4的一部分)形成在互连结构244的金属线和通孔上方并且电连接至互连结构244的金属线和通孔。例如，金属焊盘248可以由铝铜形成。可以由铜、镍、钛等形成的电连接件48可以形成在金属焊盘248上方并且连接至金属焊盘248。可以由PBO、聚酰亚胺等形成的介电层46形成为密封电连接件48。
返回参照图4，存储器管芯42和金属柱38密封在密封剂50中。相应的工艺示出为图33中所示的工艺流程中的工艺312。密封剂50填充相邻金属柱38之间的间隙以及金属柱38和存储器管芯42之间的间隙。密封剂50可以包括模塑料、模塑底部填充物、环氧树脂和/或树脂。密封剂50的顶面高于电连接件48和金属柱38的顶端。当由模塑料形成时，密封剂50可以包括可以是聚合物、树脂、环氧树脂等的基材和基材中的填料颗粒。填料颗粒可以是SiO2、Al2O3、二氧化硅等的介电颗粒，并且可以具有球形形状。而且，球形填料颗粒可具有多个不同的直径。
在随后的步骤中，实施诸如CMP工艺或机械研磨工艺的平坦化工艺以减薄密封剂50和存储器管芯42，直到暴露金属柱38和电连接件48。由于平坦化工艺，金属柱38的顶端与电连接件48的顶面基本齐平(共面)，并且与密封剂50的顶面基本共面。金属柱38在随后的段落中可选地称为通孔38，因为它们穿透密封剂50。
图5示出了另一再分布结构41(41B)的形成，其包括RDL 36和介电层34。相应的工艺示出为图33中所示的工艺流程中的工艺314。为了区分不同层的再分布结构41，位于存储器管芯42下面的再分布结构41称为(第一层)再分布结构41A，并且位于存储器管芯42上面的再分布结构41称为(第二层)再分布结构41B。而且，示出的第一层存储器管芯42标识为存储器管芯42A，并且示出的通孔38可以标识为(第一层)通孔38A。
第二层再分布结构41B中的RDL 36电连接至通孔38A和存储器管芯42中的电连接件48。因此，通孔38A将存储器管芯42电连接至器件管芯20’。应当理解，RDL 36为示意性地示出，而RDL 36不将通孔38和电连接件48电短接在一起。相反地，不同的通孔38可以通过不同的RDL 36连接至不同的电连接件48。类似地，RDL 36不与电连接件48电短接在一起。
图6示出了更多层存储器管芯42(包括42B，42C和42D)、通孔38(包括38B，38C和38D)和再分布结构41(包括41C、41D和41E)等的形成/粘合。相应的工艺示出为图33中所示的工艺流程中的工艺316。参照图3至图5的讨论可以找到形成工艺和相应的材料，并且因此此处不再重复。存储器管芯42C和42D可以与存储器管芯42A和42B相同或不同。在最终结果中，所有存储器管芯42均电连接并且信号连接至相应的下面的器件管芯20’。在整个说明书中，位于释放膜32上方的部件的组合统称为重建晶圆54。
然后，例如通过将激光束投射到释放膜32上，从载体30卸下重建晶圆54。释放膜32在激光束的热量下分解。产生的重建晶圆54如图7所示。接下来，如图8所示，根据一些实施例，在器件管芯20’的互连结构24上形成再分布结构52。相应的工艺示出为图33中所示的工艺流程中的工艺318。根据可选实施例，跳过再分布结构52的形成。因此，使用虚线示出图33中的工艺318以指示其可以实施或不实施。在再分布结构52的形成之前，减薄覆盖电连接件230的介电层232(图26)，直至暴露电连接件230。未示出再分布结构52的细节。再分布结构52可以例如使用与用于形成再分布结构41的类似的工艺和材料形成。再分布结构52包括介电层和位于介电层中的再分布线。然后，电连接件55形成在再分布结构52上，并且通过再分布结构52电连接至器件管芯20’。相应的工艺示出为图33中所示的工艺流程中的工艺320。电连接件55可以包括金属柱、焊料区域、凸块下金属(UBM)等。
图27示出了根据一些实施例在再分布结构52和电连接件55的形成之后的器件管芯20’。未示出位于器件管芯20’上方的再分布结构和存储器管芯堆叠件。
返回参照图8，在管芯锯切工艺中切割重建晶圆54。相应的工艺示出为图33中所示的工艺流程中的工艺322。例如，刀片可以锯切穿过器件管芯20’之间的划线以将重建晶圆54分隔成多个相同的封装件54’，每个都具有根据一些实例示出的结构。然后可以将封装件54’接合至另一封装部件(未示出)，诸如中介层、封装衬底、印刷电路板等，其中，例如，在封装件54’和另一封装部件之间设置有底部填充物。
在图8中，通孔38示出为形成由所有层的存储器管芯42共享的共用信号通道。根据可选实施例，每个存储器管芯42均可以具有其专用信号通道，并且一些通孔38可以连接至一个或一些(但不是全部)层的存储器管芯42。
图28示出了根据一些实施例的图8中的区域91的放大视图。在放大视图中，存储器管芯42密封在密封剂50中，并且金属焊盘48的顶面与通孔38的顶面共面。再分布结构41形成在存储器管芯42和通孔38上方。虽然示出了RDL 36的一层，但是可以存在RDL 36的多个层(诸如两层、三层或更多层)。
图29至图32示出了根据本发明的一些实施例的图8中的区域92的放大视图。参照图29，DAF 44将存储器管芯42粘合至再分布结构41中的顶部介电层34。RDL 36具有接触金属焊盘48的顶面的通孔部分，金属焊盘48位于介电层46中。介电层46可以是聚合物层，其可以由聚酰亚胺、PBO等形成。金属焊盘248可以是含铝金属焊盘，根据一些实施例，其可以是铝铜焊盘。可选地，金属焊盘248可以由其它材料形成，其它材料诸如铜或铜合金。钝化层246可以由氧化硅、氮化硅、它们的多层或它们的组合形成。
图30示出了根据可选实施例的图8中的区域92的放大视图。这些实施例与图29中所示的实施例类似，除了顶部金属层(其是与包括金属焊盘48相同的金属层)也用于布线目的。换句话说，存在与金属焊盘48处于相同层级并且同时形成的金属线，其中示意性示出的金属线可以水平延伸以路由电信号。因此，金属焊盘48所在的金属层认为是存储器管芯42中的一个金属层(用于布线目的)。根据一些实施例，金属焊盘48和相应的通孔位于其上的金属焊盘248是铝焊盘或铝铜焊盘。
图31示出了根据可选实施例的图8中的区域92的放大视图。这些实施例与图29中所示的实施例类似，除了将两层的RDL36示出为实例之外。
图32示出了根据可选实施例的图8中的区域92的放大视图。这些实施例与图29中所示的实施例类似，除了没有在金属焊盘48正下面形成铝焊盘之外。而且，金属焊盘48的通孔部分位于顶部金属层(例如M3)中的铜焊盘上。
在图8所示的结构中，存储器管芯42在相应的半导体衬底中不包括衬底通孔。上层存储器管芯与器件管芯20’的电连接通过通孔38形成。由于通孔38形成在密封剂50中，密封剂50由介电材料形成，因此在通孔38和密封剂50之间(与TSV和半导体衬底之间不同)没有寄生电容，并且产生的封装件也没有可能存在于硅通孔中的负载。
图9、图10、图11A和图11B示出了根据可选实施例形成的封装件54’。除非另有说明，否则这些实施例(以及图12至图28中所示的实施例)中的部件的材料和形成工艺与图1至图8所示的实施例中相同的参考标号表示的相同的部件基本相同。因此，可以在图1至图8所示的实施例的讨论中找到关于图9至图28所示的部件的形成工艺和材料的细节。
在上述实施例中，通孔38形成在存储器管芯42之间，并且TSV 26形成在器件管芯20’的中间。因此，产生的结构不需要长水平RDL来将TSV26连接至通孔38。图9示出了与图8中所示的实施例类似的实施例，除了在每层中和在每个器件管芯20’上方均可以存在单个存储器管芯42，并且因此通孔38形成在存储器管芯42的相对侧上之外。根据一些实施例，如图所示，TSV 26形成在器件管芯20’的中间。根据可选实施例，TSV 26可以形成在区域57中，区域57靠近器件管芯20’的边缘，以减小再分布结构41A中的横向分布线的长度。
图10示出了与图8中所示的实施例类似的实施例，除了通孔38形成于存储器管芯42的相对侧上，而不是形成在存储器管芯42之间。根据一些实施例，TSV 26可以形成为靠近器件管芯20’的边缘。代替在每层中放置单个存储器管芯42，单个存储器管芯的功能可以分成两个存储器管芯，并且存储器管芯42可以靠近器件管芯20’的相对边缘放置，使得水平RDL36的长度可以缩短。当器件管芯20’的横向尺寸远大于存储器管芯42的横向尺寸时，可以应用这些实施例。类似地，TSV 26可以如图所示形成在器件管芯20’的中间，或可以形成在靠近器件管芯20’的边缘的区域57中，以减小再分布结构41A中的横向分布线36的长度。
图11A示出了与图8中所示的实施例类似的实施例，除了在每层中放置存储器封装件43而不是存储器管芯之外。存储器封装件43可以彼此相同或可以彼此不同。每个存储器封装件43均可以包括存储器管芯42’和存储器管芯42”，它们可以彼此相同，或彼此不同。存储器管芯42’和42”中的每个均可以密封在密封剂58中，密封剂58可以是例如模塑料。密封剂58还可以包括诸如环氧树脂、树脂、聚合物等基材以及基材中的填料颗粒。填料颗粒可以是球形的，并且可以具有不同的直径。可以与再分布结构41类似地形成的再分布结构41’形成在下面的存储器管芯42’和42”上方，并且电连接至下面的存储器管芯42’和42”。再分布结构41’还可以包括介电层和介电层中的RDL。通孔61可以形成在上密封剂58中，并且将存储器管芯42’电连接至再分布结构41中的RDL 36。
图11B示出了与图8中所示的实施例类似的实施例，除了存储器管芯42面朝下而不是面朝上之外。因此，诸如第三层和第四层管芯的一些存储器管芯42可以与将这些存储器管芯42连接至器件管芯20’的相应通孔38重叠。此外，每个接合焊盘48可以与不同层级处的多个通孔38重叠。一些存储器管芯(诸如第一层管芯和第二层管芯)的一些其它接合焊盘48仍可以连接至水平RDL36。
图12至图18示出了根据可选实施例的管芯堆叠件的形成中的中间阶段的截面图。这些实施例与图1至图10、图11A和图11B所示的实施例类似，除了存储器管芯附接至器件管芯的前侧(而不是背侧)之外。参照图12，提供了包括器件管芯20’的器件晶圆20。器件晶圆20的前侧示出为面朝上，其中，互连结构24位于半导体衬底22和TSV 26上方。如图26所示，图26示出了互连结构24的一些细节，在互连结构24中，电连接件230被介电层232覆盖。然后，实施平坦化工艺减薄介电层232，直至暴露电连接件230。
接下来，参照图13，形成第一层再分布结构41和金属柱38。形成工艺和材料与先前实施例中讨论的基本相同，并且此处不再重复。一些再分布线36可以与图26所示的一些电连接件230物理接触。
图14示出了第一层存储器管芯42的放置，以及存储器管芯42和金属柱38在密封剂50中的密封。然后对密封剂50实施平坦化工艺以露出金属柱38和电连接件48。接下来，如图15所示，形成第二层再分布结构41。在随后的工艺中，形成更多层的金属柱38、密封剂50和再分布结构41，并且产生的结构如图16所示，该结构在下文中称为重建晶圆54。
参照图17，图17示出了与图16相比上下倒置的重建晶圆54，实施诸如CMP工艺或机械研磨工艺的平坦化工艺，直至暴露TSV 26。接下来，如图18所示，在器件管芯20’的半导体衬底22上形成再分布结构52’。例如，可以使用与用于形成再分布结构41类似的工艺和材料来形成再分布结构52’。再分布结构52’可以包括介电层53A和53B，以及位于介电层53A和53B中的再分布线59。根据本发明的一些实施例，介电层53A和53B由诸如PBO或聚酰亚胺的聚合物形成。介电层53A可以与半导体衬底22以及可能的TSV 26物理接触。然后，电连接件55形成在再分布结构52’上方，并且通过再分布线59电连接至器件管芯20’。电连接件55可以包括金属柱、焊料区域、凸块下金属(UBM)等。在随后的工艺中，在切割工艺中将重建晶圆54锯切成离散的封装件54’，然后可以将离散的封装件54’接合至诸如中介层、封装衬底、印刷电路板等的附加封装部件，其中，在封装件54’和附加封装部件之间设置有底部填充物。
图19至图25示出了根据可选实施例的存储器管芯堆叠件和相应封装件的形成中的中间阶段的截面图。这些实施例与图1至图18所示的实施例类似，除了首先形成存储器管芯堆叠件，并且然后通过接合工艺接合至逻辑管芯，而不是直接从逻辑管芯/晶圆形成存储器管芯堆叠件。
参照图19，提供载体60，其上形成有释放膜62。逐层形成包括存储器管芯42、金属柱38、密封剂50和再分布结构41的存储器管芯堆叠件66。存储器管芯堆叠件66还可以包括缓冲电介质39，其可以由例如PBO或聚酰亚胺形成，或包括例如PBO或聚酰亚胺。存储器管芯堆叠件66的形成工艺和材料与参照图1至图8中所示的实施例讨论的那些类似，并且此处不再重复。应当理解，在第一层密封剂50中，没有形成通孔38。接下来，参照图20，电连接件64形成为电连接至RDL 36和通孔38。电连接件64可以包括金属柱、金属焊盘、焊料区域等。因此形成重建晶圆66。在随后的工艺中，重建晶圆66从载体60脱粘，以及随后的切割工艺以将重建晶圆66锯切成多个存储器堆叠件66’。
图21至图25示出了存储器堆叠件66’与器件晶圆20(和器件管芯20’)的接合。参照图21，器件晶圆20通过释放膜72放置在载体70上。器件晶圆20的前侧朝下，并且因此互连结构24位于半导体衬底22和载体70之间。根据一些实施例，焊料区域74(有时称为预焊料区域)预形成在中介层晶圆20上，并且可以形成在介电层76中，介电层76可以由诸如PBO、聚酰亚胺等聚合物形成或包括聚合物。焊料区域74可以形成在如图26所示的电连接件230上，并且可能接触电连接件230。可选地，焊料区域74可以代替如图26所示的电连接件230。
接下来，如图22所示，对半导体衬底22实施诸如CMP工艺或机械研磨工艺的平坦化工艺以露出TSV 26。然后切割器件晶圆20以形成器件管芯20’，其中，图23示出了一个器件管芯20’。图23还示出了器件管芯20’通过焊料区域74接合在中介层晶圆78上。根据一些实施例，中介层晶圆78具有与如图26所示的器件晶圆20类似的结构，除了中介层晶圆78不包括诸如其中的有源器件的集成电路220之外。中介层晶圆78中可以包括或可以没有诸如电阻器、电容器、电感器等的无源器件。TSV 82形成为延伸至半导体衬底81内，半导体衬底81可以是诸如硅衬底的半导体衬底。绝缘衬垫83环绕TSV 82。中介层晶圆78可以在其正面处包括互连结构80。互连结构80的结构未示出，并且可以与图26中所示的互连结构24类似。根据本发明的一些实施例，中介层晶圆78的前侧(具有互连结构80的侧)朝上，如图23所示。根据本发明的可选实施例，中介层晶圆78的前侧朝下，并且焊料区域74可以直接接合至TSV82，TSV 82通过抛光中介层晶圆78中的衬底81暴露。底部填充物84设置在器件管芯20’和中介层晶圆78之间。虽然示出了一个器件管芯20’，但是多个器件管芯20’放置在中介层晶圆78上，例如，多个器件管芯20’的每个均与中介层晶圆78中的一个中介层管芯重叠。
图24示出了多个存储器堆叠件66’的接合，每个存储器堆叠件66’均位于一个器件管芯20’上。底部填充物84’设置在存储器堆叠件66’和器件管芯20’之间。密封剂86(例如，模塑料、环氧树脂等)密封在存储器堆叠件66’和器件管芯20’上以形成重建晶圆88。密封剂86还可以包括基材和基材中的球形填料。
在随后的工艺中，抛光中介层晶圆78以减薄半导体衬底81，露出TSV82。可以在TSV82上形成焊料区域90(图25)。可选地，可以形成另一再分布结构以将焊料区域90连接至TSV82。然后可以锯切重建晶圆88以形成多个封装件88’。将中介层晶圆78锯切成中介层管芯，其中，图25中示出了一个中介层管芯78’。图25还示出了封装件88’与封装部件92的接合，封装部件92可以是封装衬底、框架、印刷电路板等。
在以上示出的实施例中，根据本发明的一些实施例讨论了一些工艺和部件，以形成三维(3D)封装件。也可以包括其它部件和工艺。例如，可以包括测试结构以辅助3D封装件或3DIC器件的验证测试。测试结构可以包括例如形成在再分布层中或衬底上的测试焊盘，以允许使用探针和/或探针卡等测试3D封装件或3DIC。可以对中间结构以及最终结构实施验证测试。此外，本文公开的结构和方法可以与结合已知良好管芯的中间验证的测试方法结合使用以提高良率并且降低成本。
本发明的实施例具有一些有利特征。通过直接从器件管芯(诸如逻辑管芯)和/或存储器管芯形成再分布线，逻辑管芯和存储器管芯之间的互连通过直接从器件管芯和存储器管芯形成的RDL实现，而不是通过金属凸块或焊料区域。由于去除了金属凸块和焊料区域，所以减小了产生的封装件的高度，从而允许更多存储器管芯堆叠在相同高度。而且，通孔形成在密封材料中而不是形成在存储器管芯的半导体衬底中。因此，消除了由存储器管芯中的TSV和半导体衬底之间的寄生电容引起的负载。由于存储器管芯通常占据比下面的器件管芯更小的覆盖区，因此在封装剂中形成通孔不会使得封装件的占用面积增加。
根据本发明的一些实施例，方法包括形成存储器管芯堆叠件，形成存储器管芯堆叠件包括将第一存储器管芯放置在下介电层上；在下介电层上方形成第一多个金属柱；将第一存储器管芯密封在第一密封剂中；形成第一再分布结构，形成第一再分布结构包括在第一密封剂上方形成第一多个介电层；以及在第一多个介电层中形成第一多个再分布线，其中，第一多个再分布线电连接至第一多个金属柱和第一存储器管芯；将第二存储器管芯放置在第一再分布结构上方；在第一再分布结构上方形成第二多个金属柱，其中，第二多个金属柱电连接至第一多个金属柱；将第二存储器管芯密封在第二密封剂中；形成第二再分布结构，形成第二再分布结构包括在第二密封剂上方形成第二多个介电层；以及在第二多个介电层中形成第二多个再分布线，其中，第二多个再分布线电连接至第二多个金属柱和第二存储器管芯。在实施例中，第一存储器管芯和第二存储器管芯中没有衬底通孔。在实施例中，第一存储器管芯通过第一粘合膜放置在下介电层上，并且第二存储器管芯通过第二粘合膜放置在第二再分布结构上。在实施例中，该方法还包括形成附加再分布结构，形成附加再分布结构包括在器件管芯上方形成附加的多个介电层，该器件管芯包括半导体衬底和半导体衬底中的通孔，其中，下介电层包含在附加的多个介电层中；以及在附加的多个介电层中形成附加的多个再分布线，其中，附加的多个再分布线电连接至通孔。在实施例中，在器件管芯的前侧上形成附加再分布结构，并且器件管芯包括位于前侧上的电连接件，以及将电连接件密封在其中的第一聚合物层。在实施例中，形成附加再分布结构包括减薄第一聚合物层以露出电连接件；以及在电连接件和第一聚合物层上方设置接触电连接件和第一聚合物层的第二聚合物层，其中，第二聚合物层包含在附加的多个介电层中。在实施例中，附加再分布结构形成在器件管芯的背侧上。在实施例中，形成附加再分布结构包括：减薄器件管芯的半导体衬底以露出通孔；以及在通孔和半导体衬底上方设置接触通孔和半导体衬底的聚合物层，其中，聚合物层包含在附加的多个介电层中。在实施例中，该方法还包括将存储器管芯堆叠件接合在器件管芯上，其中，第一多个金属柱电连接至器件管芯的半导体衬底中的通孔。
根据本发明的一些实施例，方法包括减薄器件管芯的半导体衬底，以露出延伸至半导体衬底中的衬底通孔；形成第一再分布结构，形成第一再分布结构包括在半导体衬底上方形成第一多个介电层；在第一多个介电层中形成第一多个再分布线，其中，第一多个再分布线电连接至衬底通孔；将第一存储器管芯放置在第一再分布结构上方；在第一再分布结构上方形成第一多个金属柱，其中，第一多个金属柱电连接至第一多个再分布线；将第一存储器管芯密封在第一密封剂中；以及在第一多个金属柱和第一存储器管芯上方形成电连接至第一多个金属柱和第一存储器管芯的第二多个再分布线。在实施例中，该方法还包括形成第二再分布结构，形成第二再分布结构包括在第一密封剂上方形成第二多个介电层，其中，第二多个再分布线位于第二多个介电层中。在实施例中，第一多个介电层中的底部介电层与半导体衬底和衬底通孔物理接触。在实施例中，衬底通孔通过绝缘衬垫与半导体衬底分隔开，并且底部介电层进一步与绝缘衬垫接触。在实施例中，形成第一多个介电层包括形成多个聚合物层。在实施例中，第一存储器管芯包括附加半导体衬底，并且第一存储器管芯在附加半导体衬底中没有通孔。
根据本发明的一些实施例，集成电路结构包括器件管芯。器件管芯包括半导体衬底；穿透半导体衬底的多个衬底通孔；以及位于半导体衬底的侧上的互连结构；第一再分布结构，位于器件管芯上方并且包括第一多个介电层；以及位于第一多个介电层中的第一多个再分布线，其中，第一多个再分布线电连接至器件管芯。集成电路结构还包括：位于第一再分布结构上方的第一存储器管芯；位于第一再分布结构上方的第一多个金属柱，其中，第一多个金属柱电连接至第一多个再分布线；第一密封剂，其中密封第一存储器管芯和第一多个金属柱；以及第二多个再分布线，位于第一密封剂上方并且电连接至第一存储器管芯和第一多个金属柱。在实施例中，第一存储器管芯包括附加半导体衬底，并且第一存储器管芯没有穿透附加半导体衬底的通孔。在实施例中，集成电路结构还包括位于第一多个金属柱上方并且电连接至第一多个金属柱的第二存储器管芯。在实施例中，第一多个介电层包括与器件管芯的半导体衬底物理接触的底部介电层。在实施例中，互连结构位于第一再分布结构和半导体衬底之间。
根据本发明的一些实施例，集成电路结构包括：器件管芯，器件管芯包括半导体衬底，多个衬底通孔，穿透所述半导体衬底，以及互连结构，互连结构位于半导体衬底的侧上；第一再分布结构，第一再分布结构位于器件管芯上方并且包括第一多个介电层，以及第一多个再分布线，第一多个再分布线位于第一多个介电层中，其中，第一多个再分布线电连接至器件管芯；第一存储器管芯，第一存储器管芯位于第一再分布结构上方；第一多个金属柱，第一多个金属柱位于第一再分布结构上方，其中，第一多个金属柱电连接至第一多个再分布线；第一密封剂，第一密封剂中密封第一存储器管芯和第一多个金属柱；以及第二多个再分布线，第二多个再分布线位于第一密封剂上方并且电连接至第一多个金属柱。在实施例中，第一存储器管芯包括附加半导体衬底，并且第一存储器管芯没有穿透所述附加半导体衬底的通孔。在实施例中，集成电路结构还包括，位于所述第一多个金属柱上方并且电连接至所述第一多个金属柱的第二存储器管芯。在实施例中，第一多个介电层包括与所述器件管芯的半导体衬底物理接触的底部介电层。在实施例中，互连结构位于所述第一再分布结构和所述半导体衬底之间。
上面概述了若干实施例的特征，使得本领域人员可以更好地理解本发明的方面。本领域人员应该理解，它们可以容易地使用本发明作为基础来设计或修改用于实施与本文所介绍实施例相同的目的和/或实现相同优势的其它工艺和结构。本领域技术人员也应该意识到，这种等同构造并不背离本发明的精神和范围，并且在不背离本发明的精神和范围的情况下，本文中它们可以做出多种变化、替换以及改变。

Claims (10)

1.一种形成管芯堆叠件的方法，包括：
形成存储器管芯堆叠件，包括：
将第一存储器管芯放置在下介电层上；
在所述下介电层上方形成第一多个金属柱；
将所述第一存储器管芯密封在第一密封剂中；
形成第一再分布结构，包括：
在所述第一密封剂上方形成第一多个介电层；以及
在所述第一多个介电层中形成第一多个再分布线，其中，所述第一多个再分布线电连接至所述第一多个金属柱和所述第一存储器管芯；
将第二存储器管芯放置在所述第一再分布结构上方；
在所述第一再分布结构上方形成第二多个金属柱，其中，所述第二多个金属柱电连接至所述第一多个金属柱；
将所述第二存储器管芯密封在第二密封剂中；
形成第二再分布结构，包括：
在所述第二密封剂上方形成第二多个介电层；以及
在所述第二多个介电层中形成第二多个再分布线，其中，所述第二多个再分布线电连接至所述第二多个金属柱和所述第二存储器管芯。
2.根据权利要求1所述的形成管芯堆叠件的方法，其中，所述第一存储器管芯和所述第二存储器管芯中没有衬底通孔。
3.根据权利要求1所述的形成管芯堆叠件的方法，其中，所述第一存储器管芯通过第一粘合膜放置在所述下介电层上，并且所述第二存储器管芯通过第二粘合膜放置在所述第二再分布结构上。
4.根据权利要求1所述的形成管芯堆叠件的方法，还包括：
形成附加再分布结构，包括：
在器件管芯上方形成附加的多个介电层，所述器件管芯包括半导体衬底和位于所述半导体衬底中的通孔，其中，所述下介电层包含在所述附加的多个介电层中；以及
在所述附加的多个介电层中形成附加的多个再分布线，其中，所述附加的多个再分布线电连接至所述通孔。
5.根据权利要求4所述的形成管芯堆叠件的方法，其中，在所述器件管芯的前侧上形成所述附加再分布结构，并且所述器件管芯包括位于所述前侧上的电连接件，以及将所述电连接件密封在其中的第一聚合物层。
6.根据权利要求5所述的形成管芯堆叠件的方法，其中，形成所述附加再分布结构包括：
减薄所述第一聚合物层以露出所述电连接件；以及
在所述电连接件和所述第一聚合物层上方设置接触所述电连接件和所述第一聚合物层的第二聚合物层，其中，所述第二聚合物层包含在所述附加的多个介电层中。
7.根据权利要求4所述的形成管芯堆叠件的方法，其中，所述附加再分布结构形成在所述器件管芯的背侧上。
8.根据权利要求7所述的形成管芯堆叠件的方法，其中，形成所述附加再分布结构包括：
减薄所述器件管芯的半导体衬底以露出所述通孔；以及
在所述通孔和所述半导体衬底上方设置接触所述通孔和所述半导体衬底的聚合物层，其中，所述聚合物层包含在所述附加的多个介电层中。
9.一种形成管芯堆叠件的方法，包括：
减薄器件管芯的半导体衬底，以露出延伸至半导体衬底中的衬底通孔；
形成第一再分布结构，包括：
在所述半导体衬底上方形成第一多个介电层；以及
在所述第一多个介电层中形成第一多个再分布线，其中，所述第一多个再分布线电连接至所述衬底通孔；
将第一存储器管芯放置在所述第一再分布结构上方；
在所述第一再分布结构上方形成第一多个金属柱，其中，所述第一多个金属柱电连接至所述第一多个再分布线；
将所述第一存储器管芯密封在第一密封剂中；以及
在所述第一多个金属柱和所述第一存储器管芯上方形成电连接至所述第一多个金属柱和所述第一存储器管芯的第二多个再分布线。
10.一种集成电路结构，包括：
器件管芯，包括：
半导体衬底；
多个衬底通孔，穿透所述半导体衬底；以及
互连结构，位于所述半导体衬底的侧上；
第一再分布结构，位于所述器件管芯上方并且包括：
第一多个介电层；以及
第一多个再分布线，位于所述第一多个介电层中，其中，所述第一多个再分布线电连接至所述器件管芯；
第一存储器管芯，位于所述第一再分布结构上方；
第一多个金属柱，位于所述第一再分布结构上方，其中，所述第一多个金属柱电连接至所述第一多个再分布线；
第一密封剂，所述第一密封剂中密封所述第一存储器管芯和所述第一多个金属柱；以及
第二多个再分布线，位于所述第一密封剂上方并且电连接至所述第一多个金属柱。
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