CN110473841A - 用于制造半导体装置封装的方法、封装和并入有此类封装的系统 - Google Patents

用于制造半导体装置封装的方法、封装和并入有此类封装的系统 Download PDF

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CN110473841A
CN110473841A CN201910384326.1A CN201910384326A CN110473841A CN 110473841 A CN110473841 A CN 110473841A CN 201910384326 A CN201910384326 A CN 201910384326A CN 110473841 A CN110473841 A CN 110473841A
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semiconductor bare
chip
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semiconductor
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CN110473841B (zh
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仲野英一
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Micron Technology Inc
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Micron Technology Inc
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Abstract

本申请案涉及用于制造半导体装置封装的方法、封装和并入有此类封装的系统。形成半导体装置封装的方法包括堆叠多个裸片，所述裸片堆叠呈现细接合线并且具有外环境涂层，所述接合线和环境涂层包括原位形成的化合物。还公开因此形成的半导体装置封装和并入有此类封装的电子系统。

Description

用于制造半导体装置封装的方法、封装和并入有此类封装的 系统
优先权主张
本申请案主张2018年5月10日申请的申请审理中的“用于制造3D半导体装置封装的方法、所得封装和并入有此类封装的系统(METHODS FOR FABRICATING 3DSEMICONDUCTOR DEVICE PACKAGES,RESULTING PACKAGES AND SYSTEMS INCORPORATINGSUCH PACKAGES)”的美国专利申请案第15/976,398号的申请日的权益。
技术领域
本文中所公开的实施例涉及制造包括多个半导体裸片的封装的方法。更特定地，本文中所公开的实施例涉及用于制造包括多个堆叠式半导体裸片的三维封装的的方法、所得封装和并入有此类封装的系统。
背景技术
随着电子行业发展并且涵盖更多的不同应用例如智能电话和其它移动装置、日益紧凑的个人(手提式和平板)计算机、人工智能、物联网和云计算，对包括堆叠式半导体裸片的高密度、小外观尺寸模块化封装的需求不断增加。在此情况下，外观尺寸不仅包含封装的占用面积(长度和宽度)而且还包含高度、对移动应用程序的重要考虑等等。此类需求不仅针对存储器裸片封装，而且还针对不仅包括存储器裸片而且还包括存储器裸片以及逻辑、处理器和射频(RF)裸片中的一或多个的封装。
虽然已展示可能制造此类封装，但半导体行业迄今尚未具备制造此类封装以提供合理成本下的小外观尺寸和商业规模上的可接受产额的能力。
发明内容
在一实施例中，一种用于制造半导体装置封装的方法包括：将包括其横向间隔开的半导体裸片位置的晶片粘附到载体衬底，其中所述晶片的有源表面面向所述载体衬底；在所述晶片的背侧上方形成电介质材料；将第一层级的经单分半导体裸片以相互横向间隔开的关系放置在相应半导体裸片位置上方；和将从所述晶片的所述背侧穿过所述电介质材料突出的导电柱连接到所述半导体裸片的经对齐端垫。
在另一实施例中，一种形成半导体装置封装的方法包括在晶片的背侧上的相应半导体裸片位置上方以相互横向间隔开的关系堆叠多个层级的经单分半导体裸片；和在堆叠每一经单分半导体裸片之前，在半导体裸片位置或下部经单分半导体裸片的背侧上方形成电介质接合线材料。将经单分裸片的端垫连接到穿过所述半导体裸片位置的所述背侧上方或较低层级的经单分半导体裸片的背侧上方的所述电介质接合线材料暴露的相应导电柱；进行到所述经单分半导体裸片之间的空间中、到其划线区域中的材料中以及到半导体裸片位置之间的划线区域内的所述晶片的材料中的第一宽度的切割。在所述堆叠的最上部裸片的背侧上方、所述经单分半导体裸片的侧面上方以及半导体裸片位置之间的所述晶片的材料上方形成涂层，且进行在所述堆叠之间进入并穿过所述半导体裸片位置之间的所述晶片的剩余材料的第二更窄宽度的切割。
在另一实施例中，一种半导体装置封装包括半导体裸片堆叠，其中所述堆叠的最下部半导体裸片的表面横向突出到超过所述堆叠的其它较高半导体裸片的外围；所述堆叠的相邻半导体裸片之间的非聚合电介质接合线材料；所述堆叠的相邻半导体裸片的金属柱与经对齐端垫之间的连接，所述连接包括扩散接合或通过用所述电介质接合线材料对所述半导体裸片的电介质接合来保全的相互接触；和大体保形的非聚合涂层，其在所述堆叠的最上部半导体裸片的背侧上方延伸，在所述堆叠的侧面上的所述半导体裸片的材料上方延伸并接触所述材料，并且在所述堆叠的所述最下部半导体裸片的所述横向突出表面上方延伸并接触所述横向突出表面。
在又一实施例中，一种电子系统包括至少一个输入装置；至少一个输出装置；处理器装置，其以可操作方式耦合到所述至少一个输入装置和所述至少一个输出装置；和存储器装置。所述存储器装置包括半导体裸片堆叠，其中所述堆叠的最下部半导体裸片横向突出到超过所述堆叠的其它较高半导体裸片的外围；电介质接合线材料，其包括所述堆叠的相邻半导体裸片之间的原位形成的化合物；和所述堆叠的相邻半导体裸片的金属柱与经对齐端垫之间的连接，所述连接包括扩散接合或通过所述半导体裸片的电介质接合来保全的相互接触。包括原位形成的化合物的大体保形涂层在所述堆叠的最上部半导体裸片的背侧上方延伸，在所述堆叠的侧面上的所述半导体裸片的材料上方延伸并接触所述半导体裸片的材料，并且在所述堆叠的所述横向突出的最下部半导体裸片上方延伸并接触所述横向突出的最下部半导体裸片。
附图说明
图1到14是根据本公开的实施例的制造半导体装置封装的方法的实施例的横截面示意图；
图15是根据本公开的实施例的封装的半导体裸片的一部分的扩大的示意性横截面图；
图16A是根据本公开的实施例的制造并且包含存储器裸片和RF裸片的半导体装置封装的横截面示意图；
图16B是根据本公开的实施例的制造并且包含存储器裸片和逻辑裸片的半导体装置封装的横截面示意图；和
图17是根据本公开的一个或多个实施例的包含至少一个半导体装置封装的电子系统的框图。
具体实施方式
公开一种制造包括多个堆叠式半导体裸片的半导体装置封装的方法。在一些实施例中，所述封装仅包括存储器裸片，而在其它实施例中，所述封装包括存储器裸片和至少一种其它类型的裸片，例如处理器、逻辑或射频(RF)裸片。
以下描述提供例如大小、形状、材料成分和定向等具体细节以便提供对本公开的实施例的充分描述。然而，所属领域的技术人员将理解，可在不必采用这些具体细节的情况下实践本公开的实施例。可与行业中采用的常规制造技术结合来实践本公开的实施例。另外，下文提供的描述不形成用于制造半导体装置封装或包含半导体装置封装的较高层级组合件的完整过程流。下文仅详细地描述理解本公开的实施例所必需的那些过程动作和结构。可由常规制造过程执行用以从本文中所描述的过程和封装形成完整半导体装置封装或包含半导体装置封装的更高层级组合件的额外动作。
本文中呈现的图式仅出于说明性目的，且并不意图为任何特定材料、组件、结构、装置或系统的实际视图。应预期例如由于制造技术和/或公差引起的图式中描绘的形状的变化。因此，本文中所描述的实施例不应解释为限于如所说明的特定形状或区域，而是包含例如由制造引起的形状偏离。举例来说，说明或被描述为箱形的区域可具有粗糙和/或非线性特征，且说明或描述为圆形的区域可包含一些粗糙和/或线性特征。此外，所说明的表面之间的锐角可为圆角，且反之亦然。因此，图中所说明的区域在性质上是示意性的，且其形状并不意图说明区域的精确形状并且不限制本发明权利要求的范围。图式并不一定按比例绘制。
如本文中所使用，术语“包括”、“包含”、“含有”、“表征为”和其语法等效物是包含端点的或开放的术语，其不排除额外的未列出元件或方法动作，而是还包含更具限定性术语“由…组成”和“主要由…组成”以及其语法等效物。如本文中所使用，关于材料、结构、特征或方法动作的术语“可”指示此类预期供在实施本公开的实施例时使用，且此类术语优先于在更具限定性术语“是”意义上使用以便避免对于应或必须排除可与其组合使用的其它兼容材料、结构、特征和方法的任何暗示。
如本文中所使用，术语“纵向”、“竖直”、“横向”和“水平”是参考其中或其上形成一或多个结构和/或特征的衬底(例如，基底材料、基底结构、基底构造等)的主平面并且不一定由地球重力场界定。“横向”或“水平”方向是大体平行于衬底的主平面的方向，而“纵向”或“竖直”方向是大体垂直于衬底的主平面的方向。衬底的主平面是由与衬底的其它表面相比具有相对大面积的衬底的表面界定。
如本文中所使用，空间相对术语例如“下面”、“下方”、“下部”、“底部”、“上面”、“上方”、“上部”、“顶部”、“前面”、“后部”、“左侧”、“右侧”等等可为了便于描述而用于描述一个元件或特征与如图中所说明的另一或多个元件或特征的关系。除非另外规定，否则除图式中所描绘的定向之外，空间相对术语还意图涵盖材料的不同定向。举例来说，如果图式中的材料倒置，那么被描述为在其它元件或特征“上方”或“上面”或“上”或“顶部上”的元件将定向于所述其它元件或特征的“下方”或“下面”或“下”或“底部”。因此，术语“上方”可视使用术语的上下文而定涵盖上方和下方两种定向，这对于所属领域的一般技术人员将为显而易见的。材料可以其它方式定向(例如，旋转90度、倒置、翻转)，且本文中所用的空间相对描述词可相应地进行解释。
如本文中所使用，除非上下文另外明确指示，否则单数形式“一”和“所述”意图还包含复数形式。
如本文中所使用，术语“被配置成”和“配置”指代以预定方式促进至少一个结构和至少一个设备中的一或多个的操作的所述结构和所述设备中的一或多个的大小、形状、材料成分、定向和布置。
如本文中所使用，关于给定参数、性质或条件的术语“大体上”意指并包含在所属领域的一般技术人员将理解的给定参数、性质或条件满足方差度(如在可接受制造公差内)的程度。借助于实例，视大体上满足的特定参数、性质或条件而定，可至少90.0％满足、至少95.0％满足、至少99.0％满足或甚至至少99.9％满足所述参数、性质或条件。
如本文中所使用，关于给定参数的术语“约”包含所陈述值并且具有上下文指示的含义(例如，包含与给定参数的测量值相关联的误差度)。
如本文中所使用，除非另外指明，否则术语“层”和“膜”意指并包含驻留于结构上的材料层级、片材或涂层，所述层级、片材或涂层在材料部分之间可为连续或不连续的，且其可为保形或非保形的。
如本文中所使用，术语“晶片”不仅意指并包含单个材料例如单晶硅的常规的大体圆形晶片，而且还意指并包含呈绝缘体上硅(SOI)结构形式的其它块状衬底，以及包括其它半导体材料例如锗或砷化镓的块状衬底。
如本文中所使用，术语“化合物”意指并包含由呈固定、化学计量或非化学计量比例并且具有通过化学键与定义的空间布置保持在一起的唯一化学结构的两个或更多个不同类型的原子组成的材料。
图1是包括多个裸片位置102的基底半导体晶片例如硅晶片100的横截面示意图。每一裸片位置102包括有源表面，其也可表征为装置层104，包括有源电路106，例如呈动态随机存取存储器(DRAM)电路或NAND快闪存储器电路形式的存储器电路。有源电路106与呈例如其上具有(任选)焊料盖110的铜柱108形式的外部导电元件电连通。图1还标示硅晶片100中的划线区域112，描绘相邻半导体裸片位置102之间的所谓的“街道”。
图2是从图1中示出的定向倒置并且紧固到可包括硅、玻璃、陶瓷或其它合适材料的载体衬底114的硅晶片100的横截面示意图。晶片100通过暂时性粘附剂116例如热释放粘附剂、溶剂释放粘附剂或紫外线(UV)释放粘附剂紧固到载体衬底114，其中铜柱108和(任选)焊料盖110嵌入于暂时性粘附剂116和硅晶片100的背对载体衬底114的背侧118中。
在图3中，硅晶片100在紧固到载体衬底114的情况下从其背侧118薄化，例如从约600μm的初始厚度到约700μm再到介于约30μm到约70μm之间的最终厚度。可通过例如背面粗研磨后跟着细研磨或抛光、湿式(化学)蚀刻或干式等离子蚀刻或通过化学机械平面化(CMP)来实现所述薄化。当然，如下文所描述，在薄化中采用的一或多种过程与通孔是在晶片100中预成型还是在附接到载体衬底之后形成有关。
如图4中所示出，在薄化硅晶片100之后，在一个实施例中，在背侧118上形成电介质材料122，所述电介质材料122也可表征为电介质接合线材料，之后例如通过非等向性(例如，反应性离子)蚀刻形成穿过晶片100的背侧118上的电介质材料122并且延伸穿过晶片100以电连接到有源电路106的通孔120。用电介质材料222为通孔120加衬，并且通过沉积过程形成包括例如金属例如铜的导电柱126的穿通导体124。在另一实施例中，在形成电介质材料122之前形成通孔120，且共同电介质材料122为通孔120加衬并且在晶片100的背侧118上方延伸。接着形成穿通导体124和一体式导电柱126。如在转让给本公开的受让人的美国专利公开案第US 2017/01486674A1号中所公开，电介质材料122可为非聚合材料，不含填充材料并且可包括例如氧化硅(例如，SiO2)、氮化硅(例如，Si3N4)、氮氧化硅(例如，SiOxNy)，或TEOS氧化物或O3/TEOS氧化物。电介质材料122可通过化学气相沉积(CVD)、原子层沉积(ALD)、等离子体增强式化学气相沉积(PECVD)、次大气化学气相沉积(SACVD)物理气相沉积、大气压力等离子体沉积或其它已知技术原位形成为化合物。如果采用电介质材料222，那么其可包括上述材料中的一种并且包括与电介质材料122相同或不同的电介质材料。
在另一实施例中，通孔120可在如图3中所说明的薄化之前预成型为盲孔，其内衬为电介质材料222并且包括晶片100中的穿通导体124。接着通过从晶片100的背侧118蚀刻来暴露导体124，以提供从背侧118突出的导电柱126，之后可应用另一电介质材料122作为晶片100的背侧118上方的层，从而得出图4中示出的结构。
在前述实施例中的任一个中，形成的电介质材料122极薄，约为约10μm到约25μm，从而提供非常窄的接合线供随后放置半导体裸片，如下文所描述。
图5A和5B描绘包括半导体裸片位置102的另一晶片100′，每一半导体裸片位置102在以可操作方式耦合到端垫108′的装置层104上具有有源电路106，所述端垫108′可包括铜并且也可表征为接合垫。半导体裸片位置102通过划线区域112分隔开。如所示的晶片100′如晶片100从约600的初始厚度到约700μm到介于约30μm到约70μm之间的最终厚度薄化。如图5B中所示，晶片100′在切割128处穿过划线区域112分隔或“单分”成个别半导体裸片102′。值得注意的是，如图5B中所示，通过极窄划割锯片宽度实现单分，从而使划线区域112内的大部分宽度在切割128的每一侧保持完好。
在图6中，从晶片100′单分出第一层级的个别半导体裸片102′并且优选地包括已知良好裸片(KGD)，使用常规取放设备将其以相互横向间隔开的关系放置于晶片100上，每一半导体裸片102′通过端垫108′叠置于晶片100的半导体裸片位置102上，与下伏半导体裸片位置102的导电柱126对齐。可例如通过铜柱126到铜端垫108′的扩散接合，或通过使用先前应用于晶片100的背侧118的电介质材料122在每一半导体裸片102′与其对应的下伏半导体裸片位置102上方的电介质材料122之间的电介质接合，实现导电柱126与端垫108′之间的电耦合。可如在所属领域中已知，例如在美国专利9,391,143中所公开实现电介质接合。通过其中任一技术，可在确保相邻半导体裸片102′之间以及半导体裸片位置102与相邻半导体裸片102′之间的相互电耦合和机械耦合的同时达成极细接合线。归因于热预算和过程时间问题，可在堆叠所有层级的半导体裸片102′之后实现扩散接合或电介质接合。
在图7中，另一电介质材料122应用于半导体裸片102′的背侧118′上方并且覆盖半导体裸片102′的背侧118′并延伸到相邻半导体裸片102′之间的空间130中。
如图8中所示，已经执行晶片上芯片(COW)薄化过程以移除半导体裸片102′的背侧118′上方的过量电介质材料122，保留相邻半导体裸片102′之间的空间130中和其暴露侧表面132上方的电介质材料122。
随后，如图9所示，在半导体裸片102′的背侧118′上方安置又一电介质材料122。接着通过常规技术从每一半导体裸片102′的背侧118′形成穿过电介质材料122延伸到每一半导体裸片102′的有源电路106的通孔120。接着用电介质材料222为通孔120加衬并且填充导电材料(例如铜)，以形成包括突出到半导体裸片102′的背侧118′上方并且到达电介质材料122的表面的导电柱126的导体124。
在另一实施例中，先前已薄化放置在半导体裸片位置102(图6)上的第一层级的经单分半导体裸片102′以及堆叠(图10)的另外层级的经单分半导体裸片102′，并且在晶片层级(图5A)通过以下操作进行进一步处理：将电介质材料122应用到背侧118，接着形成到晶片100′中的通孔120，接着用电介质材料222为通孔加衬并且填充导电材料以形成包括突出到背侧118上方以到达电介质材料122的表面的导电柱126的导体124。接着可单分并堆叠在适当位置具有电介质材料122和导电柱126的半导体裸片102′。此类实施例可促进半导体裸片102′的堆叠的更快速制造，增加产额并且实现对接合线宽度的更紧密控制。
接着在晶片100的每一半导体裸片位置102处堆叠如图10中所示的额外层级的半导体裸片102′，每一半导体裸片102′如上文关于图6到9所描述紧固并电连接到下伏半导体裸片102′并且配置有通孔120和导电柱126以用于连接到另一半导体裸片102′的端垫108′直到形成所要数目层的半导体裸片102′。然而，最上部半导体裸片102u′不要求通孔。在所述点，并且如图10中所说明，最上部半导体裸片102′的背侧118′覆盖有延伸到相邻半导体裸片102′之间的空间130中并且在其暴露的侧表面132上方延伸的电介质材料122。
现参考图11，在进入晶片100例如在装置层104上方的深度上部分地单分晶片100的半导体裸片位置102上的堆叠式半导体裸片102′的组合件，在第一切割中通过大小设定成从相邻半导体裸片102′之间移除电介质材料122或222以及从半导体裸片102′的相邻堆叠中的相互相邻半导体裸片102′的大致上整个的每一划线区域112移除材料并且形成较大空间134的宽度W的划割锯实现单分。
如图12中所示，实现包括通过例如上文所提及的技术中的一种沉积的环境涂层的另一电介质材料322，以防止湿气渗透到多个半导体裸片102′的每一组合件200和部分地单分的半导体裸片位置102中。电介质材料322在每一组合件200的最上部裸片102′的背侧上方、在与半导体裸片102′的材料接触的裸片堆叠的侧面上方以及横向向外在部分地单分的半导体裸片位置102的暴露表面上方延伸。适合的电介质材料可为非聚合的并且原位形成在组合件200上方。此类电介质材料包含例如氮化硅或氮氧化硅，经应用以形成厚度介于约25μm与约50μm之间的大致上保形涂层。图15说明此类应用的电介质材料322不仅大致上保形地涂布裸片堆叠的外表面而且还填充例如半导体裸片102′与相互叠置半导体裸片102′之间的接合线中的先前应用的相邻电介质材料122之间的任何暴露的外围空间136的效应。
在图13中，接着在穿过晶片100的整个深度并穿过每一空间134的中心进入粘附剂116的第二更窄切割中并且使用显著小于空间134和切割间隙138的宽度的宽度的划片机单分每一组合件200，以便不接触半导体裸片102′的侧表面132上的保护涂层的电介质材料322并且完全切断晶片100的相邻半导体裸片位置102并单分组合件200。接着在通过依据粘附剂116(例如，热释放粘附剂、溶剂释放粘附剂或紫外线(UV)释放粘附剂)的性质应用适当的释放剂基本破除粘附剂116到载体衬底114的的粘附之后，通过常规取放设备从载体衬底114移除每一单分的组合件200。在图14中示出封装完成之后的个别组合件200。
图16A描绘在对应于关于图10描绘和描述的制造阶段堆叠在晶片100的半导体裸片位置102上的异构半导体裸片102′的多个过程内未经单分组合件200。在图16A中，晶片100包括逻辑裸片位置102l，在所述逻辑裸片位置102l上堆叠DRAM裸片102d′，在所述逻辑裸片位置102l上方在每一堆叠的顶部是RF裸片102r′。
图16B描绘在从载体衬底114移除之前堆叠在晶片100的经割断半导体裸片位置102上的半导体裸片102′的其它经单分组合件200。在图16B中，晶片100包括DRAM裸片位置102d，多个DRAM裸片102d′堆叠在每一DRAM裸片位置102d上，且在每一堆叠的顶部是RF裸片102r′。
值得注意的是，在图16A和16B中的每一个中，给定堆叠中的每一裸片位置102和每一裸片102′的外围处的相对宽划线区域提供用于单分的宽公差并且使得呈现不同功能性的半导体裸片能够堆叠成受控制裸片宽度的组合件，接着可制造成具有相互并行的对齐裸片侧的立方体，有利于通过所公开的类型的装配后应用的涂层的环境保护。还消除对于用模制化合物包封组合件的常规要求。另外，可通过使用所公开的电介质材料实现的相邻裸片堆叠的紧密间隔来最小化晶片材料损失，且可通过在接合线中使用所公开的电介质材料而非例如非导电膏、非导电膜和毛细管底部填料的常规电介质，显著减小裸片堆叠的高度。最后，所述的对用常规模制化合物包封组合件的要求的消除显著地减小占用面积，并且因此显著地减小较高层级封装上的封装所需的占据面积。
可在本公开的电子系统的实施例中使用根据本公开的实施例的半导体装置(例如，封装的半导体装置组合件200)。举例来说，图17是根据本公开的实施例的说明性电子系统300的框图。电子系统300可包括例如计算机或计算机硬件组件、服务器或其它网络连接硬件组件、蜂窝式电话、数码相机、个人数字助理(PDA)、便携式媒体(例如，音乐)播放器、具备Wi-Fi或蜂窝能力的平板计算机例如或平板计算机、电子书、导航装置等。电子系统300包含至少一个存储器装置302。存储器装置302可包含例如本文中所描述的半导体装置组合件200的实施例。此类存储器装置可任选地，包含被配置成用于其它功能的裸片，例如逻辑裸片、RF裸片或两者。电子系统300可另外包含至少一个电子信号处理器装置304(通常被称为“微处理器”)。电子系统300可另外包含用于用户将信息输入到电子系统300中的一或多个输入装置306，例如鼠标或其它指标装置、键盘、触摸板、按钮或控制面板。电子系统300可另外包含用于将信息(例如，视觉或音频输出)输出到用户的一或多个输出装置308，例如监视器、显示器、打印机、音频输出插孔、扬声器等。在一些实施例中，输入装置306和输出装置308可包括可用以将信息输入到电子系统300以及将视觉信息输出到用户的单个触摸屏装置。输入装置306和输出装置308可与存储器装置302和电子信号处理器装置304中的一或多个电连通。还预期，代替单独存储器和信号处理器装置302和304，单个组合件200可配置为包含处理器和/或如所先前提及的其它裸片功能性的系统级封装。
在一实施例中，一种用于制造半导体装置封装的方法包括：将包括其横向间隔开的半导体裸片位置的晶片粘附到载体衬底，其中所述晶片的有源表面面向所述载体衬底；在所述晶片的背侧上方形成电介质材料；将第一层级的经单分半导体裸片以相互横向间隔开的关系放置在相应半导体裸片位置上方；和将从所述晶片的所述背侧穿过所述电介质材料突出的导电柱连接到所述半导体裸片的经对齐端垫。
在另一实施例中，一种形成半导体装置封装的方法包括在晶片的背侧上的相应半导体裸片位置上方以相互横向间隔开的关系堆叠多个层级的经单分半导体裸片；和在堆叠每一经单分半导体裸片之前，在半导体裸片位置或下部经单分半导体裸片的背侧上方形成电介质接合线材料。将经单分裸片的端垫连接到穿过所述半导体裸片位置的所述背侧上方或较低层级的经单分半导体裸片的背侧上方的所述电介质接合线材料暴露的导电柱；进行到所述经单分半导体裸片之间的空间中、到其划线区域中的材料中以及到半导体裸片位置之间的划线区域内的所述晶片的材料中的第一宽度的切割。在所述堆叠的最上部裸片的背侧上方、所述经单分半导体裸片的侧面上方以及半导体裸片位置之间的所述晶片的材料上方形成涂层，且进行在所述堆叠之间进入并穿过所述半导体裸片位置之间的所述晶片的剩余材料的第二更窄宽度的切割。
在另一实施例中，一种半导体装置封装包括半导体裸片堆叠，其中所述堆叠的最下部半导体裸片的表面横向突出到超过所述堆叠的其它较高半导体裸片的外围；所述堆叠的相邻半导体裸片之间的非聚合电介质接合线材料；所述堆叠的相邻半导体裸片的金属柱与经对齐端垫之间的连接，所述连接包括扩散接合或通过用所述电介质接合线材料对所述半导体裸片的电介质接合来保全的相互接触；和大体保形的非聚合涂层，其在所述堆叠的最上部半导体裸片的背侧上方延伸，在所述堆叠的侧面上的所述半导体裸片的材料上方延伸并接触所述材料，并且在所述堆叠的所述最下部半导体裸片的所述横向突出表面上方延伸并接触所述横向突出表面。
在又一实施例中，一种电子系统包括至少一个输入装置；至少一个输出装置；处理器装置，其以可操作方式耦合到所述至少一个输入装置和所述至少一个输出装置；和存储器装置。所述存储器装置包括半导体裸片堆叠，其中所述堆叠的最下部半导体裸片横向突出到超过所述堆叠的其它较高半导体裸片的外围；电介质接合线材料，其包括所述堆叠的相邻半导体裸片之间的原位形成的化合物；和所述堆叠的相邻半导体裸片的金属柱与经对齐端垫之间的连接，所述连接包括扩散接合或通过所述半导体裸片的电介质接合来保全的相互接触。包括原位形成的化合物的大体保形涂层在所述堆叠的最上部半导体裸片的背侧上方延伸，在所述堆叠的侧面上的所述半导体裸片的材料上方延伸并接触所述半导体裸片的材料，并且在所述堆叠的所述横向突出的最下部半导体裸片上方延伸并接触所述横向突出的最下部半导体裸片。
虽然已结合图式描述了某些说明性实施例，但所属领域的一般技术人员将认识到且理解，本公开所包含的实施例不限于在本文中明确地示出且描述的那些实施例。确切地说，可在不脱离本公开所包涵的实施例(如本文中所主张的那些实施例，包含合法等效物)的范围的情况下，对本文中所描述的实施例做出多种添加、删除和修改。另外，一个公开的实施例的特征可与另一公开的实施例的特征组合，且仍包涵在本公开的范围内。

Claims (28)

1.一种用于制造半导体装置封装的方法，所述方法包括：
将晶片、包括其横向间隔开的半导体裸片位置在内粘附到载体衬底，其中所述晶片的有源表面面向所述载体衬底；
在所述晶片的背侧上方形成电介质材料；
将第一层级的经单分半导体裸片以相互横向间隔开的关系放置在相应半导体裸片位置上方；
将从所述晶片的所述背侧穿过所述电介质材料突出的导电柱连接到所述经单分半导体裸片的经对齐端垫；和
在所述第一层级的所述经单分半导体裸片的背侧上方并在所述背侧之间的空间中形成电介质材料。
2.根据权利要求1所述的方法，其另外包括形成穿过所述电介质材料并进入所述晶片的所述背侧到达所述半导体裸片位置的有源电路的通孔，用电介质材料为所述通孔加衬并且用导电材料填充所述通孔以形成所述导电柱。
3.根据权利要求1所述的方法，其另外包括在将所述晶片粘附到所述载体衬底之前：
在所述晶片中形成延伸到所述半导体裸片位置的有源电路的通孔；
用电介质材料为所述通孔加衬；
用导电材料填充所述通孔；
从所述晶片的所述背侧薄化所述晶片以暴露所述导电材料作为所述导电柱；和
在所述晶片粘附到所述载体衬底之后，在所述晶片的所述背侧上方形成所述电介质材料并且保留所述导电柱的暴露末端。
4.根据权利要求1所述的方法，其另外包括在所述第一层级的所述经单分半导体裸片的背侧上方并在所述背侧之间的空间中形成电介质材料。
5.根据权利要求1所述的方法，其另外包括形成穿过所述第一层级的所述经单分半导体裸片的所述背侧上方的所述电介质材料并进入其所述背侧到达有源电路的通孔，用电介质材料为所述半导体裸片中的所述通孔加衬并且用导电材料填充所述通孔以形成所述导电柱。
6.根据权利要求1所述的方法，其另外包括在将所述第一层级的经单分半导体裸片以横向间隔开的关系放置在相应半导体裸片位置上方之前：
在至少一个晶片上，在用于所述经单分半导体裸片延伸到其有源电路的位置中形成通孔；
用电介质材料为所述通孔加衬；
用导电材料填充所述通孔；和
从所述晶片的所述背侧薄化所述晶片以暴露所述导电材料作为导电柱。
7.根据权利要求1所述的方法，其另外包括：
将至少另一层级的经单分半导体裸片以相互横向间隔开的关系放置在所述第一层级的相应经单分半导体裸片上方以形成裸片堆叠；和
将从所述第一层级的经单分半导体裸片的所述背侧穿过所述电介质材料突出的导电柱连接到所述至少另一层级的经单分半导体裸片的经对齐端垫。
8.根据权利要求7所述的方法，其另外包括在所述至少另一层级的经单分半导体裸片的背侧上方和所述背侧之间的空间中形成电介质材料。
9.根据权利要求8所述的方法，其另外包括进行在所述裸片堆叠之间进入相邻堆叠的经单分半导体裸片的划线区域并进入但不穿过包括半导体裸片位置的所述晶片的材料的第一宽度的切割。
10.根据权利要求9所述的方法，其另外包括在每一堆叠中的最上部经单分半导体裸片的背侧上的电介质材料上方、在所述经单分半导体裸片的侧面上方以及在包括通过进行所述切割暴露的所述半导体裸片位置的所述材料的侧面上方形成环境保护涂层。
11.根据权利要求10所述的方法，其另外包括进行比所述第一切割更窄并且全部在所述第一切割内进入并穿过包括所述半导体裸片位置的所述晶片的剩余材料并进入将包括所述半导体裸片位置的所述晶片粘附到所述载体衬底的粘附材料的第二切割。
12.根据权利要求10所述的方法，其中形成环境保护涂层包括形成氮化硅或氮氧化硅涂层。
13.根据权利要求1所述的方法，其中将从所述晶片的所述背侧穿过所述电介质材料突出的导电柱连接到所述半导体裸片的经对齐端垫包括所述经单分半导体裸片到所述半导体裸片位置的电介质接合或所述导电柱到所述相应端垫的扩散接合中的至少一个。
14.根据权利要求1所述的方法，其中形成电介质材料包括形成氧化硅、氮化硅、氮氧化硅、原硅酸四乙酯TEOS氧化物或臭氧/TEOS氧化物。
15.一种形成半导体装置封装的方法，所述方法包括：
在晶片的背侧上的相应半导体裸片位置上方以相互横向间隔开的关系堆叠多个层级的经单分半导体裸片；
在堆叠每一经单分半导体裸片之前，在半导体裸片位置的背侧或较低层级的经单分半导体裸片的背侧上方形成电介质接合线材料；
将经单分裸片的端垫连接到穿过所述半导体裸片位置的所述背侧上方或所述较低层级的经单分半导体裸片的所述背侧上方的所述电介质接合线材料暴露的相应导电柱；
进行到所述经单分半导体裸片之间的空间中、到其划线区域中的材料中以及到半导体裸片位置之间的划线区域内的所述晶片的所述材料中的第一宽度的切割；
在所述堆叠的最上部裸片的背侧上方、所述经单分半导体裸片的侧面上方以及半导体裸片位置之间的所述晶片的所述材料上方形成涂层；和
进行在所述堆叠之间进入并穿过所述半导体裸片位置之间的所述晶片的剩余材料的第二更窄宽度的切割。
16.根据权利要求15所述的方法，其中形成电介质接合线材料包括形成氧化硅、氮化硅、氮氧化硅、TEOS氧化物或O3/TEOS氧化物。
17.根据权利要求15所述的方法，其中形成涂层包括形成氮化硅或氮氧化硅涂层。
18.根据权利要求15所述的方法，其中连接包括通过所述电介质接合线材料的接合或所述导电柱到所述相应端垫的扩散接合中的至少一个。
19.根据权利要求15所述的方法，其中形成电介质接合线材料包括原位形成电介质材料。
20.一种半导体装置封装，其包括：
半导体裸片堆叠，其中所述堆叠的最下部半导体裸片的表面横向突出到超过所述堆叠的其它较高半导体裸片的外围；
所述堆叠的相邻半导体裸片之间的非聚合电介质接合线材料；
所述堆叠的相邻半导体裸片的金属柱与经对齐端垫之间的连接，所述连接包括扩散接合或通过用所述非聚合电介质接合线材料对所述半导体裸片的电介质接合来保全的相互接触；和
大体保形的非聚合涂层，其在所述堆叠的最上部半导体裸片的背侧上方延伸，在所述堆叠的侧面上的所述半导体裸片的材料上方延伸并接触所述材料，并且在所述堆叠的所述最下部半导体裸片的所述横向突出表面上方延伸并接触所述横向突出表面。
21.根据权利要求20所述的半导体装置封装，其另外包括从所述最下部半导体裸片的与所述堆叠的其它半导体裸片相对的表面突出的导电柱。
22.根据权利要求20所述的半导体装置封装，其中所述大体保形的非聚合涂层延伸到所述非聚合电介质接合线材料与所述堆叠在其橫向外围处的相邻半导体裸片的材料之间的开口中。
23.根据权利要求20所述的半导体装置封装，其中所述非聚合电介质接合线材料和所述非聚合涂层各自包括原位形成的化合物。
24.根据权利要求23所述的半导体装置封装，其中所述化合物选自由以下组成的群组：氧化硅、氮化硅、氮氧化硅、TEOS氧化物或O3/TEOS氧化物。
25.根据权利要求20所述的半导体装置封装，其中所述堆叠的至少一个半导体裸片展现除存储器以外的功能性。
26.根据权利要求25所述的半导体装置封装，其中所述至少一个其它半导体裸片展现包括逻辑、处理器或射频的功能性。
27.一种电子系统，其包括：
至少一个输入装置；
至少一个输出装置；
处理器装置，其以可操作方式耦合到所述至少一个输入装置和所述至少一个输出装置；和
存储器装置；
其中所述存储器装置包括：
半导体裸片堆叠，其中所述堆叠的最下部半导体裸片横向突出到超过所述堆叠的其它较高半导体裸片的外围；
电介质接合线材料，其包括所述堆叠的相邻半导体裸片之间的原位形成的化合物；
所述堆叠的相邻半导体裸片的金属柱与经对齐端垫之间的连接，所述连接包括扩散接合或通过所述半导体裸片的电介质接合来保全的相互接触；和
大体保形涂层，其包括原位形成的化合物并且在所述堆叠的最上部半导体裸片的背侧上方延伸，在所述堆叠的侧面上的所述半导体裸片的材料上方延伸并接触所述半导体裸片的材料，并且在所述堆叠的所述横向突出的最下部半导体裸片上方延伸并接触所述横向突出的最下部半导体裸片。
28.根据权利要求27所述的电子系统，其中所述存储器装置包括呈现除存储器以外的功能性的至少一个裸片。
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