TWI594369B - 與互補式金屬氧化物半導體相容的晶圓接合層及製程 - Google Patents

與互補式金屬氧化物半導體相容的晶圓接合層及製程 Download PDF

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TWI594369B
TWI594369B TW103128052A TW103128052A TWI594369B TW I594369 B TWI594369 B TW I594369B TW 103128052 A TW103128052 A TW 103128052A TW 103128052 A TW103128052 A TW 103128052A TW I594369 B TWI594369 B TW I594369B
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wafer
layer
bonding
wafer bonding
aluminum
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TW103128052A
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TW201528427A (zh
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阮甘納桑 納甘拉杰
福勤 陳
家輝 盧
俊豪 易
吳稼祺
晶澤 田
普拉迪普 拉瑪迦德蘭默菲 葉列漢卡
拉凱什 庫馬爾
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格羅方德半導體私人有限公司
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Description

與互補式金屬氧化物半導體相容的晶圓接合層及製程
本案關於一種晶圓接合層與晶圓接合製程。
近年來由於3-D晶片技術上的創新，裸片及晶圓集成(在下文中統稱為堆疊結構(stack structure))使裝置的微小化及科技的進展能夠在速度和密度上都有所提升，且同時能夠減低耗能及成本。晶圓接合是一種晶圓級的封裝技術，能夠允許兩個以上的晶圓進行垂直堆疊，並能晶圓與晶圓間提供電接連(electrical connection)和氣密封裝(hermetical sealing)。
現在各式的晶圓接合技術已經正在發展並應用于接合兩同型或異型的晶圓。然而，傳統的接合技術缺乏靈活性且無法被應用於異質(heterogeneous)的裝置集成，也無法用於非矽型的表面。此外，業界對於使用互補式金屬氧化物半導體代工相容材料將第一類晶圓如互補式金屬氧化物半導體晶圓，與第二類晶圓如微機電晶圓進行 接合的封裝製程的需求也不斷上升。
從過去的討論，希望能提供一種互補式金屬氧化物半導體相容，且可用于接合同類或不同類型的晶圓的接合製程。另外，也希望能夠提供一種具靈活度且提供氣密封裝和電接連的晶圓接合方法。
此實施例涉及晶圓接合層及製程其使用相同的接合層接合晶圓。
在一實施例中，該晶圓層包含一鍺層和一阻障層。該鍺層位於該阻障層上。在另一實施例中，該鍺層為單一的阻障層。在另一實施例中，該鍺層為鍺/鋁多層，其包含以交替方式與一系列薄鋁層穿插的一系列薄鍺層。該障礙層可為導電或不導電。
在一個實施例中，該晶圓接合製程包含了設置第一晶圓，設置第二晶圓並設置晶圓接合層。該晶圓接合層會分別形成於第一或第二晶圓的接觸表面層而成為互補式金屬氧化物半導體相容製程製法的一部分。
在另一個實施例中，該晶圓接合製程含設置第一晶圓，設置第二晶圓，並設置晶圓接合層。該晶圓接合層會分別形成於第一或第二晶圓的接觸表面層而成為互補式金屬氧化物半導體相容製程製法的一部分，而另一晶圓的表面接觸層則為鋁層。
這些和其他在此公開的實施例的優點及特徵，將會透過以下的敍述和圖示更加顯而易見。此外，這 裏需要被瞭解的是，在此所敍述的實施例的特徵並非彼此互斥，而能夠在不同的排列組合中存在。
100a‧‧‧晶圓組件
100b‧‧‧晶圓組件
100c‧‧‧晶圓組件
110‧‧‧第一晶圓、晶圓
120‧‧‧第二晶圓、晶圓
1201‧‧‧CMOS晶圓
1202‧‧‧CMOS晶圓
1203‧‧‧CMOS晶圓
130‧‧‧晶圓接合層
131‧‧‧接合層、鍺層
133‧‧‧阻障層、擴散阻障層
138‧‧‧鍺/鋁多層
1401‧‧‧第一接觸表面層
1402‧‧‧第二接觸表面層
150‧‧‧矽晶穿孔
206‧‧‧介電層
212‧‧‧通孔接面
235‧‧‧非晶矽層
在圖示中，相同的元件符號通常代表在不同的視角中相同的部份。此外，圖示不一定按比例繪製，相對地，重點通常放在說明本發明的原理。本發明的各種實施例，將參照以下圖示進行描述，其中：第1a至1c圖中為各種晶圓元件的實施例；第2a至2d圖為在共晶接合製程中的晶圓接合層的實施例的剖面圖；第3a至3d圖為共晶接合製程中的晶圓接合層的其他實施例的剖面圖。
實施例基本上將涉及晶圓接合方法，其使用可在晶圓的接觸表面層上形成共晶接合的個別的互補式金屬氧化物半導體代工相容材料，以使兩個或以上的同型或異型晶圓接合。在一些實施例中，該晶圓接合層和製程允許兩個或以上的同型或異型晶圓接合只要其中之一的晶圓其頂部/接觸表面為鋁層。在下面描述的晶圓接合層和製程將可相容於微機電(MEMS)和互補式金屬氧化物半導體(CMOS)之間。舉例而言，一些實施例涉及CMOS晶圓，其可進行垂直整合而達到提高MEMS效能的目的，以符合對功能添加、小型化、及更高的晶粒晶圓數(gross dies per wafer)的需求的提升。此外，此晶圓接合製程由於無需使 用昂貴的接合材料如金-錫或銀-錫，因此將能降低成本。
第1a至1c圖為各種晶圓級元件的實施例。 如第1a圖所示，第一晶圓110與第二晶圓120進行接合，形成了晶圓元件100a。在一個實施例中，該第一晶圓和該第二晶圓是不同類型的晶圓。在一個實施例中，該第一晶圓110是一MEMS晶圓而該第二晶圓120是一CMOS封蓋晶圓(cap wafer)。其他合適類型的晶圓也可能適用。在其他實施例中，該第一晶圓和該第二晶圓為同類型。該第一晶圓110藉由位於第一接觸表面層1401和第二接觸表面層1402之間的晶圓接合層130與該第二晶圓120接合。該第一接觸表面層1401位於該第一晶圓的表面上而該第二接觸表面層1402位於該第二晶圓120的表面上。
舉例而言，該第一接觸表面層1401可為該 第一晶圓110的最上面的導電層或金屬層，而第二接觸表面層1402則可為該第二晶圓120的最上面的導電層或金屬層。例如，若該第二晶圓120是CMOS封蓋晶圓，該第二接觸表面層1402可為CMOS晶圓的最頂端的金屬層或接觸墊(contact pad)，若該第一晶圓110為MEMS晶圓，該第一接觸表面層1401可以是MEMS晶圓最頂部的導電或金屬層，其已經適當地圖案化以匹配相對應的CMOS封蓋晶圓的第二接觸表面層1402。該第一晶圓的該第一接觸表面層1401與該第二晶圓的該第二接觸表面層1402的接合是經由設置一非原生(non-native)於該第一晶圓或該第二晶圓的晶圓接合層130而促成。例如，該晶圓接合層為個別設置的 且並非為該第一晶圓或該第二晶圓的接觸表面層或金屬化層的一部份。
第1b圖為另一個晶圓組件100b的實施例， 其類似於第1a圖所示的晶圓組件100a。共同元件將不再詳加說明。該晶圓組件100b標示出第一型晶圓110，其藉由一晶圓接合層130與第二型晶圓120接合。舉例而言，該第一型晶圓包括了MEMS晶圓，而該第二型晶圓，例如包括了多層CMOS封蓋晶圓120，用以產生一3D積體電路。為了說明的目的，三層CMOS晶圓1201，1202和1203被包含於多層CMOS封蓋晶圓120。
然而，應當理解的是，該多層CMOS封蓋 晶圓120可包括兩個或兩個以上的CMOS封蓋晶圓。多個CMOS晶圓中相鄰的CMOS晶圓是經由使用晶圓接合層130接合在一起，並經由矽晶穿孔(silicon vias)150互聯。如圖所示，晶圓接合層130也可用于接合同型的晶圓。而第1b圖為利用晶圓接合層130接合在一起的CMOS封蓋晶圓。 但是應當理解的是，晶圓接合層130還可以用於將兩個或兩個以上的MEMS晶圓接合在一起。在其他的實施例中，晶圓接合層130也可用于接合彼此為同類型的晶圓。
如第1c圖所示為另一實施例的晶圓組件 100c，與第1a圖所示的晶圓組件100a相似。因此，相同的組成將不多加描述或詳細說明。如第1c圖所示，第一晶圓110經由晶圓接合層130與第二晶圓120接合，類似於第1a圖所示。於一個實施例中，該第一晶圓110為一MEMS 晶圓而該第二晶圓120為虛擬封蓋晶圓(dummy cap wafer)。如圖所示，該MEMS晶圓110經由晶圓接合層130與測試封裝晶圓120進行接合。該虛擬封蓋晶圓120包括一半導體基板，如矽基板，且其中無嵌入任何裝置。因此，它僅用於當MEMS晶圓110和虛擬封蓋晶圓120之間沒有電接連時與MEMS晶圓110進行密封接合。儘管如此，電接點有時會存于該虛擬封蓋晶圓內部並將虛擬封蓋晶圓接地，因此使虛擬封蓋晶圓可作為一種保護屏障。
正如以上所述的所有晶圓組件中，該第一 晶圓乃經由晶圓接合層130與該第二晶圓進行接合。在一個實施例中，前述接觸表面層140中之一為一鋁層且前述晶圓接合層130也可用于接合該第一晶圓與該第二晶圓。 如前所述，該第一和第二晶圓可為同型或不同型。在一個實施例中，該晶圓接合層130可促進或使該第一和第二晶圓其中之一上鋁接觸表面層可與另外一晶圓的接觸表面層進行接合，且不論其材料的類型。如此一來，在一個實施例中，兩個待接合的晶圓中僅需前述第一晶圓或前述第二晶圓中之一含有鋁接觸表面層。儘管如此，前述晶圓接合層130也可使用於該第一晶圓和該第二晶圓皆具有一鋁接觸表面層。
第2a至2d圖為前述晶圓接合層130于一共 晶接合製程中的實施例剖面圖，可施行於任何晶圓組件如第1a至1c圖所示。如第2a圖所示，在使用晶圓接合層130于一接合製程中，在晶圓之間需要有大量的電接連以進行 鍵結。如第2a圖左側所示的第一晶圓和第二晶圓。該第一晶圓與該第二晶圓皆各自擁有各自的介電層(dielectric layer)206其分別位於晶圓110和接觸表面層1401之間，與晶圓120和接觸表面層1402之間。在一個實施例中，該第一晶圓是第一類型的晶圓而第二晶圓是第二類型的晶圓，其中所述第一類型和第二類型是不同的。舉例而言，該第一晶圓110和該第二晶圓120包含了一MEMS晶圓和一CMOS晶圓，但其他合適的晶圓組合也可能適用。另外，該第一類型和第二類型的晶圓可以是相同類型的。例如，該第一接觸表面層1401和第二接觸表面層1402包含鋁層。
該晶圓接合層130為非原生non-native於該 第一晶圓或該第二晶圓。例如，該晶圓接合層為個別設置且不為該第一晶圓或第二晶圓的接觸表面層或金屬化層的一部分。該晶圓接合層可沉積為一個別的層在晶圓110或晶圓120上。例如，晶圓接合層130可以沉積在晶圓110/120中互相面對的表面的任一面。在一個實施例中，該晶圓接合層130包含了一接合層131及一阻障層133。例如，接合層131包含一可與包含如鋁的接觸表面層形成共晶鍵結合的CMOS代工相容材料。在一個實施例中，接合層131包括了一鍺層。該鍺層沉積在阻障層133之上，而形成了前述晶圓接合層130。其他合適的金屬材料，其為CMOS代工相容且可與接觸表面材料形成共晶接合者，也可以作為接合層。在此實施例中，阻障層133為一擴散阻障層且包括一導電材料。阻障層133被包含于晶圓接合層130中， 于晶圓接合層130的鍺層131與任一晶圓110或120任一個上的鋁層140之間提供了一擴散阻障層，其取決於晶圓接合層130被沉積在哪一個晶圓上，以避免在共晶接合製程中因熔融鋁鍺而造成的過度的交互擴散(inter-diffusion)和擠壓。
在一個實施例中，阻障層包含鈦、氮化鈦、 鉭、氮化鉭、或任何其他相關合金。其他合適種類的擴散阻障層也可能可以適用，其取決於，如接合層的材料及阻障層的附著性質和蝕刻特性。如第2a圖所示，該晶圓接合層130形成於晶圓120的鋁層1402上。另外，該晶圓接合層也被設置在晶圓110的鋁層1401上。若晶圓接合層設置在晶圓110的鋁層1401上，則該晶圓接合層130的阻障層133將會直接地被設置在鋁層1401上方。藉由晶圓接合層130的使用，任意兩晶圓間的接合將更具靈活性，只要兩晶圓表面其中之一擁有鋁接觸表面層，接合便是可能的，無論此接合中是哪一個晶圓表面擁有鋁接觸表面層。在該第一晶圓和該第二晶圓是有源晶圓(active wafers)時，該晶圓接合層將在其包括的接合層及阻障層皆為導電的情況下時，為該第一晶圓和該第二活動晶圓間提供電接連。
如第2a圖的右側所示為在晶圓110和晶圓 120形成共晶接合後的晶圓接合層130。如圖所示，晶圓接合層130的鍺層131促進了與晶圓110的鋁層1401的接合，而晶圓接合層130的阻障層133則在與晶圓接合層130的鍺層進行反應時保護晶圓120的鋁層1402。這個製程因此 十分穩定，且不需要在進行共晶接合製程時進行太多控制。
第2b圖呈現了另一個實施例，其中，晶圓 接合層130包括如鍺層的單一接合層131，但晶圓110和120則具有與第2b圖相同的層。因此，相同的元件便不進行詳細說明。如第2b圖所示，晶圓接合層130是形成於晶圓120的鋁層1402上。可以理解的是，該晶圓接合層130也可能形成於晶圓110的鋁層1401上，而非在晶圓120上的鋁層1402之上。在此實施例中，有鑒於該晶圓接合層130包括了單一的鍺層；該共晶接合製程必須經由嚴謹的控制以確保接合時間不會過長、該鍺層131有足夠的厚度而不會被耗盡、以及在晶圓110和120上的鋁層140有足夠的厚度使鍺層至晶圓110與120上的鋁金屬層140進行均勻的擴散。透過使用單一的鍺層131作為接合層，可簡化接合的製程，且可適用於更為靈活的設計，以容納在兩晶圓110與120上的鍺層131和鋁層140之間有更大的交互擴散(inter-diffusion)。
第2c圖呈現另一個在共晶接合製程中的晶 圓接合層130的實施例，其與第2a及2b圖相似。因此，相同的元件便不進行詳細說明。如第2c圖所示，該晶圓接合層130包括接合層131和阻障層133。該接合層131和該阻障層133與第2a圖所示相同。此實施例所呈現的是在接合製程時，沒有許多的電接連在被接合的兩晶圓之間。因此，當晶圓110與第2a圖擁有相同的層時，晶圓120可以僅包括晶圓基板層(wafer substrate layer)。該晶圓基板包括 矽時是為佳。其餘合適的材料種類，例如，但不限於玻璃、絕緣層覆矽(silicon-on-insulator,SOI)、砷化鎵或者氮化鎵，皆可能適用。在此情況下，前述晶圓接合層130可能被直接沉積在該晶圓120的晶圓基板表面，同時晶圓接合層130中的擴散阻障層133則在晶圓接合層130的鍺層131與晶圓120的晶圓基板表面之間提供了更穩固或良好的附著力。
可以看出，以下的共晶接合，接合層131 如鍺層，與晶圓110的鋁層1401形成共晶接合。同時，晶圓層130上的阻障層133將保護晶圓120的基板或矽表面，避免其與晶圓接合層130的鍺層131反應。這個製程因此十分穩定，且進行共晶接合製程時需要較少的控制。
第2d圖呈現另一個實施例，其中晶圓接合 層130包括了一結合鍺金屬層131於一圖案化的非晶矽層235上。非晶矽層是絕緣體，它可以避免通過其而產生電接連。因此，通孔圖案可被形成在非晶矽層235上，以促進晶圓110與晶圓120兩者上的鋁層140之間通過晶圓接合層130的鍺層131的電接連。在一個實施例中，通孔被成形於前述非晶矽層235上，而鍺層131被沉積在該晶圓的接觸表面層中其中之一。
在此實施例中，晶圓110和晶圓120與第 2a圖所示的層相同。因此，如第2a圖所示，晶圓接合層130形成於晶圓120的鋁層1402上，但它在另一個實施例中，也可以形成於晶圓110的鋁層1401上。參考第2d圖 的右側，一導電的通孔接面(via contact)212在經由前述晶圓接合層130的鍺/鋁多層138與晶圓110和晶圓120上的鋁層140間的擴散所產生的晶圓110和晶圓120的共晶接合之後形成。該通孔接面212提供了在前述第一晶圓與第二晶圓之間的電接連。另外，該製程也非常穩定，在此過程中不需要太多的控制，而是藉由非晶矽控制鍺在鋁層1402的擴散。
第3a至3d圖為在共晶接合製程中晶圓接合 層130於其他實施例中的剖面圖，其可應用於任意前述晶圓組件如第1a至1c圖。第3a至3d圖也與第2a至2d圖也相似，除了該接合層包括單一CMOS代工相容材料被取代為CMOS代工相容材料堆疊。例如，晶圓接合層130之鍺層131被替換為鍺/鋁多層138以促進晶圓接合層130和晶圓110與120的鋁層140的擴散更為均勻，從而得到更穩固的接合。如圖所示，鍺/鋁多層138可包括以交替方式與一系列薄鋁層交插的一系列薄鍺層。
第3a圖顯示出晶圓接合層130在接合製程 中，在欲進行接合的晶圓之間需要大量的電接連。如第3a圖左側所示，其具有第一晶圓110與第二晶圓120。在一個實施例中，該第一晶圓與該第二晶圓為不同類型的晶圓。在一個實施例中，該第一晶圓110為MEMS晶圓，而第二晶圓120為CMOS封蓋晶圓。其他合適種類的晶圓也可能適用於此。在其他實施例中，該第一晶圓與該第二晶圓為相同類型的晶圓。該第一晶圓110與該第二晶圓120 個別具有介電層206，其成形於該晶圓110與接觸表面層1401之間和晶圓120與接觸表面層1402之間。舉例而言，該接觸表面層1401與1402包括鋁層。其他合適種類的導電表面層也可能適用於此。
如第3a圖所示，晶圓接合層130包括一用 以和接觸表面材料形成共晶接合的CMOS代工相容材料堆疊138和一可沉積在任一晶圓110或120上的阻障層133。 晶圓接合層130可以被沉積在晶圓110/120的任何鋁表面上。在一個實施例中，該CMOS加代工相容材料堆疊138包括鍺/鋁多層138，且前述阻障層133為一擴散阻障層，與上方的第2a圖所述相同。其他合適的材料也可以用以形成CMOS加代工相容材料堆疊。如第3a圖所示，晶圓接合層130成形於晶圓120的鋁層1402上，但在另一個實施例中，也可成形於晶圓110的鋁層1401上。
如第3a圖的右側所示為在晶圓110和晶圓 120共晶接合形成後的晶圓接合層130。正如所見，晶圓接合層130的該鍺/鋁多層138促進了與晶圓110的鋁層1401的接合，同時晶圓接合層130的阻障層133保護了晶圓120的鋁層1402免於與晶圓接合層130的鍺/鋁多層進行反應。 正如所見，鍺/鋁多層138在擴散進晶圓110的鋁層1401之前先均勻地相互擴散。因此這個製程是非常穩定的，且不需要在共晶接合製程中經過太多控制。前述晶圓接合層130便接合了該第一晶圓與該第二晶圓。在第一晶圓和第二晶圓都是有源晶圓的情況下，該晶圓接合層130也在該 第一晶圓和該第二有源晶圓之間提供電接連，而晶圓接合層所包括的接合層與阻障層皆為導電。
第3b圖為一個替代的實施例，其中，前述 晶圓接合層130包括鍺/鋁多層138，但晶圓110與晶圓120則與第3a圖具有相同的層。因此，相同的元件便不進行詳細說明。如第3b圖所示，晶圓接合層130形成於晶圓120的鋁層1402上，但在另一個實施例中，也可以成形於晶圓110的鋁層1401上，與第2b圖所示相似。例如，如第2b圖所示的製程，其中晶圓接合層130包括單一的鍺層131；共晶接合製程的該製程參數必須經過非常嚴謹的控制以確保鍺層131至晶圓110和晶圓120的鋁層140能夠均勻的擴散。
相反地，如第3b圖所示製程，顯示出使用 鍺/鋁多層138不需要經由過多的控制來確保共晶接合製程中鍺/鋁多層138至晶圓110和晶圓120的鋁層140能夠均勻的擴散，從而省下時間及人力而降低成本。正如所見，該鍺/鋁多層138將在擴散進晶圓110與晶圓120的鋁層140前先進行均勻地相互擴散。這使互連金屬化能有更好的控制。
如第3c圖所示為晶圓接合層130在共晶接 合製程中的又一實施例，其與第3a和3b圖所述相似。因此，相同的元件便不進行詳細說明。如第3c圖所示，晶圓接合層130包括該鍺/鋁多層138及阻障層133。此實施例顯示出一接合製程，其在兩欲進行接合的晶圓間無許多電 接連。因此，雖然晶圓110與第3a圖所示有相同的層，晶圓120則有可能僅包括一前述晶圓基板層。
晶圓基板以包含矽為佳。但也應瞭解到其 他合適的材料，如但不限於玻璃、絕緣層覆矽(silicon-on-insulator,SOI)、砷化鎵或者氮化鎵，皆可能適用。在此情況下，該晶圓接合層130可直接沉積在晶圓120的晶圓基板表面上，而在晶圓接合層130中的擴散阻障層133則在晶圓接合層130的鍺/鋁多層138及晶圓120的基板表面之間提供更穩固或良好的附著力。
正如所見，在共晶鍵接後，前述晶圓接合 層130的鍺/鋁多層138促進與晶圓110的鋁層1401的鍵接，同時前述晶圓接合層130的阻障層133則為晶圓120的基板或矽表面提供保護，以免於和該晶圓接合層130的鍺/鋁多層138反應。此方法因此非常穩定且不需在共晶接合製程時進行太多的控制。如圖所示，該鍺/鋁多層138將會在擴散進晶圓110和120的鋁層140之前先均勻地擴散。這使互連金屬化能有更好的控制。
如第3d圖所示為又一實施例，其中，前述 晶圓接合層130包括一組合的鍺/鋁多層138和一圖案化的非晶矽層235。而非晶矽層為絕緣體，它可以防止通過其所產生的電接連。因此，通孔圖案也可形成在非晶矽層235上，以促進晶圓110和晶圓120兩者的鋁層140通過晶圓接合層130的鍺/鋁多層138的電接連。
在本實施例中，晶圓110和120包括與第 3a圖相同的層。因此，如第3a圖所示，該晶圓接合層130形成於晶圓120的鋁層1402上，但在另一個實施例中，也可形成於晶圓110的鋁層1401上。如第3d圖的右側所示，一導電通孔接面212在經由前述晶圓接合層130的鍺/鋁多層138與晶圓110和晶圓120上的鋁層140間的擴散所產生的晶圓110和晶圓120的共晶接合之後形成。這個製程因此十分穩定，而且不需要在製程中進行太多控制。
在以上所述的所有實施例中，晶圓接合層 130可以被沉積為CMOS相容製程的製程製法的一部分，從而提高加工製程的處理能力。在一個實施例中，前述晶圓接合層130的接合層與阻障層，如鍺、鈦、和鉭金屬層，舉例而言，是以蒸鍍或濺鍍形成。在另一個實施例中，前述晶圓接合層的非晶矽層是以等離子化學氣相沉積技術成形。其他合適類型的技術也可能可以用以形成晶圓接合層130。在一個實施例中，晶圓接合層130的厚度約為0.3至0.9微米。其他在合適厚度範圍的晶圓接合層也可能可以適用。此處的晶圓接合層130包括在阻障層133上的鍺金屬層131的組合，該鍺層131的厚度在0.2至0.6微米為佳，而該阻障層133的厚度在0.1至0.3微米為佳。
其中，上述晶圓接合層130包括在非晶矽層 235上的鍺金屬層131的組合，該鍺層131的厚度在0.2至0.6微米為佳，而該非晶矽層235的厚度則在0.2至1.0微米為佳。其他在合適厚度範圍的鍺層與非晶矽層也可能可以適用。此處晶圓接合層130包括鍺/鋁多層138，該薄鍺 層和該薄鋁層各約為0.1至0.2微米。其他在合適厚度範圍的鍺層與非晶矽層也可能為有用的，如於鍺層使其可以與晶圓上的該鋁層140擁有良好的共晶接合。
本發明可以以其他特定形式來體現而不脫離其精神或本質特徵。因此，上述實施例，乃為在全方面地說明本發明，而非用於限制本發明。因此，本發明的權利保護範圍應如申請專利範圍所述，而非由前面的描述，且所有衍生的等效的手段和範圍的變化也被包含在申請專利範圍中。
100a‧‧‧晶圓組件
110‧‧‧第一晶圓、晶圓
120‧‧‧第二晶圓、晶圓
130‧‧‧晶圓接合層
1401‧‧‧第一接觸表面層
1402‧‧‧第二接觸表面層

Claims (15)

  1. 一種晶圓接合製程，包含：設置第一晶圓；設置第二晶圓；以及設置晶圓接合層，其中，該晶圓接合層係分開設置在該第一或第二晶圓的接觸表面層上，以作為CMOS相容製程製法的一部分且並非為該第一晶圓或該第二晶圓的該接觸表面層或金屬化層的一部份；其中該晶圓接合層包含阻障層以及沉積在該阻障層上的接合層。
  2. 如申請專利範圍第1項所述之晶圓接合製程，其中，該晶圓接合層係設置於該第二晶圓的該接觸表面層上，以及該第一晶圓的該接觸表面層為鋁層。
  3. 如申請專利範圍第1項所述之晶圓接合製程，其中，該晶圓接合層包含為CMOS代工相容材料的接合層，係與該第一或第二晶圓的鋁接觸表面層形成共晶接合。
  4. 如申請專利範圍第1項所述之晶圓接合製程，其中，該接合層至少包含鍺層。
  5. 如申請專利範圍第1項所述之晶圓接合製程，其中，該晶圓接合層包含鍺層和該阻障層。
  6. 如申請專利範圍第5項所述之晶圓接合製程，其中，該阻障層包含鈦、氮化鈦、鉭、氮化鉭、或其合金。
  7. 如申請專利範圍第5項所述之晶圓接合製程，其中， 該鍺層的厚度為約0.2至0.6微米，而該阻障層的厚度以在0.1至0.3微米為佳。
  8. 如申請專利範圍第1項所述之晶圓接合製程，其中，該第一和第二晶圓包含相同類型的晶圓。
  9. 如申請專利範圍第1項所述之晶圓接合製程，其中，該第一和第二晶圓包含CMOS晶圓。
  10. 如申請專利範圍第1項所述之晶圓接合製程，其中，該第一晶圓包含CMOS晶圓，以及該第二晶圓包含MEMS晶圓。
  11. 一種晶圓接合製程，包含：設置第一晶圓；設置第二晶圓；以及設置晶圓接合層，其中，該晶圓接合層係分開設置在該第一或第二晶圓的接觸表面層上，以作為CMOS相容製程製法的一部分且並非為該第一晶圓或該第二晶圓的該接觸表面層或金屬化層的一部份，其中，另一個晶圓的該接觸層為鋁層；其中該晶圓接合層包含阻障層以及沉積在該阻障層上的接合層。
  12. 如申請專利範圍第11項所述之晶圓接合製程，其中，該晶圓接合層包含鍺/鋁多層，該鍺/鋁多層包括以交替方式與一系列薄鋁層穿插的一系列薄鍺層。
  13. 如申請專利範圍第12項所述之晶圓接合製程，其中，該晶圓接合層包含該鍺/鋁多層和該阻障層。
  14. 如申請專利範圍第12項所述之晶圓接合製程，其中，該晶圓接合層包含該鍺/鋁多層和非晶矽層。
  15. 如申請專利範圍第12項所述之晶圓接合製程，其中，該第一晶圓包含CMOS晶圓，以及該第二晶圓包含MEMS晶圓。
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