TWI502700B - 半導體基板、混成接合結構及混成接合基板的形成方法 - Google Patents

半導體基板、混成接合結構及混成接合基板的形成方法 Download PDF

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TWI502700B
TWI502700B TW102134695A TW102134695A TWI502700B TW I502700 B TWI502700 B TW I502700B TW 102134695 A TW102134695 A TW 102134695A TW 102134695 A TW102134695 A TW 102134695A TW I502700 B TWI502700 B TW I502700B
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Taiwan
Prior art keywords
barrier layer
substrate
conductive pad
diffusion barrier
conductive
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TW102134695A
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English (en)
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TW201417227A (zh
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Ping Yin Liu
Szu Ying Chen
Chen Jong Wang
Chih Hui Huang
Xin Hua Huang
Lan Lin Chao
Yeur Luen Tu
Chia Shiung Tsai
Xiaomeng Chen
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Taiwan Semiconductor Mfg Co Ltd
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Publication of TW201417227A publication Critical patent/TW201417227A/zh
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Description

半導體基板、混成接合結構及混成接合基板的形成方法
本發明係有關於一種半導體基板、混成接合結構及混成接合基板的形成方法，特別係有關於一種用於三維積體電路之半導體基板、混成接合結構及混成接合基板的形成方法。
半導體裝置係用於例如個人電腦、手機、數位相機和其他電子設備之不同的電子應用。通常會利用於半導體基板上方依序沉積絕緣或介電層、導層和半導體層之材料，且利用微影製程圖案化不同的材料層，以於半導體基板上形成電路構件和元件之方式來製造半導體裝置。通常會於一單一半導體晶圓上製造許多積體電路，且藉由沿位於積體電路之間的一切割道切割，以分割位於半導體晶圓上的各別晶片。上述各別晶片通常會分開封裝，例如多重晶片模組封裝，或其他類型封裝。
半導體產業係藉由持續縮小特徵尺寸，其允許更多電子構件被積集於一給定的區域，以持續改善不同電子構件(例如電晶體、二極體、電阻、電容等)的積集密度。在一些應用中，這些較小的電子構件也會需要使用面積較先前封裝體小 的較小封裝。
三維積體電路(3DICs)為半導體封裝的最新發展技術，其可將多個半導體晶片彼此堆疊，例如堆疊式封裝層疊(PoP)或系統級封裝(SoP)技術。一些三維積體電路係藉由在在晶片等級下於晶片上置放晶片。因為三維積體電路在例如堆疊的晶片之間的內連線的長度縮短，所以三維積體電路係提供較佳的積集密度以及其他的優點，例如更快的速度，更高的頻寬。然而，三維積體電路仍會面臨更多的挑戰。
有鑑於此，本發明揭露之一實施例係提供一種半導體基板，上述半導體基板包括一導電墊，形成於上述半導體基板的一表面中且接近上述半導體基板的上述表面，其中上述導電墊的一表面係暴露出來。上述導電墊的上述表面係用於與另一基板的另一導電墊混成接合。上述半導體基板也包括一第一阻障層，襯墊於上述導電墊；一第二阻障層，圍繞於上述導電墊，其中上述第二阻障層的一表面對齊於上述導電墊的上述表面。
本發明揭露之另一實施例係提供一種混成接合結構，上述混成接合結構包括一第一基板的一第一導電墊，接合至一第二基板的一第二導電墊，其中上述第一導電墊藉由一第一擴散阻障層與殘留的上述第一基板隔開。上述第二導電墊藉由一第二擴散阻障層與殘留的上述第二基板隔開。上述混成接合結構還包括上述第一基板的一第一介電區，接合至上述第二基板的一第二介電區。上述混成接合結構還包括上述第一基板 的一第三擴散阻障層，接合至上述第二基板的一第三介電區。上述第三擴散阻障層係圍繞上述第一導電墊。
本發明揭露之另一實施例係提供一種用於混成接合的一基板的一阻障層的形成方法。上述方法包括提供具一導電結構的上述基板。上述方法包括於上述基板的一表面上方沉積一蝕刻停止層，其中上述蝕刻停止層與導電結構接觸。上述方法還包括於上述蝕刻停止層上方沉積一介電材料；於上述介電材料上方沉積一擴散阻障層。上述方法更包括形成內嵌於依序沉積的上述蝕刻停止層、上述介電材料和上述擴散阻障層中的一導電墊，其中上述擴散阻障層的一表面對齊於上述導電墊的一表面。
本發明揭露之又另一實施例係提供一種混成接合的一基板的一阻障層的形成方法。上述方法包括提供具一導電結構的上述基板；於一蝕刻停止層上方沉積一介電材料。上述方法還包括圖案化上述基板以於上述介電材料中形成一開口，其中上述開口暴露上述導電結構。上述方法還包括沉積一第一擴散阻障層以襯墊上述開口；蝕刻位於上述開口外的一部分上述第一擴散阻障層，且移除上述開口的一底面。上述蝕刻暴露上述導電結構，其中上述第一擴散阻障層的一殘留部分覆蓋上述開口的側壁。另外，上述方法包括上述蝕刻之後沉積一第二擴散阻障層，其中上述第二擴散阻障層覆蓋上述第一擴散阻障層的上述殘留部分的暴露出來的表面。另外，上述方法包括沉積一導電材料以填充上述開口中的間隙；利用一平坦化製程以移除位於上述開口外的上述導電材料和上述第二擴散阻 障層，以形成一導電墊，且上述第一擴散阻障層係圍繞上述第二擴散阻障層和上述導電墊。
100、150、1001 、1501 、1002 、1502 、1502 ’、1503 、1003 ‧‧‧半導體晶片
102‧‧‧工件
104‧‧‧元件區
105‧‧‧基板穿孔
106‧‧‧金屬結構
108‧‧‧導線
110、156‧‧‧介層孔
111、1111 、1112 、1312 、1113 ‧‧‧開口
112、152、1121 、1521 、1122 、1522 、1523 、1523 ’‧‧‧導電墊
113、153‧‧‧阻障層
114、154、114L ‧‧‧絕緣材料
114U 、114T ‧‧‧介電材料
115‧‧‧含銅導電材料
121、151、121B 、121T ‧‧‧蝕刻停止層
1601 、160T 、160B 、160T ’、160B ’‧‧‧擴散阻障層
161‧‧‧平坦化停止層
164‧‧‧角落
1000‧‧‧晶圓
Ctop 、Cbot ‧‧‧中心
D、A、B、N、O、P、QR 、R、1100、1500‧‧‧區域
T、T’、T*、T*’‧‧‧厚度
W1 、W2 、W3 、Wtop1 、Wbot1 、Wtop2 、Wbot2 、Wtop3 、Wbot3 ‧‧‧寬度
第1圖為本發明一實施例之一半導體晶片的部分剖面圖。
第2A圖為本發明一些實施例之一接合結構的剖面圖。
第2B圖為本發明一些實施例之未對準的一接合結構的剖面圖。
第3圖為本發明一些實施例之一接合結構的剖面圖。
第4A-4E圖為本發明一些實施例之包圍一導電墊的一頂部的一擴散阻障層的形成方法。
第5A和5B圖為本發明一些實施例之接合在一起的兩個晶片的剖面圖。
第6A-6G圖為本發明一些實施例之包圍一導電墊的一頂部的一擴散阻障層的形成方法。
第7A和7B圖為本發明一些實施例之兩個相鄰的導電墊的上視圖。
第8A和8B圖為本發明一些實施例之接合在一起的兩個晶片的剖面圖。
第9A-9F圖為本發明一些實施例之包圍一導電墊的一頂部的一擴散阻障層的形成方法。
第10A圖為本發明一些實施例之一晶片的一區域的上視圖。
第10B圖為第10A圖的剖面圖。
第10C圖第10A和10B圖中的一晶片的一區域的上視圖。
以下以各實施例詳細說明並伴隨著圖式說明之範例，做為本發明之參考依據。在圖式或說明書描述中，相似或相同之部分皆使用相同之圖號。且在圖式中，實施例之形狀或是厚度可擴大，並以簡化或是方便標示。再者，圖式中各元件之部分將以分別描述說明之，值得注意的是，圖中未繪示或描述之元件，為所屬技術領域中具有通常知識者所知的形式。
混成接合(Hybrid Bonding)為三維積體電路的接合程序的一種類型，其中兩個半導體晶圓係使用一混成接合技術接合在一起。利用混成接合技術形成的一些用於三維積體電路的方法和結構係描述於以下專利：於西元2012年6月5日申請之美國專利申請號為13/488,745，發明名稱為”三維積體電路結構和半導體晶圓的混成接合方法”(U.S.Serial No.13/488,745,filed on June 5,2012,entitled,“Three Dimensional Integrated Circuit Structures and Hybrid Bonding Methods for Semiconductor Wafers”)之美國專利申請案，以及於西元2012年6月5日申請之美國專利申請號為13/542,507，發明名稱為”半導體晶圓的混成接合系統和方法”之美國專利申請案(U.S.Serial No.13/542,507,filed on July 5,2012,entitled“Hybrid Bonding Systems and Methods for Semiconductor Wafers”)。上述兩者美國專利申請案的全部內容在此係一起做為參考。
請參考第1圖，其顯示本發明一實施例之一半導體晶片100的部分剖面圖。類似於所示半導體晶片100的兩個或多 個半導體晶片可垂直耦接以形成一三維積體電路(3DIC)結構。半導體晶片100可包括一工件102。上述工件102可包括一半導體結構，其包括矽或其他半導體材料，且工件102例如可被一絕緣層覆蓋。上述工件102可包括位於單晶矽上方的氧化矽，可使用例如化合物半導體、砷化鎵、磷化銦、矽/鍺、或碳化矽來代替矽。上述工件102可包括例如絕緣層上覆矽(SOI)基板或絕緣層上覆鍺(GOI)基板。
上述工件102可包括一元件區104，形成接近於工件102的一頂面。上述元件區104可包括主動構件或電路，例如導電物、摻雜區、電阻、電容和例如電晶體、二極體等其他半導體元件。在本發明一些實施例中，上述元件區104例如可於一前段製程(FEOL)中形成於工件102的上方。在本發明一些實施例中，上述工件102可包括以一導電材料填充的基板穿孔(TSV)105，基板穿孔105係提供上述工件102底側至頂側的連接。
一金屬結構106，係形成於工件102的上方，例如可位於工件102的元件區104的上方。在本發明一些實施例中，上述金屬結構106例如可於一後段製程(BEOL)中形成於工件102的上方。金屬結構106可包括導電物，例如導線108、介層孔110和形成於為一介電材料之絕緣材料114中的導電墊112。在本發明一些實施例中，絕緣材料114可由氧化矽形成。在本發明一些實施例中，絕緣材料114可包括介電材料的多重介電層。多重介電層的一或多層可由低介電常數材料形成。在本發明一些實施例中，多重介電層的一頂層介電層可由二氧化矽 形成。如第1圖所示，導電墊112可為接觸墊或接合墊，形成於半導體晶片100的一頂面。一些介層孔110係將導電墊112耦接至金屬結構106中的導線108，且對齊於導線108的其他介層孔110將導電墊112耦接至工件102的元件區104。介層孔110也可將位於不同金屬層(圖未顯示)中的導線108連接在一起。導電物包括通常使用於後段製程(BEOL)中的導電材料，例如銅(Cu)、鋁(Al)、鎢(W)、鈦(Ti)、氮化鈦(TiN)、鉭(Ta)、氮化鉭(TaN)或上述多層或上述組合。
在本發明一實施例中，導電墊112係設置接近於金屬結構106的一頂面，且包括銅或銅合金，導電墊112藉由一擴散阻障層(圖未顯示)與絕緣材料114絕緣。金屬結構106可包括其他組合且可包括例如一或多個導線和介層孔層。在本發明其他實施例中，一些半導體晶片100可具有三個導線和介層孔層，或者四個或多個導線和介層孔層。
如上所述，類似於所示半導體晶片100的兩個或多個半導體晶片可垂直耦接以形成一三維積體電路(3DIC)結構。半導體晶片100可包括一工件102。第1圖的區域M會用於本發明不同實施例之混成接合機制。區域M可包括設置於一介層孔110上方的導電墊112。導電墊112和介層孔110會被一絕緣材料114圍繞。
第2A圖為本發明一些實施例之一接合結構的剖面圖。上述接合結構接近半導體晶片100的區域M。如上所述，區域M可包括設置於一介層孔110上方的導電墊112。導電墊112和介層孔110被絕緣材料114圍繞。係以銅或銅合金填充導 電墊112。依據本發明一個或多個實施例，絕緣材料114由二氧化矽形成。第2A圖顯示導電墊112和152係彼此接合，且絕緣材料114和154係彼此接合。由於介電材料係接合至介電材料，而導電材料係接合至導電材料，則上述晶圓與晶圓的接合製程為一混成接合製程。
因為考慮銅會在二氧化矽中擴散，一阻障層113係沉積於且襯墊於開口111中。係填充開口111以形成導電墊112。阻障層113將含銅的導電墊112與絕緣材料114隔開。依據本發明一個或多個實施例，阻障層113由銅擴散阻障材料形成。在本發明一些實施例中，阻障層113厚度為10Å至1000Å。
第2A圖顯示半導體晶片100接合至半導體晶片150，其以半導體晶片100的導電墊112接合至半導體晶片150的導電墊152。導電墊152由銅或銅合金形成。阻障層153也將含銅的導電墊152與絕緣材料154隔開，阻障層153係圍繞導電墊152和介層孔156。半導體晶片100和半導體晶片150的接合製程係包括將例如導電墊112、152的結構對齊於兩個晶片上，以使導電區接合至導電區，例如導電墊112接合至導電墊152，且使絕緣區接合至絕緣區。例如絕緣材料114接合至絕緣材料154。對齊晶圓之後，半導體晶片100和半導體晶片150係一起加壓，且會升溫以允許這些晶圓中的導電層之間和絕緣層之間產生接合。如上述，混成接合製程的詳細說明會說明於以下專利：於西元2012年6月5日申請之美國專利申請號為13/488,745，發明名稱為”三維積體電路結構和半導體晶圓的混成接合方法”(U.S.Serial No.13/488,745,filed on June 5,2012,entitled, “Three Dimensional Integrated Circuit Structures and Hybrid Bonding Methods for Semiconductor Wafers”)之美國專利申請案，以及於西元2012年6月5日申請之美國專利申請號為13/542,507，發明名稱為”半導體晶圓的混成接合系統和方法”之美國專利申請案(U.S.Serial No.13/542,507,filed on July 5,2012,entitled“Hybrid Bonding Systems and Methods for Semiconductor Wafers”)。上述兩者美國專利申請案的全部內容在此係一起做為參考。
第2A圖顯示導電墊152的表面與導電墊112的表面一致，且於導電墊112和152兩者的含銅材料會被阻障層113和153包圍。導電墊112和152不會與絕緣材料114和154接觸。
然而，因為製程變異，所以半導體晶片100和半導體晶片150的對準會產生位移。第2B圖的接合結構係類似於第2A圖的接合結構，且第2B圖為本發明一些實施例未對準的接合結構。第2B圖顯示因為對準及/或製程變異，導電墊112沿一方向(例如向右)相對於導電墊152些微移動。最後，部分導電墊152暴露於絕緣材料114的區域N，且部分導電墊112暴露於絕緣材料154的區域O。這種暴露的情形會導致銅(Cu)擴散，而銅擴散會傷害元件性能。
第3圖為本發明一些實施例之一半導體晶片1501 的一區域接合至半導體晶片1001 的剖面圖。第3圖顯示導電墊1521 的寬度Wtop1 係大於導電墊1121 的寬度Wbot1 。雖然第3圖中導電墊1521 的中心Ctop 係對齊於導電墊1121 的的中心Cbot ，但是可能會因為對準及/或製程變異而產生對準錯誤(mis-alignment)。為 了避免銅擴散，一擴散阻障層1601 係形成於半導體晶片1001 的一表面，且包圍導電墊1121 的頂部分。第3圖顯示擴散阻障層1601 會將未被導電墊1121 覆蓋的導電墊1521 的一表面與絕緣材料114隔開，以避免銅擴散。
擴散阻障層1601 可由任何類型可由阻擋銅擴散的材料形成，例如氮化矽(SiN)、氮氧化矽(SiON)、氮化鉭(TaN)、氮化鈦(TiN)、氮化鋁(AlN)等。在本發明一些實施例中，擴散阻障層1601 可由聚合物(polymers)形成，例如可阻擋銅擴散的苯並環丁烯(benzocyclobutene，BCB)聚合物介電質。上述用於銅擴散阻障物的材料可為導電，例如氮化鉭(TaN)、氮化鈦(TiN)、氮化鋁(AlN)，或為介電，例如氮化矽(SiN)、氮氧化矽(SiON)。如第3圖所示的本發明實施例中，擴散阻障層1601 可為介電質以避免相鄰導電物之間的短路。擴散阻障層1601 會接合至絕緣材料154。例如擴散阻障層1601 之使用的擴散阻障層，應接合至其他半導體晶片的材料。舉例來說，擴散阻障層1601 應接合至絕緣材料154。氮化矽(SiN)或氮氧化矽(SiON)接合至可使用為絕緣材料154的二氧化矽(SiO2 )。氮化鉭(TaN)、氮化鈦(TiN)或氮化鋁(AlN)接合至二氧化矽(SiO2 )。第3圖顯示位於半導體晶片1001 中的選擇性元件蝕刻停止層121，和位於半導體晶片1501 中的選擇性元件蝕刻停止層151。
因為擴散阻障層1601 只形成於半導體晶片1001 上，且半導體晶片1001 的導電墊1121 小於相對的導電墊1521 ，所以如果因對準錯誤(mis-alignment)使導電墊1121 的一部分位移至導電墊1521 的邊界外，則會有銅擴散的風險。如第3圖所 示，為了完美的對準，導電墊1121 的的中心Cbot 係對準導電墊1521 的中心Ctop 。導電墊1521 從邊界至中心的一距離為Wtop1 /2。導電墊1121 從邊界至中心的一距離為Wbot1 /2。如果半導體晶片1001 和1501 的其中一個位移的距離大於Wtop1 /2-Wbot1 /2，則導電墊1121 的一部分會位移至導電墊1521 的邊界外，其會導致銅擴散。因此，Wtop1 /2-Wbot1 /2係大於對準控制極限值。在本發明一些實施例中，Wtop1 /2-Wbot1 /2係大於0.01μm。在本發明一些實施例中，類似於擴散阻障層1601 的一擴散阻障層也會形成於半導體晶片1501 的表面上。在本實施例中，半導體晶片1001 的於擴散阻障層1601 會接合至半導體晶片1501 的於擴散阻障層。
第4A-4E圖依序為本發明一些實施例之位於半導體晶片1001 的表面上方且包圍一導電墊的一頂部的一擴散阻障層1601 的形成方法。第4A圖係顯示具嵌入一介電材料114U 中的一介層孔110的一部分半導體晶片1001 。如第1圖所示，可形成元件區104、基板穿孔105和其他內連線層。為了簡單說明起見，第4A圖僅顯示一個介層孔110。提供如第1圖所示的半導體晶片1001 之後，如第4B圖所示，依序於半導體晶片1001 的表面上方沉積一介電材料114T ，及一擴散阻障層(保護層)1601 。蝕刻停止層121可為一介電薄膜且可用做為圖案化導電墊1121 的一開口111之蝕刻製程期間的蝕刻停止物。在本發明一些實施例中，蝕刻停止層121可由碳化矽形成，且其厚度可從10Å至5000Å。在本發明一些實施例中，介電材料114T 可由二氧化矽形成，且其厚度可從50Å至10000Å。擴散阻障層(保護層)1601 可由氮化矽或氮氧化矽形成，且其厚度可從5Å至1000Å。
如第4C圖所示，沉積蝕刻停止層121、介電材料114T ，及擴散阻障層(保護層)1601 之後，圖案化且蝕刻半導體晶片1001 以形成開口1111 。在本發明一些實施例中，開口1111 的寬度W1 可從0.1μm至50μm。開口1111 係暴露出介層孔110的一頂部。形成開口1111 之後，沉積阻障層113以襯墊開口1111 ，且沉積用於導電墊1121 的例如銅或銅合金的一導電材料115，以填充開口1111 。在本發明一些實施例中，由氮化鉭(TaN)形成的阻障層113的厚度可從50Å至1000Å。可利用物理氣相沉積法(PVD)或其他可使用的方法來形成上述氮化鉭(TaN)。可於阻障層113上沉積一薄銅種晶層(圖未顯示)以協助導電墊1121 的導電材料的形成。可利用物理氣相沉積法(PVD)來形成上述薄銅種晶層，且其厚度可從10Å至500Å。然後沉積導電墊1121 的含銅導電材料115以填充開口1111 。在本發明一些實施例中，可利用電鍍法來形成導電墊1121 的含銅導電材料115。因為銅種晶層會與填充開口1111 的含銅導電材料115合併，所以銅種晶層不會顯示於第4D圖中。
然後，可利用化學機械研磨法(CMP)或蝕刻法來移除位於開口1111 外部的含銅導電材料115和阻障層113。第4E圖係顯示本發明一些實施例之半導體晶片1001 在進行上述移除製程之後的剖面圖。第4E圖係顯示擴散阻障層1601 會在進行上述移除製程之後暴露出來。擴散阻障層1601 會阻擋銅從上述半導體晶片1501 擴散至半導體晶片1001 的元件區。
第5A圖係顯示本發明一些實施例之半導體晶片 1502 接合至半導體晶片1002 的剖面圖。第5A係顯示導電墊1522 的寬度Wtop2 大約相同於半導體晶片1002 的導電墊1122 的寬度Wbot2 。擴散阻障層160T 係形成於導電墊1522 上，且擴散阻障層160B 係形成於導電墊1122 上。擴散阻障層160B 的一部分係沉積接近於蝕刻停止層121B 。擴散阻障層160T 也包圍和圍繞導電墊1522 。擴散阻障層160T 係沉積接近於蝕刻停止層121T 。擴散阻障層160T 和擴散阻障層160B 可為介電質，且可擇自做為擴散阻障層1601 的上述材料來形成擴散阻障層160T 和擴散阻障層160B 。
擴散阻障層160T 和160B 可避免因導電墊1122 和1522 的對準錯誤造成的銅擴散。擴散阻障層的厚度T應夠大以掩蓋對準變異量。在本發明一些實施例中，厚度T可大於0.01μm，且其為導電墊1122 和1522 的對準控制極限。
第5B圖係顯示本發明一些實施例之半導體晶片1502 ’接合至半導體晶片1002 的剖面圖。第5B圖類似於第5A圖，除了第5B圖沒有擴散阻障層160T 圍繞導電墊1522 ’之外。擴散阻障層160B 係包圍及環繞導電墊1122 。擴散阻障層160B 可避免因導電墊1122 和1522 的對準錯誤造成的銅擴散。擴散阻障層160B 的厚度T應夠大以掩蓋對準變異量。在本發明一些實施例中，厚度T可大於0.01μm，且其為導電墊1122 和1522 的對準控制極限。
第6A-6G圖為本發明一些實施例之位於半導體晶片1002 上方且包圍導電墊1122 的一頂部的一擴散阻障層160B 的形成方法。第6A圖係顯示具介層孔110的一部分半導體晶片 1002 ，上述之介層孔110係嵌入於一介電(絕緣)材料114U 中。提供如第6A圖所示的半導體晶片1002 之後，如第6B圖所示，於半導體晶片1002 的表面上依序沉積一蝕刻停止層121和一介電(絕緣)材料(或層)114T 。
如第6C圖所示，在本發明一些實施例中，沉積蝕刻停止層121和介電(絕緣)材料114T 之後，圖案化且蝕刻半導體晶片1002 以形成開口1112 。開口1112 具有一寬度W2 ，範圍從0.1μm至50μm。開口1112 係暴露介層孔110的頂部。形成開口1112 之後，沉積一阻障層113以襯墊開口1112 ，且沉積用於導電墊1122 之例如銅或銅合金的一導電材料以填充開口1112 。可於阻障層113上沉積一薄銅種晶層(圖未顯示)以協助形成導電墊1122 之導電材料。然後沉積用於導電墊1122 之含銅導電材料以填充開口1112 。之後，如第6D圖所示，在本發明一些實施例中，移除位於開口1112 之外的含銅導電材料和阻障層113。
然後，如第6E圖所示，在本發明一些實施例中，移除圍繞導電墊1122 之至少一部分介電(絕緣)材料114T 。在本發明一些實施例中，移除位於半導體晶片1002 上的全部介電(絕緣)材料114T 。在本發明其他一些實施例中，只有移除圍繞導電墊1122 之介電(絕緣)材料114T 。可利用可為例如電漿蝕刻法之一乾蝕刻製程或一濕蝕刻製程之蝕刻製程移除介電(絕緣)材料114T 。在本發明一些實施例中，在進行蝕刻製程之前，圖案化半導體晶片1002 以暴露欲移除介電(絕緣)材料114T 的區域，以保護(或覆蓋)導電墊1122 和不想移除的部分介電(絕緣)材料114T 。如第6E圖所示，在本發明一些實施例中，移除介電(絕 緣)材料114T 或圍繞導電墊1122 之絕緣材料之後，形成開口1312 。
然後，如第6F圖所示，在本發明一些實施例中，依序沉積擴散阻障層160B 和介電(絕緣)材料114T 以填充開口1312 。如第6G圖所示，在本發明一些實施例中，移除位於開口1312 之外的多餘擴散阻障層160B 和和介電(絕緣)材料114T 。
第7A圖為本發明一些實施例之兩個相鄰的導電墊1122 的上視圖。第7A圖係顯示每一個導電墊1122 係被一阻障層113和一擴散阻障層160B 環狀物圍繞。擴散阻障層160B 的厚度為T或T’，分別如第5A和5B圖所示。如第7A圖所示，在本發明一些實施例中，圍繞擴散阻障層160B 的區域，例如區域P，係由絕緣材料114T 和其下方的擴散阻障層160B 形成。在本發明一些實施例中，位於絕緣材料114T 下方的擴散阻障層160B 不會一路延伸至旁邊的結構，例如延伸至相鄰的導電墊結構。第7B圖係顯示在本發明一些實施例中，圍繞導電墊1122A 的擴散阻障層160B 僅會延伸至區域QR ，且不會連接至僅會延伸至區域R之圍繞導電墊1122B 的擴散阻障層160B 。位於介電(絕緣)材料114T 下方的擴散阻障層160B 的寬度為T*。在本發明一些實施例中，寬度T*的範圍可從0.001μm至10μm。
第8A圖為本發明一些實施例之半導體晶片1503 接合至半導體晶片1003 的剖面圖。第8A圖係顯示導電墊1523 的寬度Wtop3 約等於導電墊1123 的寬度Wbot3 。擴散阻障層160T ’係形成於半導體晶片1503 上，且擴散阻障層160B ’係形成於半導體晶片1003 上。擴散阻障層160B ’係包圍和圍繞導電墊1123 。擴散阻 障層160T ’也包圍和圍繞導電墊1523 。擴散阻障層160T ’和擴散阻障層160B’ 可為介電材料且可由類似於擴散阻障層1601 的材料形成。
擴散阻障層160T ’和擴散阻障層160B ’可避免因導電墊1123 和1523 的對準錯誤造成的銅擴散。擴散阻障層160B 的厚度T*應夠大以掩蓋對準變異量。在本發明一些實施例中，厚度T*可大於0.01μm，且其為導電墊1123 和1523 的對準控制極限。擴散阻障層160T ’及/或擴散阻障層160B ’可為一介電材料或一導電材料。擴散阻障層160T ’及/或擴散阻障層160B ’的導電性質不會導致短路，只要擴散阻障層160T ’及/或擴散阻障層160B ’的寬度小於位於相同基板上的兩個相鄰導電墊的距離的一半即可。如上所述，擴散阻障層160T ’及/或擴散阻障層160B ’可由例如氮化矽、氮氧化矽、氮化鉭、氮化鈦或氮化鋁等材料形成。
第8B圖為本發明一些實施例之半導體晶片1503 接合至半導體晶片1003 的剖面圖。第8B圖類似於第8A圖，除了第8B圖沒有擴散阻障層160T’ 圍繞導電墊1523 ’之外。擴散阻障層160B ’係包圍及環繞導電墊1123 。擴散阻障層160B ’可避免因導電墊1123 和1523 ’的對準錯誤造成的銅擴散。擴散阻障層160B ’的厚度T*’應夠大以掩蓋對準變異量。在本發明一些實施例中，厚度T*’可大於0.01μm，且其為導電墊1123 和1523 ’的對準控制極限。
第9A-9F圖為本發明一些實施例之包圍一導電墊1123 和1523 ’的一部分的一擴散阻障層的形成方法。第9A圖係顯 示具介層孔110的一部分半導體晶片1003 ，上述之介層孔110係嵌入於一介電(絕緣)材料114U 中。提供如第9A圖所示的半導體晶片1003 之後，如第9B圖所示於半導體晶片1002 的表面上依序沉積一介電(絕緣)材料(或層)114T 和一平坦化停止層161。可由氮化矽或氮氧化矽形成，且厚度範圍可從0.001μm至50μm。如第9B圖所示，在本發明一些實施例中，沉積這些介電層之後，圖案化且蝕刻半導體晶片1003 以形成開口1113 。開口1113 具有一寬度W3 ，範圍可從0.1μm至50μm。開口1113 係暴露介層孔110的頂部。如第9C圖所示，形成開口1113 之後，沉積一擴散阻障層160B ’以覆蓋基板表面且襯墊開口1112 。在本發明一些實施例中，擴散阻障層160B ’的厚度範圍可從0.001μm至10μm。
如第9D圖所示，在本發明一些實施例中，之後，進行一蝕刻製程以移除位於半導體晶片1003 表面的擴散阻障層160B ’，且使接近角落164的擴散阻障層160B ’成錐狀。錐狀角落164會使開口1112 的空隙填充更加容易。之後，如第9E圖所示，在本發明一些實施例中，依序沉積阻障層113和用於導電墊1123 的一導電材料115，以填充剩餘的開口1113 。然後進行一平坦化製程以移除位於開口1113 外部的多餘導電材料和阻障層113。平坦化停止層161係避免過度移除其下的介電(絕緣)材料114T 。在本發明一些實施例中，移除位於開口1113 外部的多餘導電材料和阻障層113之後，移除暴露出來的平坦化停止層161。第9F圖顯示本發明一些實施例之導電墊1123 和形成於導電墊1123 旁邊且圍繞導電墊1123 的擴散阻障層160B ’。
第10A圖顯示本發明一些實施例之一晶圓1000的 一區域1100。區域1100具有藉由一阻障層113和一擴散阻障層160圍繞及包圍的兩個導電墊112。擴散阻障層160係類似於上述的擴散阻障層1601 且具有阻擋銅擴散的功能。在本發明一些實施例中，擴散阻障層160可由聚合物形成，例如可阻擋銅擴散的苯並環丁烯(benzocyclobutene，BCB)聚合物介電質。
第10B圖顯示本發明一些實施例之沿第10A圖的切線X-X’的剖面圖。第10B圖顯示導電墊112係嵌入絕緣材料114係被接近晶圓1000的表面的擴散阻障層160圍繞。在本發明一些實施例中，擴散阻障層160原來為液態，且以一旋轉塗佈製程形成。擴散阻障層160的液態材料係經歷聚合而變成固態的擴散阻障層160。在本發明一些實施例中，液態擴散阻障層160的溶劑係於形成固態擴散阻障層160的製程中揮發。
第10C圖顯示本發明一些實施例之一晶圓1000的一區域1500。第10C圖顯示擴散阻障層160形成帶狀區域D，帶狀區域D圍繞導電墊112，而導電墊112包圍區域A。在本發明一些實施例中，區域A具有光感應器(或畫素)的一陣列。在本發明一些實施例中，區域A被由二氧化矽(SiO2 )形成的區域B圍繞。在本發明一些實施例中，圍繞帶狀區域D的區域C由氧化物形成。在本發明一些實施例中，圍繞區域A的帶狀區域D係遵循區域A的形狀。在第10C圖顯示之本發明實施例中，帶狀區域D具有長方形帶狀。在本發明一些實施例中，晶圓1000係接合至具相同導電墊、擴散阻障層160和光感應器配置的另一晶圓。
如第7A、7B和10A圖所示的導電墊112可為正方形 及/或長方形。在本發明其他實施例中，導電墊112可為例如圓形或橢圓形等其他形狀。
本發明實施例之擴散阻障層係提供形成一銅擴散阻障層的機制，以避免因晶圓混成接合造成元件衰退。擴散阻障層係包圍用於混成接合製程的含銅導電墊。擴散阻障層可位於兩個接合晶片的其中之一上或位於兩個接合晶片上。
本發明揭露之一實施例係提供一種半導體基板，上述半導體基板包括一導電墊，形成於上述半導體基板的一表面中且接近上述半導體基板的上述表面，其中上述導電墊的一表面係暴露出來。上述導電墊的上述表面係用於與另一基板的另一導電墊混成接合。上述半導體基板也包括一第一阻障層，襯墊於上述導電墊；一第二阻障層，圍繞於上述導電墊，其中上述第二阻障層的一表面對齊於上述導電墊的上述表面。
本發明揭露之另一實施例係提供一種混成接合結構，上述混成接合結構包括一第一基板的一第一導電墊，接合至一第二基板的一第二導電墊，其中上述第一導電墊藉由一第一擴散阻障層與殘留的上述第一基板隔開。上述第二導電墊藉由一第二擴散阻障層與殘留的上述第二基板隔開。上述混成接合結構還包括上述第一基板的一第一介電區，接合至上述第二基板的一第二介電區。上述混成接合結構還包括上述第一基板的一第三擴散阻障層，接合至上述第二基板的一第三介電區。上述第三擴散阻障層係圍繞上述第一導電墊。
本發明揭露之另一實施例係提供一種混成接合基板的形成方法。上述方法包括提供具一導電結構的上述基板。 上述方法包括於上述基板的一表面上方沉積一蝕刻停止層，其中上述蝕刻停止層與導電結構接觸。上述方法還包括於上述蝕刻停止層上方沉積一介電材料；於上述介電材料上方沉積一擴散阻障層。上述方法更包括形成內嵌於依序沉積的上述蝕刻停止層、上述介電材料和上述擴散阻障層中的一導電墊，其中上述擴散阻障層的一表面對齊於上述導電墊的一表面。
本發明揭露之又另一實施例係提供一種混成接合基板的形成方法。上述方法包括提供具一導電結構的上述基板；於一蝕刻停止層上方沉積一介電材料。上述方法還包括圖案化上述基板以於上述介電材料中形成一開口，其中上述開口暴露上述導電結構。上述方法還包括沉積一第一擴散阻障層以襯墊上述開口；蝕刻位於上述開口外的一部分上述第一擴散阻障層，且移除上述開口的一底面。上述蝕刻暴露上述導電結構，其中上述第一擴散阻障層的一殘留部分覆蓋上述開口的側壁。另外，上述方法包括上述蝕刻之後沉積一第二擴散阻障層，其中上述第二擴散阻障層覆蓋上述第一擴散阻障層的上述殘留部分的暴露出來的表面。另外，上述方法包括沉積一導電材料以填充上述開口中的間隙；利用一平坦化製程以移除位於上述開口外的上述導電材料和上述第二擴散阻障層，以形成一導電墊，且上述第一擴散阻障層係圍繞上述第二擴散阻障層和上述導電墊。
雖然本發明已以實施例揭露如上，然其並非用以限定本發明，任何熟習此技藝者，在不脫離本發明之精神和範圍內，當可作些許之更動與潤飾，因此本發明之保護範圍當視 後附之申請專利範圍所界定為準。
110‧‧‧介層孔
1121 ‧‧‧導電墊
113‧‧‧阻障層
114U 、114T ‧‧‧介電材料
121‧‧‧蝕刻停止層
1601 ‧‧‧擴散阻障層

Claims (10)

  1. 一種半導體基板，包括：一導電墊，形成於該半導體基板的一表面中且接近該半導體基板的該表面，其中該導電墊的一表面係暴露出來，且其中該導電墊的該表面係用於與另一基板的另一導電墊混成接合；一第一阻障層，襯墊於該導電墊；一第二阻障層，圍繞於該導電墊，其中該第二阻障層的一表面對齊於該導電墊的該表面；以及一絕緣材料，位於該半導體基板上方，其中該第二阻障層位於該半導體基板和該絕緣材料之間，且該絕緣材料係用於與該另一基板的另一絕緣材料混成接合。
  2. 如申請專利範圍第1項所述之半導體基板，其中該第二阻障層的該表面延伸橫越該半導體基板的該表面。
  3. 如申請專利範圍第1項所述之半導體基板，其中該第二阻障層形成一環狀物，圍繞該導電墊。
  4. 如申請專利範圍第1項所述之半導體基板，其中該第二阻障層的一部分係低於一介電層，其中該介電層係環繞著圍繞該導電墊的部分該第二阻障層。
  5. 如申請專利範圍第1項所述之半導體基板，其中該第一阻障層為導電，其中該第二阻障層為一介電材料或一導電材料。
  6. 一種混成接合結構，包括：一第一基板的一第一導電墊，接合至一第二基板的一第二導電墊，其中該第一導電墊藉由一第一擴散阻障層與殘留 的該第一基板隔開，且其中該第二導電墊藉由一第二擴散阻障層與殘留的該第二基板隔開；該第一基板的一第一介電區，接合至該第二基板的一第二介電區；該第一基板的一第三擴散阻障層，接合至該第二基板的一第三介電區，其中該第三擴散阻障層係圍繞該第一導電墊；以及該第一基板的一第一絕緣材料，接合至該第二基板的一第二絕緣材料，其中該第一絕緣材料藉由該第三擴散阻障層與該第一基板隔開。
  7. 如申請專利範圍第6項所述之混成接合結構，其中接合至該第三介電區的該第三擴散阻障層的一表面係對齊於接合至該第二導電墊的該第一導電墊的一表面。
  8. 一種混成接合基板的形成方法，包括下列步驟：提供具一導電結構的一基板；於該基板的一表面上方沉積一蝕刻停止層，其中該蝕刻停止層與導電結構接觸；於該蝕刻停止層上方沉積一介電材料；形成內嵌於依序沉積的該蝕刻停止層和該介電材料中的一導電墊和襯墊於該導電墊的一第一擴散阻障層；移除該介電材料；形成一第二擴散阻障層，圍繞該導電墊，其中該第二擴散阻障層的一表面對齊於該導電墊的一表面；以及於該基板上形成一絕緣材料，其中該第二擴散阻障層位於 該基板和該絕緣材料之間，且該絕緣材料係用於與另一基板的另一絕緣材料混成接合。
  9. 一種混成接合基板的形成方法，包括下列步驟：提供具一導電結構的該基板；於一蝕刻停止層上方沉積一介電材料；圖案化該基板以於該介電材料中形成一開口，其中該開口暴露該導電結構；沉積一第一擴散阻障層以襯墊該開口；沉積一導電材料以填充該開口中的間隙；移除位於該開口外的該導電材料和該第一擴散阻障層，以形成一導電墊；移除該介電材料；形成一第二擴散阻障層，圍繞該導電墊；以及於該基板上形成一絕緣材料，其中該第二擴散阻障層位於該基板和該絕緣材料之間，且該絕緣材料係用於與另一基板的另一絕緣材料混成接合。
  10. 如申請專利範圍第9項所述之混成接合基板的形成方法，更包括：在圖案化該基板前，於該介電材料上方沉積一平坦化停止層。
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