KR20220060620A - 반도체 장치 및 이를 포함하는 전자 시스템 - Google Patents
반도체 장치 및 이를 포함하는 전자 시스템 Download PDFInfo
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- KR20220060620A KR20220060620A KR1020200146263A KR20200146263A KR20220060620A KR 20220060620 A KR20220060620 A KR 20220060620A KR 1020200146263 A KR1020200146263 A KR 1020200146263A KR 20200146263 A KR20200146263 A KR 20200146263A KR 20220060620 A KR20220060620 A KR 20220060620A
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- H01L27/11575—
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- G11C16/00—Erasable programmable read-only memories
- G11C16/02—Erasable programmable read-only memories electrically programmable
- G11C16/06—Auxiliary circuits, e.g. for writing into memory
- G11C16/08—Address circuits; Decoders; Word-line control circuits
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Abstract
Description
도 5는 본 발명의 실시예들에 따른 반도체 장치들이 집적된 기판을 나타내는 도면이다.
도 6은 본 발명의 실시예들에 따른 반도체 장치의 개략적인 사시도이다.
도 7은 본 발명의 실시예들에 따른 반도체장치의 셀 어레이를 나타내는 회로도이다.
도 8 및 도 9는 본 발명의 실시예들에 따른 반도체 장치의 개략적인 평면도들로써, 도 4의 A 부분을 확대한 도면들이다.
도 10은 본 발명의 예시적인 실시예에 따른 반도체 장치를 포함하는 전자 시스템을 개략적으로 나타낸 도면이다.
도 11은 본 발명의 예시적인 실시예에 따른 반도체 장치를 포함하는 전자 시스템을 개략적으로 나타낸 사시도이다.
도 12는 본 발명의 예시적인 실시예에 따른 반도체 패키지들을 개략적으로 나타낸 단면도이다.
도 13은 본 발명의 실시예들에 따른 반도체 장치를 설명하기 위한 평면도이다.
도 14은 본 발명의 실시예들에 따른 반도체 장치를 설명하기 위한 단면도로써, 도 13의 A-A'선을 따라 자른 단면에 해당한다.
도 15는 본 발명의 실시예들에 따른 반도체 장치를 설명하기 위한 단면도이다.
도 16은 본 발명의 실시예들에 따른 반도체 장치를 설명하기 위한 단면도이다.
도 17 내지 도 27은 본 발명의 실시예들에 따른 반도체 장치의 제조 방법을 설명하기 위한 단면도들이다.
Claims (10)
- 상호 적층되는 셀 구조체, 및 주변 회로 구조체를 포함하되,
상기 셀 구조체는:
제 1 기판 상에 적층되는 복수의 게이트 전극층;
상기 게이트 전극층들을 수직으로 관통하는 복수의 채널 영역;
상기 제 1 기판 상에서 상기 게이트 전극층들 및 상기 채널 영역들을 덮는 제 1 층간 절연층; 및
상기 제 1 층간 절연막 상으로 노출되고, 상기 게이트 전극층들 및 상기 채널 영역들과 연결되는 제 1 금속 패드들을 포함하고,
상기 주변 회로 구조체는:
제 2 기판 상에 형성되는 적어도 하나의 트랜지스터;
상기 제 2 기판 상에서 상기 트랜지스터를 덮는 제 2 층간 절연막; 및
상기 제 2 층간 절연막 상으로 노출되고, 상기 트랜지스터와 연결되는 제 2 금속 패드들을 포함하고,
상기 제 1 금속 패드들은 서로 인접한 제 1 서브 패드 및 제 2 서브 패드를 포함하고, 상기 제 2 금속 패드들은 서로 인접한 제 3 서브 패드 및 제 4 서브 패드를 포함하고,
상기 제 1 서브 패드는 상기 제 3 서브 패드와 접하되, 상기 제 1 서브 패드의 폭은 상기 제 3 서브 패드의 폭보다 크고,
상기 제 2 서브 패드는 상기 제 4 서브 패드와 접하되, 상기 제 4 서브 패드의 폭은 상기 제 2 서브 패드의 폭보다 큰 반도체 장치. - 제 1 항에 있어서,
상기 제 1 층간 절연막과 상기 제 2 층간 절연막의 계면 상에서,
상기 제 1 서브 패드의 면적은 상기 제 3 서브 패드의 면적보다 크되, 평면적 관점에서 상기 제 3 서브 패드는 상기 제 1 서브 패드의 내측에 위치하고,
상기 제 4 서브 패드의 면적은 상기 제 2 서브 패드의 면적보다 크되, 평면적 관점에서 상기 제 2 서브 패드는 상기 제 4 서브 패드의 내측에 위치하는 반도체 장치. - 제 1 항에 있어서,
상기 제 1 내지 제 4 서브 패드들 각각은 복수로 제공되되,
상기 제 1 서브 패드들 및 상기 제 2 서브 패드들은 상기 제 1 기판의 상면에 평행한 일 방향으로 교번하여 배열되는 반도체 장치. - 제 1 항에 있어서,
상기 제 1 내지 제 4 서브 패드들 각각은 복수로 제공되되,
상기 제 1 서브 패드들은 상기 제 1 기판의 제 1 영역 상에 제공되고,
상기 제 2 서브 패드들은 상기 제 1 기판의 제 2 영역 상에 제공되는 반도체 장치. - 제 1 항에 있어서,
상기 제 1 금속 패드들은 상기 제 1 서브 패드 및 상기 제 2 서브 패드 사이의 제 5 서브 패드를 더 포함하고,
상기 제 2 금속 패드들은 상기 제 3 서브 패드 및 상기 제 4 서브 패드 사이의 제 6 서브 패드를 더 포함하고,
상기 제 5 서브 패드는 상기 제 6 서브 패드와 접하되, 상기 제 5 서브 패드의 폭은 상기 제 6 서브 패드의 폭과 동일한 반도체 장치. - 제 5 항에 있어서,
상기 제 5 서브 패드와 상기 제 6 서브 패드는 수직으로 정렬되는 반도체 장치. - 제 1 기판 상에 제공되는 제 1 패드 및 제 2 패드를 포함하는 메모리 셀 영역;
제 2 기판 상에 제공되는 제 3 패드 및 제 4 패드를 포함하고, 상기 패드들에 의해 상기 메모리 셀 영역에 수직적으로 연결되는 주변 회로 영역;
상기 메모리 셀 영역 내에 제공되고, 복수의 메모리 셀들을 포함하는 복수의 셀 스트링들, 상기 메모리 셀들에 각각 연결되는 복수의 워드 라인들, 상기 셀 스트링들의 일측에 연결되는 복수의 비트 라인들, 및 상기 셀 스트링들과 연결되는 접지 선택 라인을 포함하는 메모리 셀 어레이;
상기 주변 회로 영역 내에 제공되고, 상기 셀 스트링들 중 일부 셀 스트링들을 제어하고, 상기 메모리 셀들에 대한 복수의 데이터 프로그램 단계를 제어하기 위한 프리 차지 제어 회로를 포함하는 제어 회로; 및
상기 제어 회로의 제어에 응답하여 상기 복수의 워드 라인의 적어도 일부를 활성화시키기 위하여 상기 주변 회로 영역 내에 제공되는 로우 디코더를 포함하되,
상기 제 1 패드는 상기 제 3 패드와 접하고, 상기 제 2 패드는 상기 제 4 패드와 접하고,
평면적 관점에서 상기 제 1 패드의 평면 형상 및 상기 제 4 패드의 평면 형상은 각각 상기 제 3 패드의 평면 형상 및 상기 제 2 패드의 평면 형상보다 작은 반도체 장치. - 제 7 항에 있어서,
상기 제 1 패드의 폭은 상기 제 3 패드의 폭보다 크고,
상기 제 4 패드의 폭은 상기 제 2 패드의 폭보다 큰 반도체 장치. - 제 7 항에 있어서,
상기 메모리 셀 영역은 상기 제 1 기판 상에서 상기 셀 스트링들, 상기 워드 라인들, 상기 비트 라인들, 및 상기 접지 선택 라인을 덮는 제 1 층간 절연층을 더 포함하고,
상기 주변 회로 영역은 상기 제 2 기판 상에서 상기 제어 회로를 덮는 제 2 층간 절연층을 더 포함하고, 및
상기 제 1 층간 절연층과 상기 제 2 층간 절연층은 서로 접하고,
상기 제 1 층간 절연층과 상기 제 2 층간 절연층의 계면 상에서, 상기 제 1 패드는 상기 제 3 패드와 접하고, 상기 제 2 패드는 상기 제 4 패드와 접하는 반도체 장치. - 메인 기판;
상기 메인 기판 상에 제공되고, 하부 구조체 및 상기 하부 구조체 상에 적층되는 상부 구조체를 포함하는 반도체 장치; 및
상기 메인 기판 상에서 상기 반도체 장치와 전기적으로 연결되는 컨트롤러를 포함하되,
상기 하부 구조체는:
제 1 반도체 기판 상에 형성되는 제 1 회로 패턴;
상기 제 1 반도체 기판 상에서 상기 제 1 회로 패턴을 덮는 제 1 층간 절연막; 및
상기 제 1 층간 절연막 상으로 노출되고, 상기 제 1 회로 패턴과 연결되는 서로 인접한 제 1 금속 패드 및 제 2 금속 패드를 포함하고,
상기 상부 구조체는:
제 2 반도체 기판 상에 형성되는 제 2 회로 패턴;
상기 제 2 반도체 기판 상에서 상기 제 2 회로 패턴을 덮는 제 2 층간 절연막; 및
상기 제 2 층간 절연막 상으로 노출되고, 상기 제 1 금속 패드와 접하는 제 3 금속 패드 및 상기 제 2 금속 패드와 접하는 제 4 금속 패드를 포함하고,
상기 제 1 금속 패드의 폭 및 상기 제 4 금속 패드의 폭은 상기 제 3 금속 패드의 폭 및 상기 제 2 금속 패드의 폭보다 큰 전자 시스템.
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