CN113611685A - 半导体封装结构及其制备方法 - Google Patents

半导体封装结构及其制备方法 Download PDF

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CN113611685A
CN113611685A CN202110453317.0A CN202110453317A CN113611685A CN 113611685 A CN113611685 A CN 113611685A CN 202110453317 A CN202110453317 A CN 202110453317A CN 113611685 A CN113611685 A CN 113611685A
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semiconductor
stack
isolation
semiconductor structure
conductive
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CN113611685B (zh
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黄则尧
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Nanya Technology Corp
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Nanya Technology Corp
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Abstract

本公开提供一种半导体封装结构及该半导体封装结构的制备方法。该半导体封装结构具有一第一半导体结构以及一第二半导体结构，该第二半导体结构与该第一半导体结构接合在一起。该第一半导体结构具有一第一接合表面。该第二半导体结构具有一第二接合表面，该第二接合表面部分接触该第一接合表面。该第一接合表面的一部分与该第二接合表面的一部分分开设置，密封该第一接合表面的该部分与该第二表面的该部分之间的间隔，并形成一气隙在该半导体封装结构中。

Description

半导体封装结构及其制备方法
技术领域
本申请案主张2020年5月4日申请的美国正式申请案第16/865,909号的优先权及益处，该美国正式申请案的内容以全文引用的方式并入本文中。
本公开涉及一种半导体封装结构及其制备方法。特别是涉及一种具有气隙半导体封装结构及其制备方法，其是用以降低在导电特征之间的电容耦合。
背景技术
近年来，由于持续改善各式不同电子元件的整合密度，所以半导体产业经历了快速成长。这些尺寸的电子元件需要更小的封装结构，而相较于先前的封装结构，这些更小的封装结构是占据更小的面积。然而，可以在二维(2D)达到该半导体封装结构的规格是具有物理上的限制。当二维规格仍然是新设计的一种选择时，采用利用z方向的三维(3D)封装方案是已成为业界研究的重点。尽管如此，三维封装技术仍面临着挑战。
上文的“先前技术”说明仅是提供背景技术，并未承认上文的“先前技术”说明揭示本公开的标的，不构成本公开的先前技术，且上文的“先前技术”的任何说明均不应作为本案的任一部分。
发明内容
本公开的一实施例提供一种半导体封装结构。该半导体封装结构包括一第一半导体结构，具有一第一表面以及一第一凹部，该第一凹部是从该第一表面凹陷，且该第一半导体结构包括多个第一导电结构，所述第一导电结构是从该第一凹部的一下表面凸伸；以及一第二半导体结构，具有一第二表面以及多个第二凹部，所述第二凹部是从该第二表面凹陷，且该第二半导体结构包括多个第二导电结构，所述第二导电结构是从该第二表面凸伸，其中该第二半导体结构接合到该第一半导体结构上，所述第一导电结构插入到所述第二凹部，所述第二导电结构接触该第一凹部的该下表面，该第二表面的一部分接触该第一表面以密封该第一凹部，以便形成一气隙在该半导体封装结构中。
在本公开的一些实施例中，该气隙横向地围绕所述第一导电结构设置。
在本公开的一些实施例中，该第一半导体结构还包括多个第一隔离层的一堆叠以及一隔离图案，该隔离图案位在所述第一隔离层的该堆叠上，该第一表面为该隔离图案的一上表面，该隔离图案呈一环形形状，该隔离图案的一内侧壁为该第一凹部的一侧壁，以及该第一凹部的该下表面为所述第一隔离层的该堆叠的一上表面。
在本公开的一些实施例中，该气隙具有一高度，大致等于该隔离图案的一厚度。
在本公开的一些实施例中，该第二半导体结构还包括多个第二隔离层的一堆叠，该第二表面为所述第二隔离层的该堆叠的一表面，以及该第二凹部延伸经过所述第二隔离层的该堆叠。
在本公开的一些实施例中，所述第一导电结构从所述第一隔离层的该堆叠的该上表面凸伸的一第一厚度，大致等于该隔离图案与所述第二隔离层的该堆叠的一总厚度。
在本公开的一些实施例中，所述第二导电结构从所述第二隔离层的该堆叠凸伸的一第二厚度，大致等于该隔离图案的一厚度。
在本公开的一些实施例中，所述第一导电结构较高于所述第二导电结构，以及该第二导电结构呈一环形形状，以围绕所述第一导电结构设置。
本公开的另一实施例提供一种半导体封装结构。该半导体封装结构包括一第一半导体结构，具有一第一接合表面以及多个第一凸部，所述第一凸部从该第一接合表面凸伸；以及一第二半导体结构，具有一第二接合表面以及多个第二凸部，所述第二凸部从该第二接合表面凸伸，该第二半导体结构接合到该第一半导体结构，其中该第一接合表面部分接触该第二接合表面，该第一接合表面的一部分与该第二接合表面的一部分分开设置，密封该第一接合表面的该部分与该第二接合表面的该部分之间的一间隔，并形成一气隙在该半导体封装结构中；其中该气隙横向地围绕所述第一凸部设置，所述第一凸部较高于所述第二凸部，以及所述第二凸部呈一环形形状，以围绕所述第一凸部设置。
在本公开的一些实施例中，该第一接合表面具有一凹部，且所述第一凸部位在该凹部的范围内。
在本公开的一些实施例中，所述第二凸部接触该第一接合表面的该凹部。
在本公开的一些实施例中，所述第一凸部为多个导电栓塞，电性连接该第一半导体结构的一第一内连接以及该第二半导体结构的一第二内连接。
在本公开的一些实施例中，所述第二凸部为多个导电栓塞，接触该第二半导体的该第二内连接，并与该第一半导体的该第一内连接分开设置。
本公开的另一实施例提供一种半导体封装结构的制备方法。该方法包括：提供一第一基底，该第一基底具有一集成电路；形成多个隔离层的一第一堆叠在该集成电路上，所述隔离层的该第一堆叠具有多个第一凸部；移除所述隔离层的该第一堆叠的一最上面的隔离层；形成多个穿孔在该第一堆叠中，以形成一第一半导体结构；提供一第二基底，该第二基底具有一集成电路；形成多个隔离层的一第二堆叠在该集成电路上，所述隔离层的该第二堆叠具有多个第二凸部；形成一凹部在该第一堆叠中，以形成一第二半导体结构；以及接合该第一半导体结构与该第二半导体结构，且从该凹部形成一气隙。
在本公开的一些实施例中，所述第二凸部插入到所述穿孔中，以及所述第一凸部插入到该凹部中。
在本公开的一些实施例中，形成多个隔离层的一第二堆叠在该集成电路上，所述隔离层的该第二堆叠具有多个第二凸部的步骤包括：形成多个第一穿孔在所述隔离层的该第一堆叠中；充填所述第一穿孔，其是以导电材料进行充填；以及移除所述隔离层的该第一堆叠的一上部。
在本公开的一些实施例中，形成多个隔离层的一第一堆叠在该集成电路上，所述隔离层的该第一堆叠具有多个第一凸部的步骤包括：形成多个第二穿孔在所述隔离层的该第二堆叠中；充填所述第二穿孔，其是以导电材料进行充填；以及薄化所述隔离层的该第二堆叠的一上部；其中所述气隙的其中之一是位在其中一第一导电结构与其中一第二导电结构之间。
在本公开的一些实施例中，该气隙横向地围绕所述第一凸部设置，以及所述第一凸部较高于所述第二凸部。
在本公开的一些实施例中，该半导体封装结构的制备方法还包括：执行紫外光固化制程，以移除多个悬浮键(dangling bonds)，其是在该第一半导体结构与该第二半导体结构接合之前执行。
在本公开的一些实施例中，该半导体封装结构的制备方法还包括：执行一快速热氮化(rapid thermal nitridation)，以增浓一钝化层。
综上所述，依据本公开的一些实施例的半导体封装结构，是具有相互接合在一起的二半导体结构，亦具有多个气隙，密封在导电元件之间，而所述导电元件是经配置以建立在所述半导体结构之间的电性连接。因为空气的一低的介电常数，所以可通过设置在所述导电元件之间的气隙而降低在其间的一电容耦合。因此，可降低所述导电元件的电阻-电容延迟(RC delay)。因此，可改善所述半导体结构之间的信号传输。
上文已相当广泛地概述本公开的技术特征及优点，而使下文的本公开详细描述得以获得较佳了解。构成本公开的权利要求标的的其它技术特征及优点将描述于下文。本公开所属技术领域中具有通常知识者应了解，可相当容易地利用下文揭示的概念与特定实施例可作为修改或设计其它结构或制程而实现与本公开相同的目的。本公开所属技术领域中具有通常知识者亦应了解，这类等效建构无法脱离后附的权利要求所界定的本公开的精神和范围。
附图说明
参阅实施方式与权利要求合并考量图式时，可得以更全面了解本申请案的揭示内容，图式中相同的元件符号是指相同的元件。
图1为依据本公开一些实施例中一种半导体结构的制备方法的流程示意图。
图2A到图2I为依据本公开一些实施例在如图1所示的制造程序期间的各不同阶段的剖视示意图。
图3为依据本公开一些实施例中一种半导体结构的制备方法的流程示意图。
图4A到图4K为依据本公开一些实施例在如图3所示的制造程序期间的各不同阶段的剖视示意图。
其中，附图标记说明如下：
10：半导体结构
11：接合表面
100：基底
102：集成电路
104：内连接
106：隔离层
108：接合结构
108a：接合垫
108c：布线结构
110：支撑结构
112：钝化层
112a：钝化层
20：半导体结构
21：接合表面
200：基底
202：集成电路
204：内连接
206a：隔离层
206b：隔离层
206c：隔离层
210：支撑结构
30：半导体封装结构
300：基底
302：集成电路
304：内连接
306a：隔离层
306b：隔离层
306c：隔离层
308：接合结构
40：半导体结构
41：接合表面
50：半导体结构
51：接合表面
60：半导体封装结构
AG：气隙
AG’：气隙
M30：方法
M60：方法
PR：遮罩图案
RS：凹部
RS’：凹部
S11：步骤
S13：步骤
S15：步骤
S17：步骤
S19：步骤
S21：步骤
S23：步骤
S25：步骤
S31：步骤
S33：步骤
S35：步骤
S37：步骤
S39：步骤
S41：步骤
S43：步骤
S45：步骤
S47：步骤
S49：步骤
S51：步骤
T206a：厚度
T206b：厚度
T206c：厚度
T306a：厚度
T306b：厚度
T306c：厚度
T306c’：厚度
TH1：穿孔
TH2：穿孔
W：开口
具体实施方式
以下描述了组件和配置的具体范例，以简化本公开的实施例。当然，这些实施例仅用以例示，并非意图限制本公开的范围。举例而言，在叙述中第一部件形成于第二部件之上，可能包含形成第一和第二部件直接接触的实施例，也可能包含额外的部件形成于第一和第二部件之间，使得第一和第二部件不会直接接触的实施例。另外，本公开的实施例可能在许多范例中重复参照标号及/或字母。这些重复的目的是为了简化和清楚，除非内文中特别说明，其本身并非代表各种实施例及/或所讨论的配置之间有特定的关系。
此外，为易于说明，本文中可能使用例如“之下(beneath)”、“下面(below)”、“下部的(lower)”、“上方(above)”、“上部的(upper)”等空间相对关系用语来阐述图中所示的一个元件或特征与另一(其他)元件或特征的关系。所述空间相对关系用语旨在除图中所绘示的取向外亦囊括元件在使用或操作中的不同取向。所述装置可具有其他取向(旋转90度或处于其他取向)且本文中所用的空间相对关系描述语可同样相应地进行解释。
图1为依据本公开一些实施例中一种半导体结构的制备方法M30的流程示意图。图2A到图2I为依据本公开一些实施例在如图1所示的制造程序期间的各不同阶段的剖视示意图。
请参考图1及图2A，执行步骤S11，以及提供一基底100，基底100具有一集成电路102。在一些实施例中，基底100为一晶圆形式。在这些实施例中，基底100可为一半导体晶圆或一绝缘体上覆半导体(SOI)晶圆。举例来说，在半导体晶圆或SOI晶圆中的一半导体材料可包含一元素半导体(意即硅(Si))、一合金半导体(意即硅锗(SiGe))、一化合物半导体(意即III-V族半导体、II-VI族半导体)或是其组合。此外，半导体材料可掺杂有一第一导电类型(意即N型)或一第二导电类型(意即P型)，而第二导电类型是与第一导电类型互补。在那些实施例中，在基底100成一晶圆形式的情况下，基底100具有多个晶粒区，所述晶粒区是通过一切割线区(scribe line region)(图未示)而相互分隔设置，以及集成电路102布设在所述晶粒区内。集成电路102可具有多个主动元件及/或多个被动元件(均未图示)，其是形成在基底100的一表面处，且集成电路102可具有多个内连接在所述主动元件及/或所述被动元件上。所述内连接经配置以内连接所述主动元件及/或所述被动元件，并布线(route)所述主动元件及/或所述被动元件到集成电路102的一上侧。举例来说，所述主动元件可包括金属氧化物半导体场效晶体管(MOSFETs)，而所述被动元件可包括电容器。再者，所述内连接可形成在多个介电层的一堆叠中，并可分别包括导电线迹(traces)以及多个导电通孔(vias)，所述导电线迹是延伸在其中一介电层的一表面上，而所述通孔垂直延伸并连接到至少一导电线迹。应当理解，在图2A中仅描述所述内连接的最上面的部分，且标示所述内连接的编号为104。此外，集成电路102的一上侧可表示成均匀形成的半导体结构(意即如图2F所示的半导体结构)的一主动侧，同时基底100的一下侧可表示成半导体结构的一背侧。
请参考图1及图2B，执行步骤S13，且多个隔离层106的一堆叠(意即二隔离层106)以及多个接合结构108与多个支撑结构110形成在集成电路102上。所述接合结构108与所述支撑结构110穿经所述隔离层106的堆叠。应当理解，仅描述其中一接合结构108与其中一支撑结构110。所述接合结构108电性连接到所述内连接(意即内连接104)的最上面的部分，并可当作是集成电路102的输入/输出(I/Os)。在一些实施例中，所述接合结构108分别具有一接合垫108a以及一布线结构108c，而布线结构108c是连接接合垫108a到所述内连接(意即内连接104)的最上面的部分。接合垫108a可形成在最上面的隔离层106中，并具有一上表面，是大致与最上面的隔离层106的一上表面为共面。布线结构108c是例如一导电通孔或一导电柱(pillar)，是从接合垫108a的一下端延伸到所述内连接(意即内连接104)的最上面的部分。另一方面，所述支撑结构110可形成如导电通孔或导电柱，并延伸经过所述隔离层106的堆叠。在一些实施例中，所述支撑结构110可电性连接到所述内连接(意即内连接104)的最上面的部分。在这些实施例中，所述连接的内连接104与所述支撑结构110可电性浮接(electrically floated)，并经配置以加强均匀形成的半导体结构(意即如图2H所示的半导体封装结构30)的机构强度。或者是，所述连接的内连接104与所述支撑结构110可电性接地(electrically grounded)，并可当作是集成电路102的电磁屏蔽。在其他实施例中，所述支撑结构110可不电性连接到任何所述内连接104，并可电性浮接或电性接地。
再者，在一些实施例中，所述支撑结构110可相互连接，以形成一壁体，而此壁体横向围绕所述接合结构108。在这些实施例中，壁体可当作是一密封环。在其他实施例中，所述支撑结构110横向相互分开设置，并与所述接合结构108横向被一密封环(图未示)所围绕。
所述隔离层106的一材料可包含一非有机隔离材料(意即氧化硅、氮化硅、氮氧化硅、类似物或其组合)，同时所述接合结构108与所述支撑结构110可由一导电材料所制，例如一金属或一金属合金(意即铜、铜合金、类似物或其组合)。在一些实施例中，形成每一隔离层106的方法可包括一沉积制程(意即一化学气相沉积(CVD)制程)，同时形成所述接合结构108与所述支撑结构110在所述隔离层103的堆叠的方法，可包括至少一镶嵌(damascene)制程。然而，所属技术领域中具有通常知识者可选择其他适合的材料及/或其他适当的形成所述隔离层106、所述接合结构108与所述支撑结构110的方法，本公开并不以此为限。
在一些实施例中，在所述接合结构108与所述支撑结构110中的导电材料是通过一阻障层(图未示)而与所述隔离层106的堆叠分开设置。所述阻障层的一材料(之后以一阻障材料表示)可包含Ti、TiN、Ta、TaN、类似物或其组合。此外，形成阻障层的方法可包括一沉积制程，例如物理气相沉积(PVD)制程或原子层沉积(ALD)制程。
请参考图1及图2C，执行步骤S15，且一遮罩图案PR形成在所述隔离层106的堆叠上。遮罩图案PR是例如一光阻图案，具有多个开口W，所述开口W是界定多个凹部的位置，并在接下来的步骤(意即如图2D所示的所述凹部RS)期间，形成在所述隔离层106的堆叠中。每一开口W是横向与所述接合结构108以及所述支撑结构110分开设置。一些开口W是分别位在其中一接合结构108与其中一支撑结构110之间、在相邻接合结构108之间，或者是在相邻支撑结构110之间。此外，一些其他开口W可位在所述接合结构108与所述支撑结构110的一分布范围的外侧。在那些实施例中，在遮罩图案PR为一光阻图案的情况下，形成遮罩图案PR的方法可包括一涂布(coating)制程以及一微影(lithography)制程。
请参考图1及图2D，执行步骤S17，以及为了形成所述凹部RS在所述隔离层106的堆叠的一上区域中，通过使用遮罩图案PR当作一阴影遮罩(shadow mask)，以移除所述隔离层106的堆叠的一些部分。在一些实施例中，通过一蚀刻制程移除所述隔离层106与遮罩图案PR的所述开口W重叠的一些部分，以形成所述凹部RS，而蚀刻制程是例如一非等向性蚀刻制程。如同遮罩图案PR的所述开口W，每一凹部RS横向与所述接合结构108以及所述支撑结构110分开设置。一些凹部RS分别位在其中一接合结构108与其中一支撑结构110之间。此外，一些其他凹部RS可位在所述接合结构108与所述支撑结构110的分布范围的外侧。在一些实施例中，移除最外面的隔离层106与所述开口W重叠的一些部分，同时涂布在隔离层106下的最外面的隔离层106可大致维持完整。在这些实施例中，在参考图2B的步骤S13期间，一蚀刻终止层(图未示)可设置在二垂直的相邻隔离层106中间，且相对于这些隔离层106可具有足够的蚀刻选择性。在此方法中，在形成所述凹部RS之后，可暴露蚀刻终止层与所述开口W重叠的一些部分，并可界定所述凹部RS的下表面。或者是，可省略蚀刻终止层，且在蚀刻期间，可或不可部分移除涂布在最外面的隔离层106下的隔离层106。
请参考图1及图2E，执行步骤S19，并可整体形成一钝化层112。因此，钝化层112是覆盖隔离层106的堆叠的上表面、所述接合结构108的上表面以及所述支撑结构110的上表面。在一些实施例中，钝化层112共形地覆盖下层结构。在这些实施例中，所述凹部RS并未被钝化层112所填满，且钝化层112凹陷在相对应的所述凹部RS，而所述凹部RS是位在所述隔离层106的堆叠的上区域中。举例来说，钝化层112的一材料包含氮化硅。此外，形成钝化层112的方法可包括一沉积制程，例如一原子层沉积(ALD)制程。然而，所属技术领域中具有通常知识者可选择其他可行的隔离材料及/或其他适合的形成钝化层112的形成方法，本公开并不以此为限。
请参考图1及图2F，执行步骤S21，并移除钝化层112位在最外面的隔离层106的一上表面上的一些部分。因此，仅保留钝化层112位在所述凹部RS中的一些部分，且其每一个是表示成一钝化层112a。此外，暴露最外面的隔离层106的上表面以及所述接合结构108与所述支撑结构110的上表面。在一些实施例中，移除钝化层112一些部分的方法可包括一平坦化制程。举例来说，平坦化制程可包括一化学机械研磨(CMP)制程、一蚀刻制程或其组合。
在一些实施例中，钝化层112a是由氮化硅所构成，且在步骤S21之后执行一快速热氮化(RTN)制程。通过执行RTN制程，在钝化层112a中的氮化硅可再进一步增浓。在其他实施例中，钝化层112a可由氧化硅所制，且在遭受RTN制程之后，氧化硅可转变成氮氧化硅或氮化硅。再者，在一些实施例中，可执行一紫外光(UV)固化制程，以移除在多个导电元件中的悬浮键(dangling bonds)(意即所述接合结构108、所述支撑结构110以及集成电路102的所述内连接)。在这些实施例中，紫外光固化制程可接着RTN制程进行，但本公开并不以此为限。
到此，是形成一半导体结构10。半导体结构10是与其他半导体结构(意即如图2G所示的半导体结构20)接合在一起，且最外面的隔离层106的暴露表面、钝化层112a的暴露表面、所述接合结构108的暴露表面以及所述支撑结构110的暴露表面是集体界定半导体结构10的一接表面11。接合表面的至少一些部分(意即在所述凹部RS中的钝化层112a的表面)可不接触接下来接合的半导体结构(意即如图2G所示的半导体结构20)。在一些实施例中，半导体结构10停留在一晶圆形式。在其他实施例中，一单体化制程(singulation process)是执行在如图2F的结构上，以使可为其中一单体化结构的半导体结构10呈一芯片形式。
请参考图1及图2G，执行步骤S23，并提供一半导体结构20。在一些实施例中，通过参考图2A到图2F所描述的方法以提供半导体结构20。为了避免重复描述，在半导体结构10、20中的元件是标示相同。类似于半导体结构10，半导体结构20可停留在一晶圆形式。或者是，可再进一步执行一单体化制程，且可为多个单体化结构之一的半导体结构20是呈一芯片形式。半导体结构20是接合到半导体结构10上，且最外面的隔离层106的暴露表面、钝化层112a的暴露表面、所述接合结构108的暴露表面以及所述支撑结构110的暴露表面是集体界定半导体结构20的一接合表面21。接合表面21的至少一些部分(意即在所述凹部RS中的钝化层112a的表面)可不参与在半导体结构10、20的接合中。
请参考图1及图2H到图2I，执行步骤S25，以及半导体结构10、20是相互接合在一起，以形成一半导体封装结构30。关于半导体结构10、20可分别呈一晶圆形式或一芯片形式，则半导体封装结构30可为一晶圆上晶圆(wafer-on-wafer)结构、一晶圆上芯片(chip-on-wafer)结构或一芯片上芯片(chip-on-chip)结构。一旦半导体结构10、20接合在一起，则半导体结构10、20的接合表面是部分相互接触。在一些实施例中，半导体结构10、20的最外面的隔离层103可相互接合，且半导体结构10的所述隔离层106的堆叠与半导体结构20的所述隔离层106的堆叠是连接，以形成所述隔离层106的一组合堆叠。此外，半导体结构10、20的所述接合结构108是相互接合，且建立在半导体结构10、20之间的集成电路102之间的电性连接。再者，来自半导体结构10、20的所述支撑结构110是相互接合，并可电性浮接或电性接地。另一方面，半导体结构10、20的所述凹部RS是相互对准，以使半导体结构10的钝化层112a的垂直延伸部分与半导体结构20的钝化层112a的垂直延伸部分接合在一起。据此，在所述凹部RS中的腔室可被半导体结构10、20的钝化层112a所密封，并形成气隙AG在已接合的结构(意即半导体封装结构30)中。所述气隙AG是分别被相互接合的二钝化层112所包围。所述接合结构108、所述支撑结构110、所述钝化层112a以及所述气隙AG是位在所述隔离层106的组合堆叠中。当从所述凹部RS继承时，一些气隙AG是位在所述接合结构108与所述支撑结构110的一分布范围内，同时一些其他气隙AG是位在所述接合结构108与所述支撑结构110的分布范围外侧。
在一些实施例中，接合半导体结构10、20的方法包括置放其中一半导体结构10、20在另一个上，举例来说，是通过取放(pick and place，PNP)制程，以及执行一混合接合(hybrid bonding)制程以建立一实体接合在半导体结构10、20之间。在一些实施例中，混合接合制程是执行在真空或惰性大气中，以便避免所述导电元件的氧化及/或湿气入侵。混合接合制程可包括一第一加热步骤以及一第二加热步骤，第一加热步骤是用于接合多个隔离元件，而第二加热步骤是用于接合所述导电元件。举例来说，所述隔离元件可包括已贴合的所述隔离层106与所述钝化层112a，同时所述导电元件可包括已贴合的所述接合结构108与所述支撑结构110。在一些实施例中，第一加热步骤先于第二加热制程。此外，第一加热步骤的一加热温度是较低于第二加热步骤的一加热温度。举例来说，第一加热步骤的加热温度可从150℃到250℃之间的范围，同时第二加热步骤的加热温度可从180℃到350℃之间的范围。然而，所属技术领域中具有通常知识者可依据制程所需而调整第一加热步骤与第二加热步骤的顺序以及加热温度，但本公开并不以此为限。
因为空气的一低的介电常数(意即大约为1)，所以通过设置所述气隙AG而可降低横向相邻接合结构108之间的一电容耦合。类似地，因为所述气隙AG，所以可降低所述接合结构108与所述支撑结构110之间的一电容耦合。因此，可降低所述接合结构108的延迟(RC延迟)。因此，可改善半导体结构10、20的集成电路102之间的信号传输。
图3为依据本公开一些实施例中一种半导体结构的制备方法M60的流程示意图。图4A到图4K为依据本公开一些实施例在如图3所示的制造程序期间的各不同阶段的剖视示意图。参考图3及图4A到图4K所描述的实施例，是类似于参考如图1及图2A到图2I所描述的实施例，并仅讨论其间的差异，相同或类似的部分则不再重复。此外，类似的编号是代表类似或相同的元件(意即基底100以及基底200)。
请参考图3及图4A，执行步骤S31，且提供一基底200，基底具有一集成电路202。应当理解，仅描述在集成电路202中多个内连接的的最上面的部分，且标示为内连接204。
接下来，执行步骤S33，且隔离层206a、206b、206c形成在集成电路202上。隔离层206a涂布在隔离层206b、206c下方，且隔离层206b夹置在隔离层206a、206c之间。隔离层206a具有一厚度T206a，隔离层206b具有一厚度T206b，以及隔离层206c具有一厚度T206c。在一些实施例中，厚度T206b小于厚度T206a与厚度T206c，且厚度T206a可大于、等于或小于厚度T206c。此外，在一些实施例中，隔离层206b的一材料是不同于隔离层206a、206c的一材料。举例来说，隔离层206b可由氮化硅所构成，同时隔离层206a、206c可由氧化硅所构成。形成每一隔离层206a、206b、206c的方法可包括一沉积制程，例如一CVD制程。然而，所属技术领域中具有通常知识者可调整隔离层206a、206b、206c的厚度T206a、T206b、T206c，并选择适合的材料以及形成隔离层206a、206b、206c的形成方法，本公开并不以此为限。
请参考图3及图4B，执行步骤S35，且多个穿孔TH1形成在隔离层206a、206b、206c中。所述穿孔TH1穿经隔离层206a、206b、206c，并暴露所述内连接(意即内连接204)的一些最上面的部分。在一些实施例中，暴露的内连接204是位在接近晶粒区(参考图2A的描述)的一边缘处。形成所述穿孔TH1的方法可包括执行一微影制程以及一或多个蚀刻制程(意即非等向性蚀刻制程)。
请参考图3及图4C，执行步骤S37，且多个支撑结构210形成在所述穿孔TH1中。所述支撑结构210接触先前暴露的所述内连接204。已连接的所述支撑结构210与所述内连接201是电性浮接或电性接地。在一些实施例中，形成所述支撑结构210的方法包括充填一导电材料进入所述穿孔TH1，其是通过一沉积制程(意即一物理气相沉积(PVD)制程)、一镀覆制程(意即一电镀制程或一无电镀覆制程)或其组合所实现。此外，可执行一平坦化制程以移除导电材料在隔离层206c的一上表面上的一些部分。举例来说，导电材料可包含一金属或一金属合金(意即铜、铜合金、类似物或其组合)。此外，举例来说，平坦化制程可包括一CMP制程、一蚀刻制程或其组合。
在一些实施例中，每一支撑结构210还包括一阻障层(图未示)，是覆盖在每一穿孔TH1中的导电材料的一侧壁(意即一侧壁以及一下表面)。阻障层的一材料(之后表示成一阻障材料)可包括Ti、TiN、Ta、TaN、类似物或其组合。此外，形成所述阻障层的方法包括充填阻障材料进入所述穿孔TH1，其是通过一沉积制程所实现，例如一PVD制程或一ALD制程。在一些实施例中，可移除阻障材料位在隔离层206c的表面上的一些部分，其是使用用于移除导电材料位在隔离层206c的上表面上的一些部分的平坦化制程所实现。
请参考图3及图4D，执行步骤S39，并移除隔离层206c。当隔离层206c移除时，是暴露隔离层206b的一上表面以及所述支撑结构210的个侧壁的上部。此外，所述支撑结构210目前从隔离层206b的上表面凸伸一高度，是大致等于移除的隔离层206c的厚度(意即如图4A所示的厚度T206c)。
请参考图3及图4E，执行步骤S41，且多个穿孔TH2形成在隔离层206b、206a中。所述穿孔TH2穿经隔离层206b、206a，并暴露所述内连接(意即所述内连接204)先前被隔离层206a所覆盖的一些最上面的部分。所述穿孔TH2经配置以供在接下来的步骤中的其他半导体结构(意即如图4I所示的半导体结构50)的多个导电元件插入。在一些实施例中，形成所述穿孔TH2的方法包括一微影制程以及至少一蚀刻制程。
到此，已经形成一半导体结构40。半导体结构40可停留在一晶圆形式。或者是，可再进一步执行一单体化制程，且可为其中一单体化结构的半导体结构40可呈一芯片形式。在一些实施例中，在接下来的步骤中，半导体结构40可为翻转并接合在其他半导体结构上(意即如图4J所示的半导体结构50)。隔离层206a、206b的暴露表面、所述内连接204的暴露表面以及所述支撑结构210的暴露表面是集体界定半导体结构40的一接合表面41。接合表面的至少一些部分可不接触与半导体结构40接合的半导体结构。
请参考图3及图4F，执行步骤S43，且多个隔离层306a、306b、306c是形成在一基底300上，而基底300形成有一集成电路302。基底300以及集成电路302是类似于如图2A及图4A所描述的基底100、200以及集成电路102、202，仅描述在集成电路302中的多个内连接的最上面的部分，并标示成内连接304。此外，隔离层306a、306b、306c在材料与堆叠顺序方面可类似于参考图4A的隔离层206a、206b、206c(意即隔离层306a、306b、306c依序堆叠在集成电路302上)。在一些实施例中，隔离层306a、306b、306c的一总厚度是大于隔离层206a、206b、206c的一总厚度(如图4A所示)。在这些实施例中，隔离层306c的一厚度T306c可大于隔离层206c的厚度T206c(如图4A所示)。另一方面，隔离层306b的一厚度T306b可大致相同于隔离层206b的厚度T206b(如图4A所示)，以及隔离层306a的一厚度T306a可大致相同于隔离层206a的厚度T206a(如图4A所示)。或者是，厚度T306c、T306b、T306a可分别大于、等于或小于厚度T206c、T206b、T206a(如图4A所示)，只要隔离层306a、306b、306c的总厚度大于隔离层206a、206b、206c的总厚度。
请参考图3及图4G，执行步骤S45，且多个接合结构308形成在隔离层306a、306b、306c中。所述接合结构308穿经隔离层306a、306b、306c，并接触在集成电路302中的多个内连接的一些最上面的部分(意即内连接304)。在一些实施例中，所述接合结构308位在对应如图4E所示的半导体结构40的所述穿孔TH2处，且分别具有一宽度，是大致相同于每一穿孔TH2的一宽度。在如此的实施例中，所述接合结构308可插入到并填满在接下来的步骤的所述穿孔TH2(如图4J所示)。类似于如图4C所描述的所述支撑结构210，在一些实施例中，每一接合结构308具有一导电材料以及一阻障材料，是覆盖导电材料的一侧壁(意即一侧壁以及一下表面)。或者是，可省略所述阻障层。
请参考图3及图4H，执行步骤S47，并薄化隔离层306c。因此，所述接合结构309从已薄化的隔离层306c突伸。在一些实施例中，薄化隔离层306c到一厚度T306c’，是大致等于所述支撑结构210从隔离层206b突伸的高度(意即参考图4D所描述的厚度T206c)。在这些实施例中，在移除已薄化的隔离层306c的一部分(参考图4I所描述)之后，如图4E所示的所述支撑结构210与隔离层206b可同时接合在隔离层306b与隔离层306c的余留部分上(参考图4J所描述)。举例来说，薄化隔离层306c的方法可包括一回蚀制程。
请参考图3及图4I，执行步骤S49，并移除隔离层306c的一部分。形成一凹部RS’，其是由隔离层306c的余留部分以及隔离层306b的暴露部分所界定。在一些实施例中，在移除隔离层306c的该部分之后，隔离层306c先前被移除的部分是围绕所述接合结构308，且增加所述接合结构308的暴露部分的一高度。所述接合结构308的暴露部分的高度是大致等于如图4E所示的所述支撑结构210的一高度，且所述接合结构308的埋入部分的一高度是大致等于隔离层306a、306b的一总厚度。在此方法中，当半导体结构40的所述支撑结构210接合到隔离层306b的暴露表面上时，所述接合结构308可插入到所述穿孔TH1中，且恰到达所述内连接204，如图4J所示。另一方面，隔离层306c的余留部分可横向与所述接合结构308分开设置。在一些实施例中，隔离层306c的余留部分是包围所述接合结构309，并呈一环形形状。移除隔离层306c的该部分的方法可包括一微影制程以及一蚀刻制程(意即一非等向性蚀刻制程)。
到此，已经形成一半导体结构50。半导体结构50可停留在一晶圆形式。或者是，可再进一步执行一单体化制程，且可为其中一单体化结构的半导体结构50是呈一芯片形式。半导体结构50是如图4J所示与半导体结构40接合。隔离层306c的暴露表面、隔离层306b的暴露表面以及所述接合结构308的暴露表面是可集体界定半导体结构50的一接合表面51。半导体结构50的接合表面的至少一部分可不接触半导体结构40的接合表面，如接下来的步骤所述。
请参考图3及图4J到图4K，执行步骤S51，且如图4F所示的半导体结构40翻转并接合到半导体结构50上。半导体结构40的隔离层206b的一部分是接合在半导体结构50的隔离层306c上，同时半导体结构40的所述支撑结构210可接合到隔离层306c的暴露表面上，并可以或可不横向接触隔离层306c。在一些实施例中，所述支撑结构210是呈一环形形状，以围绕所述接合结构308。再者，所述支撑结构210接触隔离层306b的暴露表面，以实现半导体封装结构60的一密封环。
此外，半导体结构40的所述穿孔TH1是以半导体结构50的所述接合结构308插入，且半导体结构50的所述接合结构308的上表面是接触与所述穿孔TH1重叠的所述内连接204。由于所述支撑结构210从隔离层206b突伸的部分的高度，是大致等于隔离层306c的厚度，所以所述支撑结构210可恰到达隔离层306b的暴露表面。此外，由于所述接合结构308从隔离层306b突伸的高度是大致等于隔离层306b、206b、206a的总和，所以所述接合结构308可恰到达所述内连接204先前的暴露表面。
再者，在接合制程之前，是已移除半导体结构50的隔离层306c的一部分(参考图4I所描述)，因此半导体结构40的隔离层206b可不完全接触半导体结构50的隔离层306c。半导体结构40的隔离层206b的一部分可沿一垂直方向而不接触半导体结构50。在半导体结构40的隔离层206b与半导体结构50的隔离层306b之间的一间隔，可横向被隔离层306c所包围，并被密封在已接合的结构中，以形成一气隙AG’。所述接合结构308是横向被气隙AG’所围绕。此外，气隙AG’的一区域可分布在所述接合结构308与所述支撑结构210之间。
包含半导体结构40、50的结构是可表示成一半导体封装结构60。在一些实施例中，半导体封装结构60可进一步经历其他封装制程及/或测试程序。
如上所述，依据本公开的实施例的半导体封装结构是具有相互接合的二半导体结构，亦具有多个气隙，是密封在所述半导体结构之间的一界面处。一些气隙是位在导电元件之间，而所述导电元件经配置以建立所述半导体结构之间的电性连接。因为空气的一低的介电常数，所以可通过设置所述气隙在所述导电元件之间以降低其间的一电容耦合。因此，可降低所述导电元件的RC延迟。因此，可改善所述半导体结构的信号传输。
本公开的一实施例提供一种半导体封装结构。该半导体封装结构包括一第一半导体结构，具有一第一表面以及一第一凹部，该第一凹部是从该第一表面凹陷，且该第一半导体结构包括多个第一导电结构，所述第一导电结构是从该第一凹部的一下表面凸伸；以及一第二半导体结构，具有一第二表面以及多个第二凹部，所述第二凹部是从该第二表面凹陷，且该第二半导体结构包括多个第二导电结构，所述第二导电结构是从该第二表面凸伸，其中该第二半导体结构接合到该第一半导体结构上，所述第一导电结构插入到所述第二凹部，所述第二导电结构接触该第一凹部的该下表面，该第二表面的一部分接触该第一表面以密封该第一凹部，以便形成一气隙在该半导体封装结构中。
本公开的另一实施例提供一种半导体封装结构。该半导体封装结构包括一第一半导体结构，具有一第一接合表面以及多个第一凸部，所述第一凸部从该第一接合表面凸伸；以及一第二半导体结构，具有一第二接合表面以及多个第二凸部，所述第二凸部从该第二接合表面凸伸，该第二半导体结构接合到该第一半导体结构，其中该第一接合表面部分接触该第二接合表面，哀第一接合表面的一部分与该第二接合表面的一部分分开设置，密封该第一接合表面的该部分与该第二接合表面的该部分之间的一间隔，并形成一气隙在该半导体封装结构中；其中该气隙横向地围绕所述第一凸部设置，所述第一凸部较高于所述第二凸部，以及所述第二凸部呈一环形形状，以围绕所述第一凸部设置。
本公开的另一实施例提供一种半导体封装结构的制备方法。该方法包括：提供一第一基底，该第一基底具有一集成电路；形成多个隔离层的一第一堆叠在该集成电路上，所述隔离层的该第一堆叠具有多个第一凸部；移除所述隔离层的该第一堆叠的一最上面的隔离层；形成多个穿孔在该第一堆叠中，以形成一第一半导体结构；提供一第二基底，该第二基底具有一集成电路；形成多个隔离层的一第二堆叠在该集成电路上，所述隔离层的该第二堆叠具有多个第二凸部；形成一凹部在该第一堆叠中，以形成一第二半导体结构；以及接合该第一半导体结构与该第二半导体结构，且从该凹部形成一气隙。
虽然已详述本公开及其优点，然而应理解可进行各种变化、取代与替代而不脱离权利要求所定义的本公开的精神与范围。例如，可用不同的方法实施上述的许多制程，并且以其他制程或其组合替代上述的许多制程。
再者，本申请案的范围并不受限于说明书中所述的制程、机械、制造、物质组成物、手段、方法与步骤的特定实施例。该技艺的技术人士可自本公开的揭示内容理解可根据本公开而使用与本文所述的对应实施例具有相同功能或是达到实质上相同结果的现存或是未来发展的制程、机械、制造、物质组成物、手段、方法、或步骤。据此，此等制程、机械、制造、物质组成物、手段、方法、或步骤是包含于本申请案的权利要求内。

Claims (20)

1.一种半导体封装结构，包括：
一第一半导体结构，具有一第一表面以及一第一凹部，该第一凹部是从该第一表面凹陷，且该第一半导体结构包括多个第一导电结构，所述第一导电结构是从该第一凹部的一下表面凸伸；以及
一第二半导体结构，具有一第二表面以及多个第二凹部，所述第二凹部是从该第二表面凹陷，且该第二半导体结构包括多个第二导电结构，所述第二导电结构是从该第二表面凸伸，其中该第二半导体结构接合到该第一半导体结构上，所述第一导电结构插入到所述第二凹部，所述第二导电结构接触该第一凹部的该下表面，该第二表面的一部分接触该第一表面以密封该第一凹部，以便形成一气隙在该半导体封装结构中。
2.如权利要求1所述的半导体封装结构，其中，该气隙横向地围绕所述第一导电结构设置。
3.如权利要求1所述的半导体封装结构，其中，该第一半导体结构还包括多个第一隔离层的一堆叠以及一隔离图案，该隔离图案位在所述第一隔离层的该堆叠上，该第一表面为该隔离图案的一上表面，该隔离图案呈一环形形状，该隔离图案的一内侧壁为该第一凹部的一侧壁，以及该第一凹部的该下表面为所述第一隔离层的该堆叠的一上表面。
4.如权利要求3所述的半导体封装结构，其中，该气隙具有一高度，大致等于该隔离图案的一厚度。
5.如权利要求3所述的半导体封装结构，其中，该第二半导体结构还包括多个第二隔离层的一堆叠，该第二表面为所述第二隔离层的该堆叠的一表面，以及该第二凹部延伸经过所述第二隔离层的该堆叠。
6.如权利要求5所述的半导体封装结构，其中，所述第一导电结构从所述第一隔离层的该堆叠的该上表面凸伸的一第一厚度，大致等于该隔离图案与所述第二隔离层的该堆叠的一总厚度。
7.如权利要求5所述的半导体封装结构，其中，所述第二导电结构从所述第二隔离层的该堆叠凸伸的一第二厚度，大致等于该隔离图案的一厚度。
8.如权利要求1所述的半导体封装结构，其中，所述第一导电结构较高于所述第二导电结构，以及该第二导电结构呈一环形形状，以围绕所述第一导电结构设置。
9.一种半导体封装结构，包括：
一第一半导体结构，具有一第一接合表面以及多个第一凸部，所述第一凸部从该第一接合表面凸伸；以及
一第二半导体结构，具有一第二接合表面以及多个第二凸部，所述第二凸部从该第二接合表面凸伸，该第二半导体结构接合到该第一半导体结构，其中该第一接合表面部分接触该第二接合表面，哀第一接合表面的一部分与该第二接合表面的一部分分开设置，密封该第一接合表面的该部分与该第二接合表面的该部分之间的一间隔，并形成一气隙在该半导体封装结构中；
其中该气隙横向地围绕所述第一凸部设置，所述第一凸部较高于所述第二凸部，以及所述第二凸部呈一环形形状，以围绕所述第一凸部设置。
10.如权利要求9所述的半导体封装结构，其中，该第一接合表面具有一凹部，且所述第一凸部位在该凹部的范围内。
11.如权利要求10所述的半导体封装结构，其中，所述第二凸部接触该第一接合表面的该凹部。
12.如权利要求9所述的半导体封装结构，其中，所述第一凸部为多个导电栓塞，电性连接该第一半导体结构的一第一内连接以及该第二半导体结构的一第二内连接。
13.如权利要求12所述的半导体封装结构，其中，所述第二凸部为多个导电栓塞，接触该第二半导体的该第二内连接，并与该第一半导体的该第一内连接分开设置。
14.一种半导体封装结构的制备方法，包括：
提供一第一基底，该第一基底具有一集成电路；
形成多个隔离层的一第一堆叠在该集成电路上，所述隔离层的该第一堆叠具有多个第一凸部；
移除所述隔离层的该第一堆叠的一最上面的隔离层；
形成多个穿孔在该第一堆叠中，以形成一第一半导体结构；
提供一第二基底，该第二基底具有一集成电路；
形成多个隔离层的一第二堆叠在该集成电路上，所述隔离层的该第二堆叠具有多个第二凸部；
形成一凹部在该第一堆叠中，以形成一第二半导体结构；以及
接合该第一半导体结构与该第二半导体结构，且从该凹部形成一气隙。
15.如权利要求14所述的半导体封装结构的制备方法，其中，所述第二凸部插入到所述穿孔中，以及所述第一凸部插入到该凹部中。
16.如权利要求14所述的半导体封装结构的制备方法，其中，形成多个隔离层的一第二堆叠在该集成电路上，所述隔离层的该第二堆叠具有多个第二凸部的步骤包括：
形成多个第一穿孔在所述隔离层的该第一堆叠中；
充填所述第一穿孔，其是以导电材料进行充填；以及
移除所述隔离层的该第一堆叠的一上部。
17.如权利要求14所述的半导体封装结构的制备方法，其中，形成多个隔离层的一第一堆叠在该集成电路上，所述隔离层的该第一堆叠具有多个第一凸部的步骤包括：
形成多个第二穿孔在所述隔离层的该第二堆叠中；
充填所述第二穿孔，其是以导电材料进行充填；以及
薄化所述隔离层的该第二堆叠的一上部；
其中所述气隙的其中之一是位在其中一第一导电结构与其中一第二导电结构之间。
18.如权利要求14所述的半导体封装结构的制备方法，其中，该气隙横向地围绕所述第一凸部设置，以及所述第一凸部较高于所述第二凸部。
19.如权利要求14所述的半导体封装结构的制备方法，还包括：执行紫外光固化制程，以移除多个悬浮键，其是在该第一半导体结构与该第二半导体结构接合之前执行。
20.如权利要求14所述的半导体封装结构的制备方法，还包括：执行一快速热氮化，以增浓一钝化层。
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US11309249B2 (en) 2022-04-19
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