TW202143427A - 具有氣隙的半導體封裝結構及其製備方法 - Google Patents

具有氣隙的半導體封裝結構及其製備方法 Download PDF

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TW202143427A
TW202143427A TW110112882A TW110112882A TW202143427A TW 202143427 A TW202143427 A TW 202143427A TW 110112882 A TW110112882 A TW 110112882A TW 110112882 A TW110112882 A TW 110112882A TW 202143427 A TW202143427 A TW 202143427A
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semiconductor
stack
protrusions
isolation
isolation layers
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TW110112882A
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TWI763421B (zh
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黃則堯
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南亞科技股份有限公司
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Abstract

本揭露提供一種具有氣隙以降低在導電特徵之間之電容耦合的半導體封裝結構及該半導體封裝結構的製備方法。該半導體封裝結構具有一第一半導體結構以及一第二半導體結構，該第二半導體結構與該第一半導體結構接合在一起。該第一半導體結構具有一第一接合表面。該第二半導體結構具有一第二接合表面，該第二接合表面部分接觸該第一接合表面。該第一接合表面的一部分與該第二接合表面的一部分分開設置，密封該第一接合表面的該部分與該第二表面的該部分之間的間隔，並形成一氣隙在該半導體封裝結構中。

Description

具有氣隙的半導體封裝結構及其製備方法
本申請案主張2020年5月4日申請之美國正式申請案第16/865,909號的優先權及益處，該美國正式申請案之內容以全文引用之方式併入本文中。
本揭露係關於一種半導體封裝結構及其製備方法。特別是有關於一種具有氣隙半導體封裝結構及其製備方法，其係用以降低在導電特徵之間的電容耦合。
近年來，由於持續改善各式不同電子元件的整合密度，所以半導體產業經歷了快速成長。這些尺寸的電子元件需要更小的封裝結構，而相較於先前的封裝結構，這些更小的封裝結構係佔據更小的面積。然而，可以在二維(2D)達到該半導體封裝結構之規格係具有物理上的限制。當二維規格仍然是新設計的一種選擇時，採用利用z方向的三維(3D)封裝方案係已成為業界研究的重點。儘管如此，三維封裝技術仍面臨著挑戰。
上文之「先前技術」說明僅係提供背景技術，並未承認上文之「先前技術」說明揭示本揭露之標的，不構成本揭露之先前技術，且上文之「先前技術」之任何說明均不應作為本案之任一部分。
本揭露之一實施例提供一種半導體封裝結構。該半導體封裝結構包括一第一半導體結構，具有一第一表面以及一第一凹部，該第一凹部係從該第一表面凹陷，且該第一半導體結構包括多個第一導電結構，該等第一導電結構係從該第一凹部的一下表面凸伸；以及一第二半導體結構，具有一第二表面以及多個第二凹部，該等第二凹部係從該第二表面凹陷，且該第二半導體結構包括多個第二導電結構，該等第二導電結構係從該第二表面凸伸，其中該第二半導體結構接合到該第一半導體結構上，該等第一導電結構插入到該等第二凹部，該等第二導電結構接觸該第一凹部的該下表面，該第二表面的一部分接觸該第一表面以密封該第一凹部，以便形成一氣隙在該半導體封裝結構中。
在本揭露的一些實施例中，該氣隙橫向地圍繞該等第一導電結構設置。
在本揭露的一些實施例中，該第一半導體結構還包括多個第一隔離層的一堆疊以及一隔離圖案，該隔離圖案位在該等第一隔離層的該堆疊上，該第一表面為該隔離圖案的一上表面，該隔離圖案呈一環形形狀，該隔離圖案的一內側壁為該第一凹部的一側壁，以及該第一凹部的該下表面為該等第一隔離層之該堆疊的一上表面。
在本揭露的一些實施例中，該氣隙具有一高度，大致等於該隔離圖案的一厚度。
在本揭露的一些實施例中，該第二半導體結構還包括多個第二隔離層的一堆疊，該第二表面為該等第二隔離層之該堆疊的一表面，以及該第二凹部延伸經過該等第二隔離層之該堆疊。
在本揭露的一些實施例中，該等第一導電結構從該等第一隔離層之該堆疊的該上表面凸伸的一第一厚度，大致等於該隔離圖案與該等第二隔離層之該堆疊的一總厚度。
在本揭露的一些實施例中，該等第二導電結構從該等第二隔離層之該堆疊凸伸的一第二厚度，大致等於該隔離圖案的一厚度。
在本揭露的一些實施例中，該等第一導電結構較高於該等第二導電結構，以及該第二導電結構呈一環形形狀，以圍繞該等第一導電結構設置。
本揭露之另一實施例提供一種半導體封裝結構。該半導體封裝結構包括一第一半導體結構，具有一第一接合表面以及多個第一凸部，該等第一凸部從該第一接合表面凸伸；以及一第二半導體結構，具有一第二接合表面以及多個第二凸部，該等第二凸部從該第二接合表面凸伸，該第二半導體結構接合到該第一半導體結構，其中該第一接合表面部分接觸該第二接合表面，哀第一接合表面的一部分與該第二接合表面的一部份分開設置，密封該第一接合表面的該部分與該第二接合表面的該部分之間的一間隔，並形成一氣隙在該半導體封裝結構中；其中該氣隙橫向地圍繞該等第一凸部設置，該等第一凸部較高於該等第二凸部，以及該等第二凸部呈一環形形狀，以圍繞該等第一凸部設置。
在本揭露的一些實施例中，該第一接合表面具有一凹部，且該等第一凸部位在該凹部的範圍內。
在本揭露的一些實施例中，該等第二凸部接觸該第一接合表面的該凹部。
在本揭露的一些實施例中，該等第一凸部為多個導電栓塞，電性連接該第一半導體結構的一第一內連接以及該第二半導體結構的一第二內連接。
在本揭露的一些實施例中，該等第二凸部為多個導電栓塞，接觸該第二半導體的該第二內連接，並與該第一半導體的該第一內連接分開設置。
本揭露之另一實施例提供一種半導體封裝結構的製備方法。該方法包括：提供一第一基底，該第一基底具有一積體電路；形成多個隔離層的一第一堆疊在該積體電路上，該等隔離層的該第一堆疊具有多個第一凸部；移除該等隔離層之該第一堆疊的一最上面的隔離層；形成多個穿孔在該第一堆疊中，以形成一第一半導體結構；提供一第二基底，該第二基底具有一積體電路；形成多個隔離層的一第二堆疊在該積體電路上，該等隔離層的該第二堆疊具有多個第二凸部；形成一凹部在該第一堆疊中，以形成一第二半導體結構；以及接合該第一半導體結構與該第二半導體結構，且從該凹部形成一氣隙。
在本揭露的一些實施例中，該等第二凸部插入到該等穿孔中，以及該等第一凸部插入到該凹部中。
在本揭露的一些實施例中，形成多個隔離層的一第二堆疊在該積體電路上，該等隔離層的該第二堆疊具有多個第二凸部的步驟包括：形成多個第一穿孔在該等隔離層的該第一堆疊中；充填該等第一穿孔，其係以導電材料進行充填；以及移除該等隔離層之該第一堆疊的一上部。
在本揭露的一些實施例中，形成多個隔離層的一第一堆疊在該積體電路上，該等隔離層的該第一堆疊具有多個第一凸部的步驟包括：形成多個第二穿孔在該等隔離層的該第二堆疊中；充填該等第二穿孔，其係以導電材料進行充填；以及薄化該等隔離層之該第二堆疊的一上部；其中該等氣隙的其中之一係位在其中一第一導電結構與其中一第二導電結構之間。
在本揭露的一些實施例中，該氣隙橫向地圍繞該等第一凸部設置，以及該等第一凸部較高於該等第二凸部。
在本揭露的一些實施例中，該半導體封裝結構的製備方法還包括：執行紫外光固化製程，以移除多個懸浮鍵(dangling bonds)，其係在該第一半導體結構與該第二半導體結構接合之前執行。
在本揭露的一些實施例中，該半導體封裝結構的製備方法還包括：執行一快速熱氮化(rapid thermal nitridation)，以增濃一鈍化層。
綜上所述，依據本揭露之一些實施例的半導體封裝結構，係具有相互接合在一起的二半導體結構，亦具有多個氣隙，密封在導電元件之間，而該等導電元件係經配置以建立在該等半導體結構之間的電性連接。因為空氣的一低的介電常數，所以可藉由設置在該等導電元件之間的氣隙而降低在其間的一電容耦合。因此，可降低該等導電元件的電阻-電容延遲(RC delay)。因此，可改善該等半導體結構之間的訊號傳輸。
上文已相當廣泛地概述本揭露之技術特徵及優點，俾使下文之本揭露詳細描述得以獲得較佳瞭解。構成本揭露之申請專利範圍標的之其它技術特徵及優點將描述於下文。本揭露所屬技術領域中具有通常知識者應瞭解，可相當容易地利用下文揭示之概念與特定實施例可作為修改或設計其它結構或製程而實現與本揭露相同之目的。本揭露所屬技術領域中具有通常知識者亦應瞭解，這類等效建構無法脫離後附之申請專利範圍所界定之本揭露的精神和範圍。
以下描述了組件和配置的具體範例，以簡化本揭露之實施例。當然，這些實施例僅用以例示，並非意圖限制本揭露之範圍。舉例而言，在敘述中第一部件形成於第二部件之上，可能包含形成第一和第二部件直接接觸的實施例，也可能包含額外的部件形成於第一和第二部件之間，使得第一和第二部件不會直接接觸的實施例。另外，本揭露之實施例可能在許多範例中重複參照標號及/或字母。這些重複的目的是為了簡化和清楚，除非內文中特別說明，其本身並非代表各種實施例及/或所討論的配置之間有特定的關係。
此外，為易於說明，本文中可能使用例如「之下(beneath)」、「下面(below)」、「下部的(lower)」、「上方(above)」、「上部的(upper)」等空間相對關係用語來闡述圖中所示的一個元件或特徵與另一(其他)元件或特徵的關係。所述空間相對關係 用語旨在除圖中所繪示的取向外亦囊括元件在使用或操作中的不同取向。所述裝置可具有其他取向(旋轉90度或處於其他取向)且本文中所用的空間相對關係描述語可同樣相應地進行解釋。
圖1為依據本揭露一些實施例中一種半導體結構之製備方法M30的流程示意圖。圖2A到圖2I為依據本揭露一些實施例在如圖1所示的製造程序期間之各不同階段的剖視示意圖。
請參考圖1及圖2A，執行步驟S11，以及提供一基底100，基底100具有一積體電路102。在一些實施例中，基底100為一晶圓形式。在這些實施例中，基底100可為一半導體晶圓或一絕緣體上覆半導體(SOI)晶圓。舉例來說，在半導體晶圓或SOI經援中的一半導體材料可包含一元素半導體(意即矽(Si))、一合金半導體(意即矽鍺(SiGe))、一化合物半導體(意即III-V族半導體、II-VI族半導體)或是其組合。此外，半導體材料可摻雜有一第一導電類型(意即N型)或一第二導電類型(意即P型)，而第二導電類型係與第一導電類型互補。在那些實施例中，在基底100程一晶圓形式的情況下，基底100具有多個晶粒區，該等晶粒區係藉由一切割線區(scribe line region)(圖未示)而相互分隔設置，以及積體電路102佈設在該等晶粒區內。積體電路102可具有多個主動元件及/或多個被動元件(均未圖示)，其係形成在基底100的一表面處，且積體電路102可具有多個內連接在該等主動元件及/或該等被動元件上。該等內連接經配置以內連接該等主動元件及/或該等被動元件，並佈線(route)該等主動元件及/或該等被動元件到積體電路102的一上側。舉例來說，該等主動元件可包括金屬氧化物半導體場效電晶體(MOSFETs)，而該等被動元件可包括電容器。再者，該等內連接可形成在多個介電層的一堆疊中，並可分別包括導電線跡(traces)以及多個導電通孔(vias)，該等導電線跡係延伸在其中一介電層的一表面上，而該等通孔垂直延伸並連接到至少一導電線跡。應當理解，在圖2A中僅描述該等內連接之最上面的部分，且標示該等內連接的編號為104。此外，積體電路102的一上側可表示成均勻形成之半導體結構(意即如圖2F所示的半導體結構)的一主動側，同時基底100的一下側可表示成半導體結構的一背側。
請參考圖1及圖2B，執行步驟S13，且多個隔離層106的一堆疊(意即二隔離層106)以及多個接合結構108與多個支撐結構110形成在積體電路102上。該等接合結構108與該等支撐結構110穿經該等隔離層106的堆疊。應當理解，僅描述其中一接合結構108與其中一支撐結構110。該等接合結構108電性連接到該等內連接(意即內連接104)之最上面的部分，並可當作是積體電路102的輸入/輸出(I/Os)。在一些實施例中，該等接合結構108分別具有一接合墊108a以及一佈線結構108c，而佈線結構108c係連接接合墊108a到該等內連接(意即內連接104)之最上面的部分。接合墊108a可形成在最上面的隔離層106中，並具有一上表面，係大致與最上面之隔離層106的一上表面為共面。佈線結構108c係例如一導電通孔或一導電柱(pillar)，係從接合墊108a的一下端延伸到該等內連接(意即內連接104)之最上面的部分。另一方面，該等支撐結構110可形成如導電通孔或導電柱，並延伸經過該等隔離層106的堆疊。在一些實施例中，該等支撐結構110可電性連接到該等內連接(意即內連接104)之最上面的部分。在這些實施例中，該等連接的內連接104與該等支撐結構110可電性浮接(electrically floated)，並經配置以加強均勻形成之半導體結構(意即如圖2H所示的半導體封裝結構30)的機構強度。或者是，該等連接的內連接104與該等支撐結構110可電性接地(electrically grounded)，並可當作是積體電路102的電磁屏蔽。在其他實施例中，該等支撐結構110可不電性連接到任何該等內連接104，並可電性浮接或電性接地。
再者，在一些實施例中，該等支撐結構110可相互連接，以形成一壁體，而此壁體橫向圍繞該等接合結構108。在這些實施例中，壁體可當作是一密封環。在其他實施例中，該等支撐結構110橫向相互分開設置，並與該等接合結構108橫向被一密封環(圖未示)所圍繞。
該等隔離層106的一材料可包含一非有機隔離材料(意即氧化矽、氮化矽、氮氧化矽、類似物或其組合)，同時該等接合結構108與該等支撐結構110可由一導電材料所製，例如一金屬或一金屬合金(意即銅、銅合金、類似物或其組合)。在一些實施例中，形成每一隔離層106的方法可包括一沉積製程(意即一化學氣相沉積(CVD)製程)，同時形成該等接合結構108與該等支撐結構110在該等隔離層103之堆疊的方法，可包括至少一鑲嵌(damascene)製程。然而，所屬技術領域中具有通常知識者可選擇其他適合的材料及/或其他適當之形成該等隔離層106、該等接合結構108與該等支撐結構110的方法，本揭露並不以此為限。
在一些實施例中，在該等接合結構108與該等支撐結構110中的導電材料係藉由一阻障層(圖未示)而與該等隔離層106的堆疊分開設置。該等阻障層的一材料(之後以一阻障材料表示)可包含Ti、TiN、Ta、TaN、類似物或其組合。此外，形成阻障層的方法可包括一沉積製程，例如物理氣相沉積(PVD)製程或原子層沉積(ALD)製程。
請參考圖1及圖2C，執行步驟S15，且一遮罩圖案PR形成在該等隔離層106的堆疊上。遮罩圖案PR係例如一光阻圖案，具有多個開口W，該等開口W係界定多個凹部的位置，並在接下來的步驟(意即如圖2D所示的該等凹部RS)期間，形成在該等隔離層106的堆疊中。每一開口W係橫向與該等接合結構108以及該等支撐結構110分開設置。一些開口W係分別位在其中一接合結構108與其中一支撐結構110之間、在相鄰接合結構108之間，或者是在相鄰支撐結構110之間。此外，一些其他開口W可位在該等接合結構108與該等支撐結構110之一分布範圍的外側。在那些實施例中，在遮罩圖案PR為一光阻圖案的情況下，形成遮罩圖案PR的方法可包括一塗佈(coating)製程以及一微影(lithography)製程。
請參考圖1及圖2D，執行步驟S17，以及為了形成該等凹部RS在該等隔離層106之堆疊的一上區域中，藉由使用遮罩圖案PR當作一陰影遮罩(shadow mask)，以移除該等隔離層106之堆疊的一些部分。在一些實施例中，藉由一蝕刻製程移除該等隔離層106與遮罩圖案PR之該等開口W重疊的一些部分，以形成該等凹部RS，而蝕刻製程係例如一非等向性蝕刻製程。如同遮罩圖案PR的該等開口W，每一凹部RS橫向與該等接合結構108以及該等支撐結構110分開設置。一些凹部RS分別位在其中一接合結構108與其中一支撐結構110之間。此外，一些其他凹部RS可位在該等接合結構108與該等支撐結構110之分布範圍的外側。在一些實施例中，移除最外面之隔離層106與該等開口W重疊的一些部分，同時塗佈在隔離層106下之最外面的隔離層106可大致維持完整。在這些實施例中，在參考圖2B的步驟S13期間，一蝕刻終止層(圖未示)可設置在二垂直的相鄰隔離層106中間，且相對於這些隔離層106可具有足夠的蝕刻選擇性。在此方法中，在形成該等凹部RS之後，可暴露蝕刻終止層與該等開口W重疊的一些部分，並可界定該等凹部RS的下表面。或者是，可省略蝕刻終止層，且在蝕刻期間，可或不可部分移除塗佈在最外面之隔離層106下的隔離層106。
請參考圖1及圖2E，執行步驟S19，並可整體形成一鈍化層112。因此，鈍化層112係覆蓋隔離層106之堆疊的上表面、該等接合結構108的上表面以及該等支撐結構110的上表面。在一些實施例中，鈍化層112共形地覆蓋下層結構。在這些實施例中，該等凹部RS並未被鈍化層112所填滿，且鈍化層112凹陷在相對應之該等凹部RS，而該等凹部RS係位在該等隔離層106之堆疊的上區域中。舉例來說，鈍化層112的一材料包含氮化矽。此外，形成鈍化層112的方法可包括一沉積製程，例如一原子層沉積(ALD)製程。然而，所屬技術領域中具有通常知識者可選擇其他可行的隔離材料及/或其他適合的形成鈍化層112的形成方法，本揭露並不以此為限。
請參考圖1及圖2F，執行步驟S21，並移除鈍化層112位在最外面之隔離層106的一上表面上的一些部分。因此，僅保留鈍化層112位在該等凹部RS中的一些部分，且其每一個係表示成一鈍化層112a。此外，暴露最外面之隔離層106的上表面以及該等接合結構108與該等支撐結構110的上表面。在一些實施例中，移除鈍化層112一些部分的方法可包括一平坦化製程。舉例來說，平坦化製程可包括一化學機械研磨(CMP)製程、一蝕刻製程或其組合。
在一些實施例中，鈍化層112a係由氮化矽所構成，且在步驟S21之後執行一快速熱氮化(RTN)製程。藉由執行RTN製程，在鈍化層112a中的氮化矽可再進一步增濃。在其他實施例中，鈍化層112a可由氧化矽所製，且在遭受RTN製程之後，氧化矽可轉變成氮氧化矽或氮化矽。再者，在一些實施例中，可執行一紫外光(UV)固化製程，以移除在多個導電元件中的懸浮鍵(dangling bonds)(意即該等接合結構108、該等支撐結構110以及積體電路102的該等內連接)。在這些實施例中，紫外光固化製程可接著RTN製程進行，但本揭露並不以此為限。
到此，係形成一半導體結構10。半導體結構10係與其他半導體結構(意即如圖2G所示的半導體結構20)接合在一起，且最外面之隔離層106的暴露表面、鈍化層112a的暴露表面、該等接合結構108的暴露表面以及該等支撐結構110的暴露表面係集體界定半導體結構10的一接表面11。接合表面的至少一些部分(意即在該等凹部RS中之鈍化層112a的表面)可不接觸接下來接合的半導體結構(意即如圖2G所示的半導體結構20)。在一些實施例中，半導體結構10停留在一晶圓形式。在其他實施例中，一單體化製程(singulation process)係執行在如圖2F的結構上，以使可為其中一單體化結構之半導體結構10呈一晶片形式。
請參考圖1及圖2G，執行步驟S23，並提供一半導體結構20。在一些實施例中，藉由參考圖2A到圖2F所描述的方法以提供半導體結構20。為了避免重複描述，在半導體結構10、20中的元件係標示相同。類似於半導體結構10，半導體結構20可停留在一晶圓形式。或者是，可再進一步執行一單體化製程，且可為多個單體化結構之一的半導體結構20係呈一晶片形式。半導體結構20係接合到半導體結構10上，且最外面之隔離層106的暴露表面、鈍化層112a的暴露表面、該等接合結構108的暴露表面以及該等支撐結構110的暴露表面係集體界定半導體結構20的一接合表面21。接合表面21的至少一些部分(意即在該等凹部RS中之鈍化層112a的表面)可不參與在半導體結構10、20的接合中。
請參考圖1及圖2H到圖2I，執行步驟S25，以及半導體結構10、20係相互接合在一起，以形成一半導體封裝結構30。關於半導體結構10、20可分別呈一晶圓形式或一晶片形式，則半導體封裝結構30可為一晶圓上晶圓(wafer-on-wafer)結構、一晶圓上晶片(chip-on-wafer)結構或一晶片上晶片(chip-on-chip)結構。一旦半導體結構10、20接合在一起，則半導體結構10、20的接合表面係部分相互接觸。在一些實施例中，半導體結構10、20之最外面的隔離層103可相互接合，且半導體結構10之該等隔離層106的堆疊與半導體結構20之該等隔離層106的堆疊係連接，以形成該等隔離層106的一組合堆疊。此外，半導體結構10、20的該等接合結構108係相互接合，且建立在半導體結構10、20之間的積體電路102之間的電性連接。再者，來自半導體結構10、20之該等支撐結構110係相互接合，並可電性浮接或電性接地。另一方面，半導體結構10、20的該等凹部RS係相互對準，以使半導體結構10之鈍化層112a的垂直延伸部分與半導體結構20之鈍化層112a的垂直延伸部分接合在一起。據此，在該等凹部RS中的腔室可被半導體結構10、20的鈍化層112a所密封，並形成氣隙AG在已接合的結構(意即半導體封裝結構30)中。該等氣隙AG係分別被相互接合之二鈍化層112所包圍。該等接合結構108、該等支撐結構110、該等鈍化層112a以及該等氣隙AG係位在該等隔離層106的組合堆疊中。當從該等凹部RS繼承時，一些氣隙AG係位在該等接合結構108與該等支撐結構110的一分布範圍內，同時一些其他氣隙AG係位在該等接合結構108與該等支撐結構110的分布範圍外側。
在一些實施例中，接合半導體結構10、20的方法包括置放其中一半導體結構10、20在另一個上，舉例來說，係藉由取放(pick and place，PNP)製程，以及執行一混合接合(hybrid bonding)製程以建立一實體接合在半導體結構10、20之間。在一些實施例中，混合接合製程係執行在真空或惰性大氣中，以便避免該等導電元件的氧化及/或濕氣入侵。混合接合製程可包括一第一加熱步驟以及一第二加熱步驟，第一加熱步驟係用於接合多個隔離元件，而第二加熱步驟係用於接合該等導電元件。舉例來說，該等隔離元件可包括已貼合的該等隔離層106與該等鈍化層112a，同時該等導電元件可包括已貼合的該等接合結構108與該等支撐結構110。在一些實施例中，第一加熱步驟先於第二加熱製程。此外，第一加熱步驟的一加熱溫度係較低於第二加熱步驟的一加熱溫度。舉例來說，第一加熱步驟的加熱溫度可從150℃到250℃之間的範圍，同時第二加熱步驟的加熱溫度可從180℃到350℃之間的範圍。然而，所屬技術領域中具有通常知識者可依據製程所需而調整第一加熱步驟與第二加熱步驟的順序以及加熱溫度，但本揭露並不以此為限。
因為空氣的一低的介電常數(意即大約為1)，所以藉由設置該等氣隙AG而可降低橫向相鄰接合結構108之間的一電容耦合。類似地，因為該等氣隙AG，所以可降低該等接合結構108與該等支撐結構110之間的一電容耦合。因此，可降低該等接合結構108的延遲(RC延遲)。因此，可改善半導體結構10、20的積體電路102之間的訊號傳輸。
圖3為依據本揭露一些實施例中一種半導體結構之製備方法M60的流程示意圖。圖4A到圖4K為依據本揭露一些實施例在如圖3所示的製造程序期間之各不同階段的剖視示意圖。參考圖3及圖4A到圖4K所描述的實施例，係類似於參考如圖1及圖2A到圖2I所描述的實施例，並僅討論其間的差異，相同或類似的部分則不再重複。此外，類似的編號係代表類似或相同的元件(意即基底100以及基底200)。
請參考圖3及圖4A，執行步驟S31，且提供一基底200，基底具有一積體電路202。應當理解，僅描述在積體電路202中多個內連接之之最上面的部分，且標示為內連接204。
接下來，執行步驟S33，且隔離層206a、206b、206c形成在積體電路202上。隔離層206a塗佈在隔離層206b、206c下方，且隔離層206b夾置在隔離層206a、206c之間。隔離層206a具有一厚度T206a，隔離層206b具有一厚度T206b，以及隔離層206c具有一厚度T206c。在一些實施例中，厚度T206b小於厚度T206a與厚度T206c，且厚度T206a可大於、等於或小於厚度T206c。此外，在一些實施例中，隔離層206b的一材料係不同於隔離層206a、206c的一材料。舉例來說，隔離層206b可由氮化矽所構成，同時隔離層206a、206c可由氧化矽所構成。形成每一隔離層206a、206b、206c的方法可包括一沉積製程，例如一CVD製程。然而，所屬技術領域中具有通常知識者可調整隔離層206a、206b、206c的厚度T206a、T206b、T206c，並選擇適合的材料以及形成隔離層206a、206b、206c的形成方法，本揭露並不以此為限。
請參考圖3及圖4B，執行步驟S35，且多個穿孔TH1形成在隔離層206a、206b、206c中。該等穿孔TH1穿經隔離層206a、206b、206c，並暴露該等內連接(意即內連接204)的一些最上面的部分。在一些實施例中，暴露的內連接204係位在接近晶粒區(參考圖2A的描述)的一邊緣處。形成該等穿孔TH1的方法可包括執行一微影製程以及一或多個蝕刻製程(意即非等向性蝕刻製程)。
請參考圖3及圖4C，執行步驟S37，且多個支撐結構210形成在該等穿孔TH1中。該等支撐結構210接觸先前暴露的該等內連接204。已連接的該等支撐結構210與該等內連接201係電性浮接或電性接地。在一些實施例中，形成該等支撐結構210的方法包括充填一導電材料進入該等穿孔TH1，其係藉由一沉積製程(意即一物理氣相沉積(PVD)製程)、一鍍覆製程(意即一電鍍製程或一無電鍍覆製程)或其組合所實現。此外，可執行一平坦化製程以移除導電材料在隔離層206c之一上表面上的一些部分。舉例來說，導電材料可包含一金屬或一金屬合金(意即銅、銅合金、類似物或其組合)。此外，舉例來說，平坦化製程可包括一CMP製程、一蝕刻製程或其組合。
在一些實施例中，每一支撐結構210還包括一阻障層(圖未示)，係覆蓋在每一穿孔TH1中之導電材料的一側壁(意即一側壁以及一下表面)。阻障層的一材料(之後表示成一阻障材料)可包括Ti、TiN、Ta、TaN、類似物或其組合。此外，形成該等阻障層的方法包括充填阻障材料進入該等穿孔TH1，其係藉由一沉積製程所實現，例如一PVD製程或一ALD製程。在一些實施例中，可移除阻障材料位在隔離層206c之表面上的一些部分，其係使用用於移除導電材料位在隔離層206c之上表面上的一些部分之平坦化製程所實現。
請參考圖3及圖4D，執行步驟S39，並移除隔離層206c。當隔離層206c移除時，係暴露隔離層206b的一上表面以及該等支撐結構210之個側壁的上部。此外，該等支撐結構210目前從隔離層206b的上表面凸伸一高度，係大致等於移除之隔離層206c的厚度(意即如圖4A所示的厚度T206c)。
請參考圖3及圖4E，執行步驟S41，且多個穿孔TH2形成在隔離層206b、206a中。該等穿孔TH2穿經隔離層206b、206a，並暴露該等內連接(意即該等內連接204)先前被隔離層206a所覆蓋之一些最上面的部分。該等穿孔TH2經配置以供在接下來的步驟中之其他半導體結構(意即如圖4I所示之半導體結構50)的多個導電元件插入。在一些實施例中，形成該等穿孔TH2的方法包括一微影製程以及至少一蝕刻製程。
到此，已經形成一半導體結構40。半導體結構40可停留在一晶圓形式。或者是，可再進一步執行一單體化製程，且可為其中一單體化結構之半導體結構40可呈一晶片形式。在一些實施例中，在接下來的步驟中，半導體結構40可為翻轉並接合在其他半導體結構上(意即如圖4J所示的半導體結構50)。隔離層206a、206b的暴露表面、該等內連接204的暴露表面以及該等支撐結構210的暴露表面係集體界定半導體結構40的一接合表面41。接合表面的至少一些部分可不接觸與半導體結構40接合的半導體結構。
請參考圖3及圖4F，執行步驟S43，且多個隔離層306a、306b、306c係形成在一基底300上，而基底300形成有一積體電路302。基底300以及積體電路302係類似於如圖2A及圖4A所描述之基底100、200以及積體電路102、202，僅描述在積體電路302中之多個內連接的最上面的部分，並標示成內連接304。此外，隔離層306a、306b、306c在材料與堆疊順序方面可類似於參考圖4A的隔離層206a、206b、206c(意即隔離層306a、306b、306c依序堆疊在積體電路302上)。在一些實施例中，隔離層306a、306b、306c的一總厚度係大於隔離層206a、206b、206c的一總厚度(如圖4A所示)。在這些實施例中，隔離層306c的一厚度T306c可大於隔離層206c的厚度T206c(如圖4A所示)。另一方面，隔離層306b的一厚度T306b可大致相同於隔離層206b的厚度T206b(如圖4A所示)，以及隔離層306a的一厚度T306a可大致相同於隔離層206a的厚度T206a(如圖4A所示)。或者是，厚度T306c、T306b、T306a可分別大於、等於或小於厚度T206c、T206b、T206a(如圖4A所示)，只要隔離層306a、306b、306c的總厚度大於隔離層206a、206b、206c的總厚度。
請參考圖3及圖4G，執行步驟S45，且多個接合結構308形成在隔離層306a、306b、306c中。該等接合結構308穿經隔離層306a、306b、306c，並接觸在積體電路302中之多個內連接之一些最上面的部分(意即內連接304)。在一些實施例中，該等接合結構308位在對應如圖4E所示之半導體結構40的該等穿孔TH2處，且分別具有一寬度，係大致相同於每一穿孔TH2的一寬度。在如此的實施例中，該等接合結構308可插入到並填滿在接下來之步驟的該等穿孔TH2(如圖4J所示)。類似於如圖4C所描述的該等支撐結構210，在一些實施例中，每一接合結構308具有一導電材料以及一阻障材料，係覆蓋導電材料的一側壁(意即一側壁以及一下表面)。或者是，可省略該等阻障層。
請參考圖3及圖4H，執行步驟S47，並薄化隔離層306c。因此，該等接合結構309從已薄化的隔離層306c突伸。在一些實施例中，薄化隔離層306c到一厚度T306c’，係大致等於該等支撐結構210從隔離層206b突伸的高度(意即參考圖4D所描述的厚度T206c)。在這些實施例中，在移除已薄化之隔離層306c之一部分(參考圖4I所描述)之後，如圖4E所示之該等支撐結構210與隔離層206b可同時接合在隔離層306b與隔離層306c的餘留部分上(參考圖4J所描述)。舉例來說，薄化隔離層306c的方法可包括一回蝕製程。
請參考圖3及圖4J，執行步驟S49，並移除隔離層306c的一部份。形成一凹部RS’，其係由隔離層306c的餘留部分以及隔離層306b的暴露部分所界定。在一些實施例中，在移除隔離層306c的該部分之後，隔離層306c先前被移除的部分係圍繞該等接合結構308，且增加該等接合結構308之暴露部分的一高度。該等接合結構308之暴露部分的高度係大致等於如圖4E所示之該等支撐結構210的一高度，且該等接合結構308之埋入部分的一高度係大致等於隔離層306a、306b的一總厚度。在此方法中，當半導體結構40的該等支撐結構210接合到隔離層306b的暴露表面上時，該等接合結構308可插入到該等穿孔TH1中，且恰到達該等內連接204，如圖4J所示。另一方面，隔離層306c的餘留部分可橫向與該等接合結構308分開設置。在一些實施例中，隔離層306c的餘留部分係包圍該等接合結構309，並呈一環形形狀。移除隔離層306c之該部分的方法可包括一微影製程以及一蝕刻製程(意即一非等向性蝕刻製程)。
到此，已經形成一半導體結構50。半導體結構50可停留在一晶圓形式。或者是，可再進一步執行一單體化製程，且可為其中一單體化結構的半導體結構50係呈一晶片形式。半導體結構50係如圖4J所示與半導體結構40接合。隔離層306c的暴露表面、隔離層306b的暴露表面以及該等接合結構308的暴露表面係可集體界定半導體結構50的一接合表面51。半導體結構50之接合表面的至少一部分可不接觸半導體結構40的接合表面，如接下來的步驟所述。
請參考圖3及圖4K到圖4K，執行步驟S51，且如圖4F所示的半導體結構40翻轉並接合到半導體結構50上。半導體結構40之隔離層206b的一部份係接合在半導體結構50的隔離層306c上，同時半導體結構40的該等支撐結構210可接合到隔離層306c之的暴露表面上，並可以或可不橫向接觸隔離層306c。在一些實施例中，該等支撐結構210係呈一環形形狀，以圍繞該等接合結構308。再者，該等支撐結構210接觸隔離層306b的暴露表面，以實現半導體封裝結構60的一密封環。
此外，半導體結構40的該等穿孔TH1係以半導體結構50的該等接合結構308插入，且半導體結構50之該等接合結構308的上表面係接觸與該等穿孔TH1重疊的該等內連接204。由於該等支撐結構210從隔離層206b突伸之部分的高度，係大致等於隔離層306c的厚度，所以該等支撐結構210可恰到達隔離層306b的暴露表面。此外，由於該等接合結構308從隔離層306b突伸的高度係大致等於隔離層306b、206b、206a的總和，所以該等接合結構308可恰到達該等內連接204先前的暴露表面。
再者，在接合製程之前，係已移除半導體結構50之隔離層306c的一部份(參考圖4I所描述)，因此半導體結構40的隔離層206b可不完全接觸半導體結構50的隔離層306c。半導體結構40之隔離層206b的一部分可沿一垂直方向而不接觸半導體結構50。在半導體結構40的隔離層206b與半導體結構50的隔離層306b之間的一間隔，可橫向被隔離層306c所包圍，並被密封在已接合的結構中，以形成一氣隙AG’。該等接合結構308係橫向被氣隙AG’所圍繞。此外，氣隙AG’的一區域可分布在該等接合結構308與該等支撐結構210之間。
包含半導體結構40、50的結構係可表示成一半導體封裝結構60。在一些實施例中，半導體封裝結構60可進一步經歷其他封裝製程及/或測試程序。
如上所述，依據本揭露之實施例的半導體封裝結構係具有相互接合的二半導體結構，亦具有多個氣隙，係密封在該等半導體結構之間的一界面處。一些氣隙係位在導電元件之間，而該等導電元件經配置以建立該等半導體結構之間的電性連接。因為空氣之一低的介電常數，所以可藉由設置該等氣隙在該等導電元件之間以降低其間的一電容耦合。因此，可降低該等導電元件的RC延遲。因此，可改善該等半導體結構的訊號傳輸。
本揭露之一實施例提供一種半導體封裝結構。該半導體封裝結構包括一第一半導體結構，具有一第一表面以及一第一凹部，該第一凹部係從該第一表面凹陷，且該第一半導體結構包括多個第一導電結構，該等第一導電結構係從該第一凹部的一下表面凸伸；以及一第二半導體結構，具有一第二表面以及多個第二凹部，該等第二凹部係從該第二表面凹陷，且該第二半導體結構包括多個第二導電結構，該等第二導電結構係從該第二表面凸伸，其中該第二半導體結構接合到該第一半導體結構上，該等第一導電結構插入到該等第二凹部，該等第二導電結構接觸該第一凹部的該下表面，該第二表面的一部分接觸該第一表面以密封該第一凹部，以便形成一氣隙在該半導體封裝結構中。
本揭露之另一實施例提供一種半導體封裝結構。該半導體封裝結構包括一第一半導體結構，具有一第一接合表面以及多個第一凸部，該等第一凸部從該第一接合表面凸伸；以及一第二半導體結構，具有一第二接合表面以及多個第二凸部，該等第二凸部從該第二接合表面凸伸，該第二半導體結構接合到該第一半導體結構，其中該第一接合表面部分接觸該第二接合表面，哀第一接合表面的一部分與該第二接合表面的一部份分開設置，密封該第一接合表面的該部分與該第二接合表面的該部分之間的一間隔，並形成一氣隙在該半導體封裝結構中；其中該氣隙橫向地圍繞該等第一凸部設置，該等第一凸部較高於該等第二凸部，以及該等第二凸部呈一環形形狀，以圍繞該等第一凸部設置。
本揭露之另一實施例提供一種半導體封裝結構的製備方法。該方法包括：提供一第一基底，該第一基底具有一積體電路；形成多個隔離層的一第一堆疊在該積體電路上，該等隔離層的該第一堆疊具有多個第一凸部；移除該等隔離層之該第一堆疊的一最上面的隔離層；形成多個穿孔在該第一堆疊中，以形成一第一半導體結構；提供一第二基底，該第二基底具有一積體電路；形成多個隔離層的一第二堆疊在該積體電路上，該等隔離層的該第二堆疊具有多個第二凸部；形成一凹部在該第一堆疊中，以形成一第二半導體結構；以及接合該第一半導體結構與該第二半導體結構，且從該凹部形成一氣隙。
雖然已詳述本揭露及其優點，然而應理解可進行各種變化、取代與替代而不脫離申請專利範圍所定義之本揭露的精神與範圍。例如，可用不同的方法實施上述的許多製程，並且以其他製程或其組合替代上述的許多製程。
再者，本申請案的範圍並不受限於說明書中所述之製程、機械、製造、物質組成物、手段、方法與步驟之特定實施例。該技藝之技術人士可自本揭露的揭示內容理解可根據本揭露而使用與本文所述之對應實施例具有相同功能或是達到實質上相同結果之現存或是未來發展之製程、機械、製造、物質組成物、手段、方法、或步驟。據此，此等製程、機械、製造、物質組成物、手段、方法、或步驟係包含於本申請案之申請專利範圍內。
10:半導體結構 11:接合表面 100:基底 102:積體電路 104:內連接 106:隔離層 108:接合結構 108a:接合墊 108c:佈線結構 110:支撐結構 112:鈍化層 112a:鈍化層 20:半導體結構 21:接合表面 200:基底 202:積體電路 204:內連接 206a:隔離層 206b:隔離層 206c:隔離層 210:支撐結構 30:半導體封裝結構 300:基底 302:積體電路 304:內連接 306a:隔離層 306b:隔離層 306c:隔離層 308:接合結構 40:半導體結構 41:接合表面 50:半導體結構 51:接合表面 60:半導體封裝結構 AG:氣隙 AG’:氣隙 M30:方法 M60:方法 PR:遮罩圖案 RS:凹部 RS’:凹部 S11:步驟 S13:步驟 S15:步驟 S17:步驟 S19:步驟 S21:步驟 S23:步驟 S25:步驟 S31:步驟 S33:步驟 S35:步驟 S37:步驟 S39:步驟 S41:步驟 S43:步驟 S45:步驟 S47:步驟 S49:步驟 S51:步驟 T206a:厚度 T206b:厚度 T206c:厚度 T306a:厚度 T306b:厚度 T306c:厚度 T306c’:厚度 TH1:穿孔 TH2:穿孔 W:開口
參閱實施方式與申請專利範圍合併考量圖式時，可得以更全面了解本申請案之揭示內容，圖式中相同的元件符號係指相同的元件。 圖1為依據本揭露一些實施例中一種半導體結構之製備方法的流程示意圖。 圖2A到圖2I為依據本揭露一些實施例在如圖1所示的製造程序期間之各不同階段的剖視示意圖。 圖3為依據本揭露一些實施例中一種半導體結構之製備方法的流程示意圖。 圖4A到圖4K為依據本揭露一些實施例在如圖3所示的製造程序期間之各不同階段的剖視示意圖。
10:半導體結構
100:基底
102:積體電路
104:內連接
106:隔離層
108:接合結構
110:支撐結構
112a:鈍化層
20:半導體結構
30:半導體封裝結構
AG:氣隙
RS:凹部

Claims (20)

  1. 一種半導體封裝結構，包括： 一第一半導體結構，具有一第一表面以及一第一凹部，該第一凹部係從該第一表面凹陷，且該第一半導體結構包括多個第一導電結構，該等第一導電結構係從該第一凹部的一下表面凸伸；以及 一第二半導體結構，具有一第二表面以及多個第二凹部，該等第二凹部係從該第二表面凹陷，且該第二半導體結構包括多個第二導電結構，該等第二導電結構係從該第二表面凸伸，其中該第二半導體結構接合到該第一半導體結構上，該等第一導電結構插入到該等第二凹部，該等第二導電結構接觸該第一凹部的該下表面，該第二表面的一部分接觸該第一表面以密封該第一凹部，以便形成一氣隙在該半導體封裝結構中。
  2. 如請求項1所述之半導體封裝結構，其中該氣隙橫向地圍繞該等第一導電結構設置。
  3. 如請求項1所述之半導體封裝結構，其中該第一半導體結構還包括多個第一隔離層的一堆疊以及一隔離圖案，該隔離圖案位在該等第一隔離層的該堆疊上，該第一表面為該隔離圖案的一上表面，該隔離圖案呈一環形形狀，該隔離圖案的一內側壁為該第一凹部的一側壁，以及該第一凹部的該下表面為該等第一隔離層之該堆疊的一上表面。
  4. 如請求項3所述之半導體封裝結構，其中該氣隙具有一高度，大致等於該隔離圖案的一厚度。
  5. 如請求項3所述之半導體封裝結構，其中該第二半導體結構還包括多個第二隔離層的一堆疊，該第二表面為該等第二隔離層之該堆疊的一表面，以及該第二凹部延伸經過該等第二隔離層之該堆疊。
  6. 如請求項5所述之半導體封裝結構，其中該等第一導電結構從該等第一隔離層之該堆疊的該上表面凸伸的一第一厚度，大致等於該隔離圖案與該等第二隔離層之該堆疊的一總厚度。
  7. 如請求項5所述之半導體封裝結構，其中該等第二導電結構從該等第二隔離層之該堆疊凸伸的一第二厚度，大致等於該隔離圖案的一厚度。
  8. 如請求項1所述之半導體封裝結構，其中該等第一導電結構較高於該等第二導電結構，以及該第二導電結構呈一環形形狀，以圍繞該等第一導電結構設置。
  9. 一種半導體封裝結構，包括： 一第一半導體結構，具有一第一接合表面以及多個第一凸部，該等第一凸部從該第一接合表面凸伸；以及 一第二半導體結構，具有一第二接合表面以及多個第二凸部，該等第二凸部從該第二接合表面凸伸，該第二半導體結構接合到該第一半導體結構，其中該第一接合表面部分接觸該第二接合表面，哀第一接合表面的一部分與該第二接合表面的一部份分開設置，密封該第一接合表面的該部分與該第二接合表面的該部分之間的一間隔，並形成一氣隙在該半導體封裝結構中； 其中該氣隙橫向地圍繞該等第一凸部設置，該等第一凸部較高於該等第二凸部，以及該等第二凸部呈一環形形狀，以圍繞該等第一凸部設置。
  10. 如請求項9所述之半導體封裝結構，其中該第一接合表面具有一凹部，且該等第一凸部位在該凹部的範圍內。
  11. 如請求項12所述之半導體封裝結構，其中該等第二凸部接觸該第一接合表面的該凹部。
  12. 如請求項9所述之半導體封裝結構，其中該等第一凸部為多個導電栓塞，電性連接該第一半導體結構的一第一內連接以及該第二半導體結構的一第二內連接。
  13. 如請求項12所述之半導體封裝結構，其中該等第二凸部為多個導電栓塞，接觸該第二半導體的該第二內連接，並與該第一半導體的該第一內連接分開設置。
  14. 一種半導體封裝結構的製備方法，包括： 提供一第一基底，該第一基底具有一積體電路； 形成多個隔離層的一第一堆疊在該積體電路上，該等隔離層的該第一堆疊具有多個第一凸部； 移除該等隔離層之該第一堆疊的一最上面的隔離層； 形成多個穿孔在該第一堆疊中，以形成一第一半導體結構； 提供一第二基底，該第二基底具有一積體電路； 形成多個隔離層的一第二堆疊在該積體電路上，該等隔離層的該第二堆疊具有多個第二凸部； 形成一凹部在該第一堆疊中，以形成一第二半導體結構；以及 接合該第一半導體結構與該第二半導體結構，且從該凹部形成一氣隙。
  15. 如請求項14所述之半導體封裝結構的製備方法，其中該等第二凸部插入到該等穿孔中，以及該等第一凸部插入到該凹部中。
  16. 如請求項14所述之半導體封裝結構的製備方法，其中形成多個隔離層的一第二堆疊在該積體電路上，該等隔離層的該第二堆疊具有多個第二凸部的步驟包括： 形成多個第一穿孔在該等隔離層的該第一堆疊中； 充填該等第一穿孔，其係以導電材料進行充填；以及 移除該等隔離層之該第一堆疊的一上部。
  17. 如請求項14所述之半導體封裝結構的製備方法，其中形成多個隔離層的一第一堆疊在該積體電路上，該等隔離層的該第一堆疊具有多個第一凸部的步驟包括： 形成多個第二穿孔在該等隔離層的該第二堆疊中； 充填該等第二穿孔，其係以導電材料進行充填；以及 薄化該等隔離層之該第二堆疊的一上部； 其中該等氣隙的其中之一係位在其中一第一導電結構與其中一第二導電結構之間。
  18. 如請求項14所述之半導體封裝結構的製備方法，其中該氣隙橫向地圍繞該等第一凸部設置，以及該等第一凸部較高於該等第二凸部。
  19. 如請求項14所述之半導體封裝結構的製備方法，還包括執行紫外光固化製程，以移除多個懸浮鍵，其係在該第一半導體結構與該第二半導體結構接合之前執行。
  20. 如請求項14所述之半導體封裝結構的製備方法，還包括執行一快速熱氮化，以增濃一鈍化層。
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