TWI757140B - 具有氣隙的半導體封裝體及其製造方法 - Google Patents

具有氣隙的半導體封裝體及其製造方法 Download PDF

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TWI757140B
TWI757140B TW110112217A TW110112217A TWI757140B TW I757140 B TWI757140 B TW I757140B TW 110112217 A TW110112217 A TW 110112217A TW 110112217 A TW110112217 A TW 110112217A TW I757140 B TWI757140 B TW I757140B
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semiconductor
recesses
insulating layer
semiconductor package
semiconductor structure
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TW110112217A
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TW202143426A (zh
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黃則堯
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南亞科技股份有限公司
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Abstract

本揭露提供一種具有氣隙以降低導電構件之間的電容耦合的半導體封裝體及其製造方法。該半導體封裝體包括一第一半導體結構以及與該第一半導體結構接合的一第二半導體結構。該第一半導體結構具有一第一接合表面。該第二半導體結構具有一第二接合表面，其與該第一接合表面部分地接觸。該第一接合表面的一部分與該第二接合表面的一部分隔離。該第一和該第二接合表面的該些部分之間的一空間被密封並形成一氣隙於該半導體封裝體中。

Description

具有氣隙的半導體封裝體及其製造方法
本申請案主張2020年5月1日申請之美國正式申請案第16/864,767號的優先權及益處，該美國正式申請案之內容以全文引用之方式併入本文中。
本揭露係關於一種半導體封裝體及其製造方法。特別是關於一種具有氣隙以降低導電構件之間的電容耦合之半導體封裝體及其製造方法。
近年來，由於各種電子構件的積體密度不斷提高，半導體工業已歷經快速的成長。這些持續微縮化的電子構件需要比先前的封裝體佔據更小面積的較小封裝體。然而，在二維(2D)中可實現的半導體封裝體之微縮化存在著物理限制。雖然2D微縮化仍然是新設計的選擇之一，但採用利用z方向的三維(3D)封裝方案已成為業界研究的焦點。儘管如此，3D封裝技術仍存在待處理的挑戰。
上文之「先前技術」說明僅係提供背景技術，並未承認上文之「先前技術」說明揭示本揭露之標的，不組成本揭露之先前技術，且上文之「先前技術」之任何說明均不應做為本案之任一部分。
本揭露的一方面提供一種半導體封裝體。該半導體封裝體包括：一第一半導體結構，具有一第一表面和從該第一表面凹陷的複數個第一凹部；以及一第二半導體結構，具有一第二表面和從該第二表面凹陷的複數個第二凹部，其中該第一和第二半導體結構與彼此接合，該第一表面與該第二表面接觸，每一個該些第一凹部與該些第二凹部的其中之一彼此重疊並結合以形成密封於該半導體封裝體中的一氣隙。
在一些實施例中，該第一半導體結構包括複數個第一導電結構，其具有與該第一表面實質上共平面的表面，該第二半導體結構包括複數個第二導電結構，其具有與該第二表面實質上共平面的表面，且該些第一導電結構分別與該些第二導電結構接觸。
在一些實施例中，該些氣隙的其中之一位於相鄰的該些第一導電結構之間，且位於相鄰的該些第二導電結構之間。
在一些實施例中，該些第一凹部在形狀和尺寸上與該些第二凹部實質上相同。
在一些實施例中，該第一表面為一第一絕緣結構的一表面，該些第一凹部凹陷至該第一絕緣結構之中，該第二表面為一第二絕緣結構的一表面，且該些第二凹部凹陷至該第二絕緣結構之中。
在一些實施例中，該第一半導體結構包括複數個第一鈍化層共形地覆蓋該些第一凹部的表面，且該第二半導體結構包括複數個第二鈍化層共形地覆蓋該些第二凹部的表面。
在一些實施例中，該些氣隙分別被該些第一鈍化層的其中之一和該些第二鈍化層的其中之一包圍。
本揭露的另一方面提供一種半導體封裝體。該半導體封裝體包括：一第一半導體結構，具有一第一接合表面；一第二半導體結構，具有一第二接合表面，其與該第一半導體結構接合，其中該第一接合表面與該第二接合表面部分地接觸，該第一接合表面的一部分與該第二接合表面的一部分隔離，該第一和該第二接合表面的該些部分之間的一空間被密封並形成一氣隙於該半導體封裝體中。
在一些實施例中，該第一接合表面具有一第一凹陷部分，該第二接合表面具有一第二凹陷部分，該第一凹陷部分和該第二凹陷部分結合以形成該氣隙。
在一些實施例中，該第一凹陷部分與該第二凹陷部分在形狀和尺寸上與彼此實質上相同。
本揭露的又另一方面提供一種半導體封裝體的製造方法。該方法包括：提供具有一積體電路的一基板；形成具有接合結構和支撐結構的一第一絕緣層堆疊於該積體電路上；形成一罩幕圖案於該第一絕緣層堆疊上；移除該第一絕緣層堆疊的一些部分以形成複數個第一凹部於該第一絕緣層堆疊的一頂部區域中；形成一鈍化層共形地覆蓋該些第一凹部和該第一絕緣層堆疊的一頂表面；移除該鈍化層位於該第一絕緣層堆疊的該頂表面上方的部分，以形成一第一半導體結構；提供具有一第二絕緣層堆疊的一第二半導體結構，其中該第二絕緣層堆疊具有複數個第二凹部；以及接合該第一半導體結構與該第二半導體結構，該些第一凹部和該些第二凹部形成複數個氣隙。
在一些實施例中，該些第一凹部和該些第二凹部彼此重疊並結合以形成密封於該半導體封裝體中的該些氣隙。
在一些實施例中，該第一半導體結構包括複數個第一導電結構，其具有與該第一絕緣層堆疊的該頂表面實質上共平面的表面，該第二半導體結構包括複數個第二導電結構，其具有與該第二絕緣層堆疊的一頂表面實質上共平面的表面，且該些第一導電結構與該些第二導電結構接觸以形成用以傳遞訊號的一導線。
在一些實施例中，該些氣隙的其中之一位於相鄰的該些第一導電結構之間，且位於相鄰的該些第二導電結構之間。
在一些實施例中，該些第一凹部在形狀和尺寸上與該些第二凹部實質上相同。
在一些實施例中，該第二半導體結構包括一第二鈍化層共形地覆蓋該些第二凹部和該第二絕緣層堆疊的一頂表面。
在一些實施例中，該些氣隙分別被該第一鈍化層和該第二鈍化層包圍。
在一些實施例中，該些氣隙的其中之一位於該些第一導電結構的其中一者和該些第二導電結構的其中一者之間。
在一些實施例中，該半導體封裝體的製造方法更包括：在接合該第一半導體結構與該第二半導體結構之前，進行一紫外線(UV)固化製程以移除懸鍵(dangling bonds)。
在一些實施例中，該半導體封裝體的製造方法更包括：進行一快速熱氮化以緻密化該鈍化層。
綜上所述，根據本揭露實施例的半導體封裝體包括彼此接合的兩個半導體結構，且包括密封於半導體結構之間的界面處的氣隙。 一些氣隙位於用來在半導體結構之間建立電性連接的導電構件之間。由於空氣的低介電常數，故可透過在這些導電構件之間設置氣隙來減少它們之間的電容耦合。藉此，可降低導電構件的RC延遲。據此，可改善半導體結構之間的訊號傳遞。
上文已相當廣泛地概述本揭露之技術特徵及優點，俾使下文之本揭露詳細描述得以獲得較佳瞭解。組成本揭露之申請專利範圍標的之其它技術特徵及優點將描述於下文。本揭露所屬技術領域中具有通常知識者應瞭解，可相當容易地利用下文揭示之概念與特定實施例可做為修改或設計其它結構或製程而實現與本揭露相同之目的。本揭露所屬技術領域中具有通常知識者亦應瞭解，這類等效建構無法脫離後附之申請專利範圍所界定之本揭露的精神和範圍。
以下揭示提供許多不同的實施例或是例子來實行本揭露實施例之不同部件。以下描述具體的元件及其排列的例子以簡化本揭露實施例。當然這些僅是例子且不該以此限定本揭露實施例的範圍。例如，在描述中提及第一個部件形成於第二個部件“之上”或“上”時，其可能包括第一個部件與第二個部件直接接觸的實施例，也可能包括兩者之間有其他部件形成而沒有直接接觸的實施例。此外，本揭露可能在不同實施例中重複參照符號及/或標記。這些重複係為了簡化與清晰的目的，並非用以限定所討論的不同實施例及/或結構之間的關係。
此外，此處用到與空間相關的用詞，例如：“在…下方”、“下方”、“較低的”、“之上”、“較高的”、及其相似的用詞係為了便於描述圖式中所示的一個元件或部件與另一個元件或部件之間的關係。這些空間關係詞係用以涵蓋圖式所描繪的方位之外的使用中或操作中的元件之不同方位。裝置可能被轉向不同方位(旋轉90度或其他方位)，則其中使用的空間相關形容詞也可相同地照著解釋。
圖1是根據本揭露一些實施例顯示半導體結構的製造方法M30流程圖。圖2A到圖2I是顯示圖1所示製程期間各階段的中間結構之剖面示意圖。
參照圖1和圖2A，進行步驟S11，提供具有積體電路102的基板100。在一些實施例中，基板100為晶圓形式。在這些實施例中，基板100可為半導體晶片或絕緣體上半導體(semiconductor-on-insulator；SOI)晶片。例如，半導體晶片或SOI晶片中的半導體材料可包括元素半導體(例如：Si)、合金半導體(例如：SiGe)、化合物半導體(例如：第3-5族半導體、第2-6族半導體)、或前述之組合。此外，半導體材料可摻雜有第一導電類型(例如：N型)或與第一導電類型互補的第二導電類型(例如：P型)。在基板100為晶圓形式的那些實施例中，基板100可具有透過劃線區域(均未顯示)與彼此分離的晶粒區域，且積體電路102散佈在晶粒區域內。積體電路102可包括形成於基板100表面處的主動元件及/或被動元件(均未顯示)，且可包括位於主動元件及/或被動元件之上的內連線(也未顯示)。內連線被配置為內連接主動元件及/或被動元件，並且將主動元件及/或被動元件佈線到積體電路102的頂側。例如，主動元件可包括金氧半場效電晶體(metal-oxide-semiconductor field effect transistors；MOSFET)，而被動元件可包括電容器。此外，內連線可形成於一介電層堆疊中，且可包括分別延伸於該些介電層的其中一者之表面上的導電線路和垂直延伸並連接到至少一導電線路的導電通孔。應注意的是，在圖2A只顯示出內連線的最頂端部分，並將其標記為內連線104。此外，積體電路102的頂側可稱為最終形成的半導體結構(例如，如圖2F所示的半導體結構10)的主動側，而基板100的底側可稱為半導體結構的背側。
參照圖1和圖2B，進行步驟S13，形成絕緣層106堆疊(例如，兩層絕緣層106)以及接合結構108和支撐結構110於積體電路102上。接合結構108和支撐結構110穿過絕緣層106堆疊。應注意的是，只顯示出接合結構108的其中之一和支撐結構110的其中之一。接合結構108電性連接到內連線(亦即，內連線104)的最頂端部分，並且可用作積體電路102的輸入/輸出(I/O)。在一些實施例中，接合結構108分別包括接合墊108a和將接合墊108a連接到內連線(亦即，內連線104)的最頂端部分之佈線結構108b。接合墊108a可形成於最外層絕緣層106中，並具有與最外層絕緣層106的頂表面實質上共平面的一頂表面。佈線結構108b，像是導電通孔或導電柱，從接合墊108a的底端延伸到內連線(亦即，內連線104)的最頂端部分。另一方面，支撐結構110可形成為導電通孔或導電柱，並延伸穿過絕緣層106堆疊。在一些實施例中，支撐結構110可電性連接到內連線(即，內連線104)的最頂端部分。在這些實施例中，經連接的內連線104和支撐結構110可為電性浮動的，且被配置以增強最終形成的半導體結構(例如，如圖2I所示的半導體封裝體30)的機械強度。可選地，經連接的內連線104和支撐結構110可電性接地，且可用作積體電路102的電磁屏蔽。在其他實施例中，支撐結構110可不電性連接到任何內連線104，且可為電後浮動的或電性接地的。
此外，在一些實施例中，支撐結構110可彼此連接以形成壁(wall)，且該壁橫向地包圍接合結構108。在這些實施例中，壁可用作密封環。在替代實施例中，支撐結構110在橫向上與彼此分離，並且與接合結構108一起被密封環(未顯示)橫向地包圍。
絕緣層106的材料可包括無機絕緣材料(例如：氧化矽、氮化矽、氮氧化矽、其類似材料、或前述之組合)，而接合結構108和支撐結構110可由導電材料組成，像是金屬或金屬合金(例如：銅、銅合金、其類似材料、或前述之組合)。在一些實施例中，用於形成每一層絕緣層106的方法可包括沉積製程(例如：化學氣相沉積(chemical vapor deposition；CVD)製程)，而用於形成位於絕緣層106堆疊中的接合結構108和支撐結構110的方法可包括至少一個鑲嵌製程。然而，本技術領域具有通常知識者可選擇其他可行的材料及/或其他合適的形成方法來形成絕緣層106、接合結構108、和支撐結構110，本揭露不限於此。
在一些實施例中，接合結構108和支撐結構110中的導電材料透過障壁層(未顯示)與絕緣層106堆疊分離。障壁層的材料(在下文中稱為障壁材料)可包括Ti、TiN、Ta、TaN、其類似材料、或前述之組合。此外，用於形成障壁層的方法可包括沉積製程，像是物理氣相沉積(physical vapor deposition；PVD)製程或原子層沉積(atomic layer deposition；ALD)製程。
參照圖1和圖2C，進行步驟S15，並且形成罩幕圖案PR於絕緣層106堆疊上。罩幕圖案PR(像是光阻圖案)具有開口W，其定義在隨後的步驟期間要在該絕緣層106堆疊形成凹部的位置(例如：如圖2D所示的凹部RS)。每一個開口W與接合結構108和支撐結構110均橫向地間隔開。一些開口W分別位於接合結構108的其中一者和支撐結構110的其中一者之間，且位於相鄰的接合結構108之間或相鄰的支撐結構110之間。此外，一些其他的開口W可位於接合結構108和支撐結構110的分佈範圍之外。在那些罩幕圖案PR是光阻圖案的實施例中，用於形成罩幕圖案PR的方法可包括塗佈製程和微影製程。
參照圖1和圖2D，進行步驟S17，透過利用罩幕圖案PR作為陰影罩幕來移除絕緣層106堆疊的一些部分，以形成凹部RS於該絕緣層106堆疊的頂部區域中。在一些實施例中，透過像是非等向性蝕刻製程(anisotropic etching process)的蝕刻製程來移除絕緣層106堆疊與罩幕圖案PR的開口W重疊的部分以形成凹部RS。與罩幕圖案PR的開口W相同，每一個凹部RS分別與接合結構108和支撐結構110橫向地間隔開。一些凹部RS分別位於接合結構108的其中一者和支撐結構110的其中一者之間。此外，一些其他的凹部RS可位於接合結構108和支撐結構110的分佈範圍之外。在一些實施例中，將最外層絕緣層106與開口W重疊的部分移除，而位於最外層絕緣層106下方的絕緣層106則可實質上保持完整。在這些實施例中，在參照圖2B所述之步驟S13期間，蝕刻停止層(未顯示)可設置於兩個垂直地相鄰的絕緣層106之間，且對這些絕緣層106具有足夠的蝕刻選擇性。透過這種方式，在凹部W形成之後，可暴露出蝕刻停止層與開口W重疊的部分，並可定義凹部RS的底表面。可選地，可省略蝕刻停止層，且在蝕刻製程期間可移除或不移除位於最外層絕緣層106下方的絕緣層106。
參照圖1和圖2E，進行步驟S19，全面地(globally formed)形成鈍化層112。其結果，絕緣層106堆疊、接合結構108和支撐結構110的頂表面被鈍化層112覆蓋。在一些實施例中，鈍化層112共形地覆蓋下方的結構。在這些實施例中，凹部RS可不被鈍化層112填充，且鈍化層112在絕緣層106堆疊的頂部區域中相應於凹部RS凹陷。鈍化層112的材料可包括例如氮化矽。此外，用於形成鈍化層112的方法可包括沉積製程，像是原子層沉積(ALD)製程。然而，本技術領域具有通常知識者可選擇其他可行的絕緣材料及/或其他合適的形成方法來形成鈍化層112，本揭露不限於此。
參照圖1和圖2F，進行步驟S21，移除鈍化層112位於最外層絕緣層106的頂表面上方的部分。其結果，只留下凹部RS中部分的鈍化層112，並將其分別稱為鈍化層112a。此外，暴露出最外層絕緣層106的頂表面以及接合結構108和支撐結構110的頂表面。在一些實施例中，用於移除部分的鈍化層112之方法可包括一平坦化製程。例如，平坦化製程可包括化學機械研磨(chemical mechanical polishing；CMP)製程、蝕刻製程、或前述之組合。
在一些實施例中，鈍化層112a由氮化矽組成，並且在步驟S21之後進行快速熱氮化(rapid thermal nitridation；RTN)製程。透過進行RTN製程，可進一步緻密化鈍化層112中的氮化矽。在替代實施例中，鈍化層112a可由氧化矽組成，且氧化矽在經過RTN製程之後可變成氮氧化矽或氮化矽。此外，在一些實施例中，可進行紫外線(UV)固化製程以移除導電構件(例如，接合結構108、支撐結構110和積體電路102的內連線)中的懸鍵(dangling bonds)。在這些實施例中，UV固化製程可接在RTN製程之後，但本揭露不限於此。
至此，形成了半導體結構10。半導體結構10將與另一半導體結構(例如，如圖2G所示的半導體結構20)接合，而且最外層絕緣層106、鈍化層112a、接合結構108、和支撐結構110的暴露表面可共同定義半導體結構10的接合表面11。接合表面(例如，凹部RS中的鈍化層112a的表面)的至少一些部分可不與隨後接合的半導體結構(例如，如圖2G所示的半導體結構20)接觸。在一些實施例中，半導體結構10保持晶圓形式。在替代實施例中，可在圖2F所示的結構上進行單片化製程(singulation process)，使得可為單片結構之一的半導體結構10成為晶片形式。
參照圖1和圖2G，進行步驟S23，提供半導體結構20。在一些實施例中，透過參照圖2A到圖2F所述的方法來提供半導體結構20。為了避免重複描述，半導體結構10、20中的構件具有相同的標記。類似於半導體結構10，半導體結構20可保持晶圓形式。可選地，可進一步進行單片化製程，且可為單片結構之一的半導體結構20為晶片形式。半導體結構20將被接合到半導體結構10上，且最外層絕緣層106、鈍化層112a、接合結構108、和支撐結構110的暴露表面可共同定義半導體結構20的接合表面21。接合表面的至少一些部分(例如，凹部RS中的鈍化層112a的表面)可不參與半導體結構10、20的接合。
參照圖1和圖2H-2I，進行步驟S25，將半導體結構10、20彼此接合以形成半導體封裝體30。關於半導體結構10、20，其可分別為晶圓形式或晶片形式，而半導體封裝體30可為晶圓上晶圓(wafer-on-wafer)結構、晶圓上晶片(chip-on-wafer)結構、或晶片上晶片(chip-on-chip)結構。一旦半導體結構10、20接合在一起，半導體結構10、20的接合表面就與彼此部分地接觸。在一些實施例中，半導體結構10、20的最外層絕緣層106彼此接合，且半導體結構10的絕緣層106堆疊與半導體結構20的絕緣層106堆疊連接以形成結合的絕緣層106堆疊。此外，半導體結構10、20的接合結構108與彼此接合，並且在半導體結構10、20的積體電路102之間建立電性連接。此外，來自半導體結構10、20的支撐結構110彼此接合，並且可為電性浮動或電性接地的。另一方面，半導體結構10、20的凹部RS彼此對準，使得半導體結構10的鈍化層112a的垂直延伸部分與半導體結構20的鈍化層112a的垂直延伸部分接合。據此，可透過半導體結構10、20的鈍化層112a來密封凹部RS中的空腔，並形成氣隙AG於接合結構(亦即，半導體封裝體30)中。氣隙AG分別由彼此接合的兩個鈍化層112a包圍。接合結構108、支撐結構110、鈍化層112a、和氣隙AG位於結合的絕緣層106堆疊中。承自凹部RS的本質，一些氣隙AG位於接合結構108和支撐結構110的分佈範圍之內，而一些其他的氣隙AG位於接合結構108和支撐結構110的分佈範圍之外。
在一些實施例中，用於接合半導體結構10、20的方法包括透過例如拾取和放置(pick and place；PNP)製程將半導體結構10、20中的一個放置於另一個上，並進行混合接合製程以在半導體結構10、20之間建立物理接合。在一些實施例中，在真空氣氛或惰性氣氛中進行混合接合製程，以防止導電構件的氧化及/或濕氣侵入。混合接合製程可包括用於接合絕緣構件的第一加熱步驟和用於接合導電構件的第二加熱步驟。例如，絕緣部件可包括附接的絕緣層106和鈍化層112a，而導電構件可包括附接的接合結構108和支撐結構110。在一些實施例中，第一加熱步驟在第二加熱步驟之前。此外，在一些實施例中，第一加熱步驟的加熱溫度低於第二加熱步驟的加熱溫度。例如，第一加熱步驟的加熱溫度可以在150ºC至250ºC的範圍內，而第二加熱步驟的加熱溫度可以在180ºC至350ºC的範圍內。然而，本技術領域具有通常知識者可根據製程需求調整第一加熱步驟和第二加熱步驟的順序和加熱溫度，本揭露不限於此。
由於空氣的低介電常數(例如：大約1)，故可透過設置氣隙AG來減少橫向相鄰的接合結構108之間的電容耦合。類似地，接合結構108和支撐結構110之間的電容耦合可因氣隙AG而減少。因此，可降低接合結構108的電阻電容延遲(resistive-capacitive delay；RC延遲)。從而，可改善半導體結構10、20的積體電路102之間的訊號傳遞。
圖3是根據本揭露一些實施例顯示半導體結構的製造方法M60流程圖。圖4A到圖4K是顯示結構在圖3所示製程期間各階段的剖面示意圖。參照圖3和圖4A到圖4K描述的實施例和參照圖1和圖2A到圖2I描述的實施例相似，將只討論它們之間的差異而不再重複相同或相似的部分。此外，相似的標記代表相似或相同的構件(例如：基板100和基板200)。
參照圖3和圖4A，進行步驟S31，提供形成有積體電路202的基板200。應注意的是，只顯示出積體電路202中內連線的最頂端部分，並將其標記為內連線204。
隨後，進行步驟S33，形成絕緣層206a、206b、206c於積體電路202上。絕緣層206a位於絕緣層206b、206c的下方，且絕緣層206b夾在絕緣層206a、206c之間。絕緣層206a具有厚度T206a 、絕緣層206b具有厚度T206b 、且絕緣層206c具有厚度T206c 。在一些實施例中，厚度T206b 小於厚度T206a 和厚度T206c ，且厚度T206a 可大於、等於、或小於厚度T206c 。此外，在一些實施例中，絕緣層206b的材料不同於絕緣層206a、206c的材料。例如，絕緣層206b可由氮化矽組成，而絕緣層206a、206c可由氧化矽組成。用於形成每一層絕緣層206a、206b、206c的方法可包括沉積製程，像是化學氣相沈積(CVD)製程。然而，本技術領域具有通常知識者可調整絕緣層206a、206b、206c的厚度T206a 、T206b 、T206c ，並選擇其他合適的材料和形成絕緣層206a、206b、206c的形成方法，本揭露不限於此。
參照圖3和圖4B，進行步驟S35，形成穿孔TH1於絕緣層206a、206b、206c中。穿孔TH1穿過絕緣層206a、206、206c，並暴露出內連線(亦即，內連線204)的一些最頂端部份。在一些實施例中，暴露的內連線204位於靠近晶粒區域邊緣的位置(如參照圖2A所描述的)。用於形成穿孔TH1的方法可包括進行微影製程和一個或多個蝕刻製程(例如：非等向性蝕刻)。
參照圖3和圖4C，進行步驟S37，形成支撐結構210於穿孔TH1中。支撐結構210與先前暴露的內連線204接觸。連接的支撐結構210和內連線204為電性浮動或電性接地的。在一些實施例中，用於形成支撐結構210的方法包括透過沉積製程(例如：物理氣相沉積(PVD)製程)、鍍覆製程(例如：電鍍製程或無電鍍製程)、或前述之組合將導電材料填充到穿孔TH1中。此外，可進行平坦化製程以移除導電材料位於絕緣層206c的頂表面上方的部分。例如，導電材料可包括金屬或金屬合金(例如：銅、銅合金、其類似材料、或前述之組合)。此外，平坦化製程可包括例如：CMP製程、蝕刻製程、或前述之組合。
在一些實施例中，每一個支撐結構210更包括障壁層(未顯示)，其覆蓋每一個穿孔TH1中導電材料的側壁(或側壁及底表面)。障壁層(在下文中稱為障壁材料)的材料可包括Ti、TiN、Ta、TaN、其類似材料、或前述之組合。此外，用於形成障壁層的方法可包括透過像是物理氣相沈積(PVD)製程或原子層沉積(ALD)製程的沉積製程將障壁材料填充到穿孔TH1中。在一些實施例中，可透過用來移除導電材料位於絕緣層206c的頂表面上方的部分的平坦化製程來移除障壁材料位於絕緣層206c的頂表面上方的部分。
參照圖3和圖4D，進行步驟S39，移除絕緣層206c。隨著絕緣層206c的移除，暴露出絕緣層206b的頂表面和支撐結構210之側壁的上部份。此外，支撐結構210目前從絕緣層206b的頂表面突出的高度實質上等於絕緣層206c被移除的厚度(亦即，如圖4A所示的厚度T206c )。
參照圖3和圖4E，進行步驟S41，形成穿孔TH2於絕緣層206b、206a中。穿孔TH2穿過絕緣層206b、206a，並暴露出內連線(亦即，內連線204)先前被絕緣層206a覆蓋的一些最頂端部分。穿孔TH2被配置為在隨後的步驟中被另一半導體結構的導電構件插入(例如：如圖4J所示之半導體結構50的接合結構308)。在一些實施例中，用於形成穿孔TH2的方法包括微影製程和至少一蝕刻製程。
至此，已形成了半導體結構40。半導體結構40可保持晶圓形式。可選地，可進一步進行單片化製程，且可為單片結構之一的半導體結構40為晶片形式。在一些實施例中，可在以下步驟中將半導體結構40翻轉並接合到另一半導體結構(例如，如圖4J所示的半導體結構50)上。絕緣層206a、206b、內連線204、和支撐結構210的暴露表面共同定義半導體結構40的接合表面41。接合表面的至少一些部分可不和與半導體結構40接合的半導體結構接觸。
參照圖3和圖4F，進行步驟S43，形成絕緣層306a、306b、306c於形成有積體電路302的基板300上。基板300和積體電路302類似於參照圖2A和圖4A所述的基板100、200和積體電路102、202，只顯示出積體電路302中內連線的最頂端部份，並將其標記為內連線304。此外，絕緣層306a、306b、306c在材料和堆疊順序方面可類似於參照圖4A所描述的絕緣層206a、206b、206c(亦即，絕緣層306a、306b、306c依序堆疊於積體電路302上)。在一些實施例中，絕緣層306a、306b、306c的總厚度大於絕緣層206a、206b、206c的總厚度(如圖4A所示)。在這些實施例中，絕緣層306c的厚度T306c 可大於絕緣層206c的厚度T206c (如圖4A所示)。另一方面，絕緣層306b的厚度T306b 與絕緣層206b的厚度T206b (如圖4A所示)可實質上相同，且絕緣層306a的厚度T306a 與絕緣層206a的厚度T206a (如圖4A所示)可實質上相同。可選地，厚度T306c 、T306b 、T306a 可分別大於、等於、或小於厚度T206c 、T206b 、和T206a (如圖4A所示)，只要絕緣層306a、306b、306c的總厚度大於絕緣層206a、206b、206c的總厚度即可。
參照圖3和圖4G，進行步驟S45，形成接合結構308於絕緣層306a、306b、306c中。接合結構308穿過絕緣層306a、306b、306c，並與積體電路302中內連線(亦即，內連線304)的一些最頂端部分接觸。在一些實施例中，接合結構308被定位在對應於如圖4E所示之半導體結構40的穿孔TH2的位置，且接合結構308的寬度分別與每一個穿孔TH2的寬度實質上相同。在這樣的實施例中，可在以下步驟中將接合結構308插入並填充穿孔TH2(如圖4J所示)。與參照圖4C所述之支撐結構210類似，在一些實施例中，每一個接合結構308包括導電材料和覆蓋導電材料的側壁(或側壁及底表面)的障壁層。可選地，可省略障壁層。
參照圖3和圖4H，進行步驟S47，薄化絕緣層306c。其結果，接合結構308從薄化的絕緣層306c突出。在一些實施例中，將絕緣層306c薄化到厚度T306c ’，該厚度T306c ’實質上等於支撐結構210從絕緣層206b突出的高度(亦即，厚度T206c ，如參照圖4D所述)。在這些實施例中，在移除薄化的絕緣層306c的一部分(如將參照圖4I所述的)之後，如圖4E所示之支撐結構210和絕緣層206b可同時接合在絕緣層306b和絕緣層306c的剩餘部分上(如將參照圖4J所述的)。用於薄化絕緣層306c的方法可包括例如回蝕刻製程。
參照圖3和圖4I，進行步驟S49，移除絕緣層306c的一部分。形成由絕緣層306c的剩餘部分和絕緣層306b的暴露部分定義的凹部RS’。在一些實施例中，絕緣層306c被移除的部分先前包圍接合結構308，在將絕緣層306c的一部分移除之後，接合結構308的暴露部分之高度增加。接合結構308的暴露部分之高度實質上等於如圖4E所示之支撐結構210的高度，且接合結構308的埋藏部分之高度實質上等於絕緣層306a、306b的總厚度。這樣一來，當將半導體結構40的支撐結構210接合到絕緣層306b的暴露表面上時，接合結構308可插入穿孔TH1中並且剛好到達內連線204，如圖4J所示。另一方面，絕緣層306c的剩餘部分可與接合結構308橫向地間隔開。在一些實施例中，絕緣層306c的剩餘部分在橫向上包圍接合結構308，並且呈現為環形。用於移除一部分的絕緣層306c的方法可包括微影製程和蝕刻製程(例如：非等向性蝕刻)。
至此，已形成了半導體結構50。半導體結構50可保持晶圓形式。可選地，可進一步進行單片化製程，且可為單片結構之一的半導體結構50為晶片形式。如圖4J所示，半導體結構50與半導體結構40接合。絕緣層306c、絕緣層306b、和接合結構308的暴露表面可共同定義半導體結構50的接合表面51。半導體結構50的接合表面之至少一部分可不與半導體結構40的接合表面接觸，如以下步驟中所述。
參照圖3和圖4J至圖4K，進行步驟S51，將如圖4E所示之半導體結構40翻轉並接合到半導體結構50上。半導體結構40的一部分絕緣層206b接合到半導體結構50的絕緣層306c上，而半導體結構40的支撐結構210可接合到絕緣層306b的暴露表面上，並且可與絕緣層306c橫向地接觸或不接觸。此外，半導體結構50的接合結構308插入半導體結構40的穿孔TH2，且半導體結構50的接合結構308之頂表面和與穿孔TH2重疊的內連線204接觸。由於支撐結構210從絕緣層206b突出的的部分之高度實質上等於絕緣層306c的厚度，因此支撐結構210可剛好到達絕緣層306b的暴露表面。此外，由於接合結構308從絕緣層306b突出的高度實質上等於絕緣層306c、206b、206a的厚度之總和，所以接合結構308可剛好到達內連線204的先前暴露的表面。此外，由於在接合製程之前已經移除了半導體結構50之絕緣層306c的一部分(如參照圖4I所描述的)，所以半導體結構40的絕緣層206b可不完全與半導體結構50的絕緣層306c接觸。半導體結構40的絕緣層206b的一部分可不沿著垂直方向與半導體結構50接觸。半導體結構40的絕緣層206b和半導體結構50的絕緣層306b之間的空間可被絕緣層306c橫向地包圍，並且被密封在接合結構中以形成氣隙AG’。此外，氣隙AG’的區域可散佈在接合結構308和支撐結構210之間。
可將包括結合的半導體結構40、50之結構稱為半導體封裝體60。在一些實施例中，半導體封裝體60可進一步接受其他封裝製程及/或測試步驟。
如上所述，根據本揭露實施例的半導體封裝體包括彼此接合的兩個半導體結構，且包括密封於半導體結構之間的界面處的氣隙。 一些氣隙位於用來在半導體結構之間建立電性連接的導電構件之間。由於空氣的低介電常數，故可透過在這些導電構件之間設置氣隙來減少它們之間的電容耦合。藉此，可降低導電構件的RC延遲。據此，可改善半導體結構之間的訊號傳遞。
本揭露的一方面提供一種半導體封裝體。該半導體封裝體包括：一第一半導體結構，具有一第一表面和從該第一表面凹陷的複數個第一凹部；以及一第二半導體結構，具有一第二表面和從該第二表面凹陷的複數個第二凹部，其中該第一和第二半導體結構與彼此接合，該第一表面與該第二表面接觸，每一個該些第一凹部與該些第二凹部的其中之一彼此重疊並結合以形成密封於該半導體封裝體中的一氣隙。
本揭露的另一方面提供了一種半導體封裝體。該半導體封裝體包括：一第一半導體結構，具有一第一表面和從該第一表面凹陷的一第一凹部，並且包括從該第一凹部的一底表面突出的第一導電結構；以及一第二導電結構，具有一第二表面和從該第二表面凹陷的一第二凹部，並且包括從該第二表面突出的一第二導電結構，其中該第二半導體結構接合到該第一半導體結構上，該第一導電結構插入第二凹部中，該第二導電結構與該第一凹部的該底表面接觸，該第二表面的一部分與該第一表面接觸以密封該第一凹部，從而形成一氣隙於該半導體封裝體中。
本揭露的又另一方面提供一種半導體封裝體。該半導體封裝體包括：一第一半導體結構，具有一第一接合表面；一第二半導體結構，具有一第二接合表面，其與該第一半導體結構接合，其中該第一接合表面與該第二接合表面部分地接觸，該第一接合表面的一部分與該第二接合表面的一部分隔離，該第一和該第二接合表面的該些部分之間的一空間被密封並形成一氣隙於該半導體封裝體中。
雖然已詳述本揭露及其優點，然而應理解可進行各種變化、取代與替代而不脫離申請專利範圍所定義之本揭露的精神與範圍。例如，可用不同的方法實施上述的許多製程，且以其他製程或前述之組合替代上述的許多製程。
再者，本申請案的範圍並不受限於說明書中該之製程、機械、製造、物質組成物、手段、方法與步驟之特定實施例。該技藝之技術人士可自本揭露的揭示內容理解可根據本揭露而使用與本文該之對應實施例具有相同功能或是達到實質上相同結果之現存或是未來發展之製程、機械、製造、物質組成物、手段、方法、或步驟。據此，此等製程、機械、製造、物質組成物、手段、方法、或步驟係包含於本申請案之申請專利範圍內。
10:半導體結構 11:接合表面 20:半導體結構 21:接合表面 30:半導體封裝體 40:半導體結構 41:接合表面 50:半導體結構 51:接合表面 60:半導體封裝體 100:基板 102:積體電路 104:內連線 106:絕緣層 108:接合結構 108a:接合墊 108b:佈線結構 110:支撐結構 112:鈍化層 112a:鈍化層 200:基板 202:積體電路 204:內連線 206a:絕緣層 206b:絕緣層 206c:絕緣層 210:支撐結構 300:基板 302:積體電路 304:內連線 306a:絕緣層 306b:絕緣層 306c:絕緣層 308:接合結構 AG:氣隙 AG’:氣隙 M30:製造方法 M60:製造方法 PR:罩幕圖案 RS:凹部 RS’:凹部 S13:步驟 S15:步驟 S17:步驟 S19:步驟 S21:步驟 S23:步驟 S25:步驟 S31:步驟 S33:步驟 S35:步驟 S37:步驟 S39:步驟 S41:步驟 S43:步驟 S45:步驟 S47:步驟 S49:步驟 S51:步驟 T206a :厚度 T206b :厚度 T206c :厚度 T306a :厚度 T306b :厚度 T306c :厚度 T306c ’:厚度 TH1:穿孔 TH2:穿孔 W:開口
本揭露各方面可配合以下圖式及詳細說明閱讀以便了解。要強調的是，依照工業上的標準慣例，各個部件(feature)並未按照比例繪製。事實上，為了清楚之討論，可能任意的放大或縮小各個部件的尺寸。 圖1是根據本揭露一些實施例顯示半導體結構的製造方法流程圖。 圖2A到圖2I是顯示結構在圖1所示製程期間各階段的剖面示意圖。 圖3是根據本揭露一些實施例顯示半導體結構的製造方法流程圖。 圖4A到圖4K是顯示結構在圖3所示製程期間各階段的剖面示意圖。
10:半導體結構
20:半導體結構
30:半導體封裝體
100:基板
102:積體電路
104:內連線
106:絕緣層
108:接合結構
110:支撐結構
112a:鈍化層
AG:氣隙
RS:凹部

Claims (16)

  1. 一種半導體封裝體，包括：一第一半導體結構，具有一第一表面和從該第一表面凹陷的複數個第一凹部；以及一第二半導體結構，具有一第二表面和從該第二表面凹陷的複數個第二凹部，其中該第一和第二半導體結構與彼此接合，該第一表面與該第二表面接觸，每一個該些第一凹部的與該些第二凹部的其中之一彼此重疊並結合以形成密封於該半導體封裝體中的一氣隙；其中該第一半導體結構包括複數個第一導電結構，其具有與該第一表面實質上共平面的表面，該第二半導體結構包括複數個第二導電結構，其具有與該第二表面實質上共平面的表面，且該些第一導電結構分別與該些第二導電結構接觸。
  2. 如請求項1所述之半導體封裝體，其中該些氣隙的其中之一位於相鄰的該些第一導電結構之間，且位於相鄰的該些第二導電結構之間。
  3. 如請求項1所述之半導體封裝體，其中該些第一凹部在形狀和尺寸上與該些第二凹部實質上相同。
  4. 如請求項1所述之半導體封裝體，其中該第一表面為一第一絕緣結構的一表面，該些第一凹部凹陷至該第一絕緣結構之中，該第二表面為一第二絕緣結構的一表面，且該些第二凹部凹陷至該第二絕緣結構之中。
  5. 如請求項4所述之半導體封裝體，其中該第一半導體結構包括複數個第一鈍化層共形地覆蓋該些第一凹部的表面，且該第二半導體結構包括複數個第二鈍化層共形地覆蓋該些第二凹部的表面。
  6. 如請求項5所述之半導體封裝體，其中該些氣隙分別被該些第一鈍化層的其中之一和該些第二鈍化層的其中之一包圍。
  7. 一種半導體封裝體的製造方法，包括：提供具有一積體電路的一基板；形成具有接合結構和支撐結構的一第一絕緣層堆疊於該積體電路上；形成一罩幕圖案於該第一絕緣層堆疊上；移除一部分的該第一絕緣層堆疊以形成複數個第一凹部於該第一絕緣層堆疊的一頂部區域中；形成一鈍化層共形地覆蓋該些第一凹部和該第一絕緣層堆疊的一頂表面；移除該鈍化層位於該第一絕緣層堆疊的該頂表面上方的部分，以形成一第一半導體結構；提供具有一第二絕緣層堆疊的一第二半導體結構，其中該第二絕緣層堆疊具有複數個第二凹部；以及接合該第一半導體結構與該第二半導體結構，該些第一凹部和該些第二凹部形成複數個氣隙。
  8. 如請求項7所述之半導體封裝體的製造方法，其中該些第一凹部和該些第二凹部彼此重疊並結合以形成密封於該半導體封裝體中的該些氣隙。
  9. 如請求項8所述之半導體封裝體的製造方法，其中該第一半導體結構包括複數個第一導電結構，其具有與該第一絕緣層堆疊的該頂表面實質上共平面的表面，該第二半導體結構包括複數個第二導電結構，其具有與該第二絕緣層堆疊的一頂表面實質上共平面的表面，且該些第一導電結構與該些第二導電結構接觸以形成用以傳遞訊號的一導線。
  10. 如請求項9所述之半導體封裝體的製造方法，其中該些氣隙的其中之一位於相鄰的該些第一導電結構之間，且位於相鄰的該些第二導電結構之間。
  11. 如請求項8所述之半導體封裝體的製造方法，其中該些第一凹部在形狀和尺寸上與該些第二凹部實質上相同。
  12. 如請求項8所述之半導體封裝體的製造方法，其中該第二半導體結構包括一第二鈍化層共形地覆蓋該些第二凹部和該第二絕緣層堆疊的一頂表面。
  13. 如請求項12所述之半導體封裝體的製造方法，其中該些氣隙分別被該第一鈍化層和該第二鈍化層包圍。
  14. 如請求項12所述之半導體封裝體的製造方法，其中該些氣隙的其中之一位於該些第一導電結構的其中一者和該些第二導電結構的其中一者之間。
  15. 如請求項10所述之半導體封裝體的製造方法，更包括：在接合該第一半導體結構與該第二半導體結構之前，進行一紫外線(UV)固化製程以移除懸鍵。
  16. 如請求項10所述之半導體封裝體的製造方法，更包括：進行一快速熱氮化以緻密化該鈍化層。
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