TWI503906B - 半導體結構、半導體裝置及半導體裝置的製造方法 - Google Patents

半導體結構、半導體裝置及半導體裝置的製造方法 Download PDF

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TWI503906B
TWI503906B TW102129242A TW102129242A TWI503906B TW I503906 B TWI503906 B TW I503906B TW 102129242 A TW102129242 A TW 102129242A TW 102129242 A TW102129242 A TW 102129242A TW I503906 B TWI503906 B TW I503906B
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idle
plane
substrate
edge
layer
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TW201411752A (zh
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Yao Chun Chuang
Yu Chen Hsu
Hao Juin Liu
Chita Chuang
Chen Cheng Kuo
Chen Shien Chen
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Taiwan Semiconductor Mfg Co Ltd
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Description

半導體結構、半導體裝置及半導體裝置的製造方法
本發明係有關於一種半導體裝置及其製造方法。
因為各種電子元件(例如電晶體、二極體、電阻器、電容器等)的積集度不斷地改善，半導體工業已經歷快速的發展。大多數的情況下，積集度的改善是因為電子元件之最小特徵尺寸不斷地縮小，這容許更多的元件整合在有限的範圍。近來隨著更小的電子裝置的需求成長，較小且更創新的半導體晶粒之封裝技術的需求增加。
隨著半導體技術的發展，開發出三維(three-dimensional)積體電路裝置以作為縮小半導體晶片實體大小的有效選擇。在一個三維積體電路中，封裝係和各銅凸塊(bumps)所提供的接點(contacts)一起形成於晶粒上。藉由使用三維積體電路裝置能達成更高的密度。再者，三維積體電路可達到較小的形狀因素(form factor)、成本效益、提高效能與降低耗電力。
一個三維積體電路可包括頂主動電路層、底主動電路層、與多個中間層(inter-layer)。在一個三維積體電路中，兩個半導體晶粒可透過多個凸塊(bump)接合並透過多個貫孔 (through via)互相電性連接。凸塊與貫孔在提供三維積體電路的垂直內連線(interconnect)。如此一來，兩個半導體晶粒之間的訊號路徑短於傳統的三維積體電路裝置，其中在傳統的三維積體電路中係藉由內連線技術(例如，以導線接合(wire bonding)為基礎的晶片堆疊封裝)接合不同的半導體晶粒。一個三維積體電路裝置可包括各種半導體晶粒互相堆疊。多個半導體晶粒係在切割晶圓之前被封裝。
三維積體電路具有多種好處。在晶圓階段封裝多個半導體晶粒的一個有利特徵係在於多晶片晶圓及封裝技術可降低製造成本。另一個在晶圓階段封裝多個半導體晶粒的有利特徵係在於藉由使用凸塊與貫孔可減少寄生損耗(parasitic losses)。
本發明提供一種半導體結構，包括：多個連接器，形成於一第一半導體晶粒之一頂表面上；一第二半導體晶粒，形成於第一半導體晶粒上且透過些連接器與第一半導體晶粒相連；一第一閒置(dummy)導電平面，形成於第一半導體晶粒的一邊緣與些連接器之間，其中第一半導體晶粒之一邊緣與一第一中性點距離(Distance to Neutral Point,DNP)方向形成一第一角度，且其中第一角度小於或等於約45°。
本發明又提供一種半導體裝置，包括：一基底，其包括矽；一第一金屬層，形成於半導體之上；一第一介電層，形成於第一金屬層之上；一第二金屬層，形成於第一介電層之上；一第一鈍化保護層，形成於第二金屬層之上；一第二鈍化 保護層，形成於第一鈍化保護層之上；一接合墊，內埋於第一鈍化保護層與第二鈍化保護層中；一聚合物層，形成於第二鈍化保護層上；以及一連接器與一第一閒置平面，形成於聚合物層上方，其中：第一閒置平面係形成於基底的一邊緣與連接器之間，且其中第一半導體晶粒之一邊緣與一第一中性點距離方向形成一第一角度，且其中第一角度小於或等於約45°。
本發明亦提供一種半導體裝置的製造方法，包括：沉積一保護(protection)層於一第一基底上；形成一底凸塊金屬結構於保護層上；形成一連接器於底凸塊金屬結構上；形成一第一閒置平面於保護層上，其中第一閒置平面位於連接器與第一基底之一邊緣之間，且其中：第一半導體晶粒之一邊緣與一第一中性點距離方向形成一第一角度，且其中第一角度小於或等於約45°。
100、300、400‧‧‧三維積體電路
101‧‧‧第一半導體晶粒
102‧‧‧基底
104‧‧‧層間介電層
106‧‧‧底金屬化層
108‧‧‧頂金屬化層
110‧‧‧介電層
112‧‧‧第一鈍化保護層
114‧‧‧第二鈍化保護層
116‧‧‧接合墊
118‧‧‧聚合物層
120‧‧‧底凸塊金屬層
122、222、224、226‧‧‧連接器
124‧‧‧頂金屬連接器
128‧‧‧金屬線
150‧‧‧第二半導體晶粒
160‧‧‧底膠層
202、204、206、208‧‧‧角
210‧‧‧中心點
212、214、302、304、402‧‧‧閒置導電平面
218‧‧‧角度
216、232、234、236‧‧‧第一中性點距離方向
第1圖根據一實施例繪示出具有閒置(dummy)導電平面的三維積體電路之剖面示意圖；第2圖根據一實施例第1圖的第一半導體晶粒最上層表面的上視圖；第3圖根據另一實施例繪示出具有閒置導電平面的三維積體電路的剖面示意圖；第4圖根據又一實施例繪示出具有閒置導電平面的三維積體電路的剖面示意圖。
以下說明本發明實施例之製作與使用。然而，可輕易了解本發明實施例提供許多合適的發明概念而可實施於廣泛的各種特定背景。所揭示的特定實施例僅僅用於說明以特定方法製作及使用本發明，並非用以侷限本發明的範圍。
以下將對應到本發明實施例作特定背景的詳細敘述，其為三維積體電路的應力降低裝置。然而，本發明之實施例也可應用於各種半導體裝置。以下，將配合附圖對不同實施例作出詳細說明。
第1圖根據一實施例繪示出具有閒置(dummy)導電平面的三維積體電路之剖面示意圖。如第1圖所示，三維積體電路100包括第一半導體晶粒101與堆疊於第一半導體晶粒101之上的第二半導體晶粒150。第二半導體晶粒150可具有相似於第一半導體晶粒101的結構。為了簡單起見，第1圖僅繪示出第一半導體晶粒101的詳細結構以展示不同實施例的創新性。
第一半導體晶粒101包括基底102。基底102可由矽形成，然而其亦可由其他III族、IV族、及/或V族元素所形成，例如，矽、鍺、鎵、砷、或前述之組合。基底102也可為矽覆絕緣體(silicon-on-insulator,SOI)的形式。SOI基底可包括一層半導體材料(例如，矽、鍺等)形成於一絕緣層(例如，埋入氧化物(buried oxide)等)上，絕緣層形成於矽基底中。此外，其他可被使用的基底包括多層(multi-layered)基底、梯度(gradient)基底、混成定向(hybrid orientation)基底等。
基底102可進一步包括各種電子電路(未顯示)。形 成於基底102上的電子電路可為適用於特定應用的任何電路。
根據一實施例，電子電路可包括不同的n型金屬氧化物半導體(n-type metal-oxide semiconductor,NMOS)及/或p型金屬氧化物半導體(p-type metal-oxide semiconductor,PMOS)裝置，例如，電晶體、電容器、電阻器、二極體、光二極體、熔絲等。電子電路可互連以呈現一或多種功能。功能可包括記憶體(memory)結構、處理(processing)結構、感測器、擴大器、電力分佈、輸入/輸出電路等。
任何所屬技術領域中具有通常知識者可理解上文的範例僅是提供說明之用，以進一步闡明本發明之應用而並非用於限定本發明之範圍。
在基底102之上形成層間介電層(interlayer dielectric layer,IDL)104。舉例來說，層間介電層104可由低介電常數材料(例如，氧化矽)所形成。層間介電層104可由任何合適的習知方法所形成，例如，旋塗(spinning)、化學氣相沉積(chemical vapor deposition,CVD)、與電漿增強化學氣相沉積(plasma enhanced chemical vapor deposition,PECVD)。應注意的是，任何所屬技術領域中具有通常知識者將理解層間介電層104可進一步包括多個介電層。
在層間介電層104上形成底金屬化(metallization)層106與頂金屬化層108。如第1圖所示，底金屬化層106可包括第一金屬線126。同樣的，頂金屬化層108包括第二金屬線128。金屬線126、128係由金屬材料所形成，例如，銅或銅合金等金屬材料。可由合適的製程(例如，沉積、鑲嵌等)形成 成底金屬化層106與頂金屬化層108。一般而言，層間金屬介電(inter-metal dielectric)層與其相關的金屬化層係用來使基底102中的電子電路互連，以形成功能性電路並進一步提供外部電路連接。
應注意的是，雖然第1圖僅顯示底金屬化層106與頂金屬化層108，任何所屬技術領域中具有通常知識者將理解到在成底金屬化層106與頂金屬化層108之間形成有一或多個層間金屬介電(inter-metal dielectric,IMD)層(未顯示)與相關的金屬層(未顯示)。具體來說，形成於底金屬化層106與頂金屬化層108之間的多個層可藉由交替多個介電層(例如，極低介電常數(extremely low-k,ELK)材料)與導電材料(例如，銅)的方式形成。
在頂金屬化層108之上形成介電層110。如第1圖所示，頂金屬連接器124內埋於介電層110中。具體而言，頂金屬連接器在金屬線128與半導體裝置的電性連接結構之間提供導電通道。頂金屬連接器124可由金屬材料形成，例如，銅、銅合金、銀、金、或前述任一組合。可藉由合適的製程形成頂金屬連接器124，例如，CVD。此外，可由濺鍍、電鍍(electroplating)等製程形成頂金屬連接器124。
在介電層110之上形成第一鈍化保護(passivation)層112。根據一實施例，第一鈍化保護層112係由無機材料形成，例如，未摻雜(un-doped)矽玻璃、氮化矽、氧化矽等。除此之外，可使用極低介電常數材料形成第一鈍化保護層112，例如，多孔碳摻雜二氧化矽。可透過任何合適的製程形成第一 鈍化保護層112，例如CVD。如第1圖所示，可在第一鈍化保護層112中形成開口。開口係為了容納接合墊116，以下將對接合墊116作詳述。
在第一鈍化保護層112之上形成第二鈍化保護層114。第二鈍化保護層114相似於第一鈍化保護層112，故在此不再詳述以避免不必要的重複。如第1圖所示，在第一與第二鈍化保護層的開口中形成接合墊116。接合墊116可由金屬材料形成，例如，銅、銅合金、銀、金、前述任一組合、及/或前述之複合層。接合墊116可由任何合適的製程形成，例如，CVD。除此之外，可由濺鍍、電鍍等製程形成接合墊116。
接合墊116可被第一與第二鈍化保護層112、114包圍。具體而言，接合墊116的底部部份內埋於第一鈍化保護層112中而接合墊116的頂部部分內埋於第二鈍化保護層114中。第一與第二鈍化保護層112、114相互重疊且將接合墊116的邊緣密封以藉由防止接合墊116的邊緣遭侵蝕並改善電性穩定度。再者，鈍化保護層有助於降低半導體裝置的漏電流。
在第二鈍化保護層114之上形成聚合物層118。可由聚合物材料製作聚合物層118，例如，環氧聚合物(epoxy)、聚亞醯氨(polyimide)、聚苯噁唑(polybenzoxazole,PBO)、苯並環丁烯(benzocyclobutene,BCB)、及/或塑型(molding)化合物等。根據不同實施例，聚合物118層可由PBO形成。為了簡單起見，在整個說明書中，聚合物層118又可稱為PI層118。聚合物層118可由任何合適的習知沉積法形成，例如，旋轉塗佈等。
若接合墊116重置(relocate)於新的位置，可在三維積體電路100中形成重分佈(redistribute)層。重分佈層在金屬線(例如，金屬線128)與重分佈的接合墊之間提供導電路徑。重分佈層的運作原理在此技藝是眾所皆知的，故在此不詳述。
圖案化PI層118以形成多個開口。再者，在開口之上形成多種底凸塊金屬(under bump metal,UBM)結構(例如，UBM120)。使用UBM結構(例如，UBM120)以連接接合墊(例如，接合墊116)與各種輸入及輸出端子(例如，連接器122)。可使用任何合適的製程形成UBM結構，例如電鍍。可依據期望的(desired)材料而使用其他製程，例如濺鍍(sputtering)、蒸鍍(evaporation)、PECVD等。
如第1圖所示，在PI層118之上可形成有多個閒置(dummy)導電平面140。閒置導電平面140置於UBM結構120與第一半導體晶粒101的邊緣之間。根據一實施例，閒置導電平面140可由銅形成。閒置導電平面140的形狀與位置將對應到第2圖在以下作詳述。
連接器122形成於UBM結構120之上。根據一實施例，連接器可為焊球(solder ball)。焊球122可由任何合適的材料形成。根據一實施例，焊球122可包括SAC405。SAC405包括95%的錫、4.0%的銀與0.5%的銅。
根據一實施例，連接器122可為銅凸塊。銅凸塊之高度可為約45nm。根據一實施例，可使用各種半導體封裝技術形成銅凸塊，例如濺鍍、電鍍、或光微影 (photolithography)。如此領域中所知的，為了確保銅凸塊與接合墊116之間可靠的附著力與電連續性(electrical continuity)，可在銅凸塊與接合墊116之間形成額外的層，額外的層包括阻障(barrier)層、黏著(adhesion)層、與晶種(seed)層。應注意的是，第1圖中的連接器僅是範例。本發明適用於各種半導體連接器。
底膠(underfill)材料層160可形成於第一半導體晶粒101之頂表面與第二半導體晶粒之間的空隙中。根據一實施例，底膠材料層160可為環氧聚合物(epoxy)，其分配(dispense)於第一半導體晶粒101之頂表面與第二半導體晶粒之間的空隙中。環氧聚合物可以液體的型態塗敷，且經過硬化製程(curing process)後被硬化。
根據另一實施例，底膠材料層160可由可硬化型(curable)材料形成，例如，聚合物材料、樹脂材料、聚亞醯氨環氧聚合物(polyimide epoxy)、或前述任一組合等。可由旋轉式塗佈(spin-on coating)製程、或乾膜層疊(dry film lamination)製程等形成底膠材料層160。底膠材料(例如，底膠材料層160)的一個有利的特徵係在於底膠材料層160有助於防止三維積體電路100在可靠度測試(例如，熱循環(thermal cycling)製程)期間破裂。再者，底膠材料層160的另一個有利的特徵係在於其有助於降低三維積體電路100在製造過程中的機械應力與熱應力。
第2圖根據一實施例第1圖的第一半導體晶粒最上層表面的上視圖。如第2圖所示，第一半導體晶粒101之頂 表面可包括四個角(corners)，即角202、204、206與208。可在四個角之間設置多個連接器(例如，連接器222、224與226)。考慮到製作的機械強度與設計，連接器(例如，連接器222)可視情況地不設置相鄰於第一半導體晶粒101的邊緣。除此之外，可在連接器(例如，連接器222、224與226)與第一半導體晶粒101的邊緣之間設置多個閒置導電平面(例如，閒置導電平面212與214)。
第一半導體晶粒101頂表面的中心點稱為中心點210。從第一半導體晶粒101上表面的左上角(例如，角202)到第一半導體晶粒101之中心點210的方向係定義為第一中性點距離(Distance to Neutral Point,DNP)方向216。
同樣地，如第2圖所示，從第一半導體晶粒101上表面的左下角(例如，角206)到第一半導體晶粒101之中心點210的方向係定義為第二DNP方向232。從第一半導體晶粒101上表面的右下角(例如，角208)到第一半導體晶粒101之中心點210的方向係定義為第三DNP方向234。從第一半導體晶粒101上表面的右上角(例如，角204)到第一半導體晶粒101之中心點210的方向係定義為第四DNP方向236。
根據一實施例，為了降低連接器(例如，連接器222)的相鄰區域之應力，閒置導電平面(例如，閒置導電平面214)的形狀與位置受限於以下限制。那就是，一DNP方向與其相鄰的閒置導電平面之外邊緣可形成一小於或等於45°的角度。舉例來說，可有兩個閒置導電平面212與214於左上角202中。閒置導電平面214之外邊緣與第一DNP方向216形成角度 218。根據一實施例，角度218可約等於45°。除此之外，角度218可小於45°。
在具有傳統閒置導電平面的半導體裝置中，介於閒置導電平面與其對應的DNP方向之間的角度(例如90°)會在熱循環或其他可靠度測試期間擴大相鄰於閒置導電平面的連接器周圍之應力。具體而言，熱循環期間的膨脹(expansion)效應可造成各種應力，其包括伸張(tensile)應力及/或壓縮(compressive)應力等。這樣的應力，特別是相鄰於半導體裝置的角落(corners)的應力，會在半導體裝置的角落之上的底膠層中造成各種裂痕。裂痕會延伸過底膠層並進一步引發基底上與基底中的裂痕。
第2圖所示的角度之一個有利特徵係在於閒置導電平面與DNP方向之間的角度要求有助於降低應力以便防止角落(corner)發生裂痕。
第3圖根據另一實施例繪示出具有閒置導電平面的三維積體電路的剖面示意圖。三維積體電路300相似於第1圖所示的三維積體電路100，除了可以多個閒置導電平面(例如，閒置導電平面302與304)替代第1圖中的閒置導電平面140。如第3圖所示，可在相鄰於第一半導體晶粒101之邊緣處設置兩個閒置導電平面。各個閒置導電平面(例如，閒置導電平面302)之長度可為約20~500um。應注意的是，雖然第3圖顯示兩個閒置導電平面，三維積體電路300可容納任何數量的閒置平面。
第4圖根據又一實施例繪示出具有閒置導電平面 的三維積體電路的剖面示意圖。三維積體電路400相似於第1圖所示的三維積體電路100，除了在第二半導體晶粒150之右邊緣與閒置導電平面402之間可有排除區域(keep-out zone,KOZ)。如第4圖所示，閒置導電平面402與第二半導體晶粒150的右邊緣之間的排除區域被定義為D。根據一實施例，D大於50um。
雖然本發明已以較佳實施例揭露如上，然其並非用以限定本發明，任何所屬技術領域中具有通常知識者，在不脫離本發明之精神和範圍內，當可作更動、替代與潤飾。舉例來說，任何所屬技術領域中具有通常知識者可輕易理解此處所述的許多特徵、功能、製程及材料可在本發明的範圍內作更動。
再者，本發明之保護範圍並未侷限於說明書內所述特定實施例中的製程、機器、製造、物質組成、裝置、方法及步驟，任何所屬技術領域中具有通常知識者可從本發明揭示內容中理解現行或未來所發展出的製程、機器、製造、物質組成、裝置、方法及步驟，只要可以在此處所述實施例中實施大體相同功能或獲得大體相同結果皆可使用於本發明中。因此，本發明之保護範圍包括前述製程、機器、製造、物質組成、裝置、方法及步驟。另外，每一申請專利範圍構成個別的實施例，且本發明之保護範圍也包括各個申請專利範圍及實施例的組合。
100‧‧‧三維積體電路
101‧‧‧第一半導體晶粒
102‧‧‧基底
104‧‧‧層間介電層
106‧‧‧底金屬化層
108‧‧‧頂金屬化層
110‧‧‧介電層
112‧‧‧第一鈍化保護層
114‧‧‧第二鈍化保護層
116‧‧‧接合墊
118‧‧‧聚合物層
120‧‧‧底凸塊金屬層
122‧‧‧連接器
124‧‧‧頂金屬連接器
126、128‧‧‧金屬線
140‧‧‧閒置導電平面
150‧‧‧第二半導體晶粒
160‧‧‧底膠層

Claims (10)

  1. 一種半導體結構，包括：多個連接器，形成於一第一半導體晶粒之一頂表面上；一第二半導體晶粒，形成於該第一半導體晶粒上且透過該些連接器與該第一半導體晶粒相連；以及一第一閒置(dummy)導電平面，形成於該第一半導體晶粒的一邊緣與該些連接器之間，其中該第一閒置導電平面之一外邊緣與該第一半導體晶粒之一外邊緣垂直地對齊，其中該第一閒置導電平面之一邊緣與一第一中性點距離(Distance to Neutral Point,DNP)方向形成一第一角度，且其中該第一角度小於或等於約45°。
  2. 如申請專利範圍第1項所述之半導體結構，其中該第一閒置導電平面係由銅所形成，且其中該第一閒置導電平面之一邊緣與該第二半導體晶粒之一邊緣以一水平距離隔開，且該水平距離大於50um。
  3. 如申請專利範圍第1項所述之半導體結構，更包括：一第二閒置導電平面，形成於該第一閒置導電平面與該第一半導體晶粒之該邊緣之間，且其中：該第一閒置導電平面之寬度為約20~500um；以及該第二閒置導電平面之寬度為約20~500um。
  4. 一種半導體裝置，包括：一基底，其包括矽；一第一金屬層，形成於該半導體之上；一第二金屬層，形成於該第一金屬層之上； 一第一鈍化保護層，形成於該第二金屬層之上；一第二鈍化保護層，形成於該第一鈍化保護層之上；一接合墊，內埋於該第一鈍化保護層與該第二鈍化保護層中；一聚合物層，形成於該第二鈍化保護層上；以及一連接器與一第一閒置平面，形成於該聚合物層上方，其中：該第一閒置平面係形成於該基底的一邊緣與該連接器之間，其中該第一閒置平面之一外邊緣與該第一半導體晶粒之一外邊緣垂直地對齊，且其中該第一閒置平面之一邊緣與一第一中性點距離方向形成一第一角度，且其中該第一角度小於或等於約45°。
  5. 如申請專利範圍第4項所述之半導體裝置，更包括一第二半導體晶粒，形成於該基底上方且透過該連接器與該基底連接。
  6. 如申請專利範圍第5項所述之半導體裝置，更包括一底膠層，形成於該基底之一頂表面與該第二半導體晶粒之間，其中該連接器與該第一閒置平面內埋於該底膠層中。
  7. 一種半導體裝置的製造方法，包括：沉積一保護(protection)層於一第一基底上；形成一底凸塊金屬結構於該保護層上；形成一連接器於該底凸塊金屬結構上；以及形成一第一閒置平面於該保護層上，其中該第一閒置平面位於該連接器與該第一基底之一邊緣之間，其中該第一閒 置平面之一外邊緣與該第一半導體晶粒之一外邊緣垂直地對齊，且其中：該第一閒置平面之一邊緣與一第一中性點距離方向形成一第一角度，且其中該第一角度小於或等於約45°。
  8. 如申請專利範圍第7項所述之半導體裝置的製造方法，更包括：形成一第二閒置平面相鄰於該第一閒置平面，其中該第一閒置平面與該第二閒置平面在該第一基底之一角落處具有一共通節點(node)，且其中該第一閒置平面之一第一邊緣與該第二閒置平面之一第二邊緣形成約等於90°的角度。
  9. 如申請專利範圍第7項所述之半導體裝置的製造方法，更包括：形成一第三閒置平面，其中該第三閒置平面位於該第一閒置平面與該基底之該邊緣之間，且其中：該第三閒置平面之寬度為約20~500um。
  10. 如申請專利範圍第7項所述之半導體裝置的製造方法，更包括：透過一回焊(reflow)製程固定一第二基底於該第一基底，其中該第二基底透過該連接器連接至該第一基底，且其中：該第一閒置平面以大於50um的一水平距離從該第二基底隔開。
TW102129242A 2012-09-12 2013-08-15 半導體結構、半導體裝置及半導體裝置的製造方法 TWI503906B (zh)

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