CN103681587A - 应力降低装置 - Google Patents

应力降低装置 Download PDF

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CN103681587A
CN103681587A CN201310004946.0A CN201310004946A CN103681587A CN 103681587 A CN103681587 A CN 103681587A CN 201310004946 A CN201310004946 A CN 201310004946A CN 103681587 A CN103681587 A CN 103681587A
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substrate
layer
pseudo
edge
plane
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CN103681587B (zh
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庄曜群
徐语晨
刘浩君
庄其达
郭正铮
陈承先
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Abstract

应力降低装置。一种结构包括：在第一半导体管芯的顶面上形成的多个连接件；在第一半导体管芯上形成并且通过多个连接件连接到第一半导体管芯的第二半导体管芯；以及在第一半导体管芯的边缘和多个连接件之间形成的第一伪导电平面，其中第一伪导电平面的边缘和第一距中性点距离(DNP)方向形成第一角度，其中第一角度小于或者等于45度。

Description

应力降低装置
技术领域
本发明涉及三维集成电路器件，更具体而言，涉及应力降低装置。
背景技术
由于各种电子部件(例如，晶体管、二极管、电阻器、电容器等)的集成密度不断得到提高，半导体产业经历了快速的发展。在极大程度上，集成密度的这种改进归因于最小部件尺寸的不断减小，这使得更多的部件被集成到给定区域中。近来随着对更小电子器件的需求的增长，对一种更小且更具创新性的半导体管芯封装技术的需要也在增长。
随着半导体技术的发展，三维集成电路器件作为有效的替代品应运而生以进一步减小半导体芯片的物理尺寸。在三维集成电路中，在具有通过各种凸块提供的接触件的管芯上形成封装。通过利用三维集成电路器件可以实现更高的密度。而且，三维集成电路器件可以实现更小的形状因数、成本高效益、增强的性能以及更低的功耗。
三维集成电路器件可以包括顶部有源电路层、底部有源电路层和多个中间层。在三维集成电路中，两个半导体管芯可以通过多个凸块接合到一起，并且通过多个通孔彼此电连接。凸块和通孔在三维集成电路的纵轴上提供电互连。因此，两个半导体管芯之间的信号通路短于传统的三维集成电路器件中的信号通路，在传统的三维集成电路器件中使用诸如基于引线接合的芯片堆叠封装件的互连技术将不同的半导体管芯接合到一起。三维集成电路器件可以包括堆叠在一起的各种半导体管芯。在切割晶圆之前封装多个半导体管芯。
三维集成电路技术具有许多优点。在晶圆级封装多个半导体管芯的一个有利的特征是多芯片晶圆级封装技术可以降低制造成本。基于晶圆级封装件的多芯片半导体器件的另一有利特征是通过使用凸块和通孔减小了寄生损失。
发明内容
为了解决现有技术中存在的问题，根据本发明的一方面，提供了一种结构，包括：多个连接件，形成在第一半导体管芯的顶面上；第二半导体管芯，形成在所述第一半导体管芯上并且通过所述多个连接件与所述第一半导体管芯连接；以及第一伪导电平面，形成在所述第一半导体管芯的边缘和所述多个连接件之间，其中所述第一伪导电平面的边缘与第一距中性点距离(DNP)方向形成第一角度，其中所述第一角度小于或者等于约45度。
在所述的结构中，所述多个连接件由焊料形成。
在所述的结构中，所述多个连接件由铜形成。
在所述的结构中，所述第一伪导电平面由铜形成。
在所述的结构中，所述第一伪导电平面的边缘与所述第二半导体管芯的边缘分开水平距离，其中所述水平距离大于50μm。
所述的结构还包括：第二伪导电平面，形成在所述第一伪导电平面和所述第一半导体管芯的边缘之间。
所述的结构还包括：第二伪导电平面，形成在所述第一伪导电平面和所述第一半导体管芯的边缘之间，其中，所述第一伪导电平面具有约20μm至约500μm的第一宽度；以及所述第二伪导电平面具有约20μm至约500μm的第二宽度。
根据本发明的另一方面，提供了一种器件，包括：衬底，包含硅；第一金属层，形成在所述衬底上方；第一介电层，形成在所述第一金属层上；第二金属层，形成在所述第一介电层上；第一钝化层，形成在所述第二金属层上方；第二钝化层，形成在所述第一钝化层上方；接合焊盘，嵌入所述第一钝化层和所述第二钝化层中；聚合物层，形成在所述第二钝化层上；以及连接件和第一伪平面，形成在所述聚合物层上方，其中：所述第一伪平面形成在所述衬底的边缘和所述连接件之间，并且所述第一伪平面的边缘与第一距中性点距离(DNP)方向形成第一角度，其中所述第一角度小于或者等于约45度。
所述的器件还包括：在所述衬底上方形成并且通过所述连接件与所述衬底连接的第二半导体管芯。
所述的器件还包括：在所述衬底上方形成并且通过所述连接件与所述衬底连接的第二半导体管芯；以及在所述衬底的顶面和所述第二半导体管芯之间形成的底部填充层，其中所述连接件和所述第一伪平面嵌入所述底部填充层中。
所述的器件还包括：在所述衬底上方形成并且通过所述连接件与所述衬底连接的第二半导体管芯；以及在所述衬底的顶面和所述第二半导体管芯之间形成的底部填充层，其中所述连接件和所述第一伪平面嵌入所述底部填充层中，其中，所述底部填充层由环氧树脂形成。
在所述的器件中，所述聚合物层包含聚酰亚胺。
在所述的器件中，所述接合焊盘包含铝。
所述的器件还包括：在所述接合焊盘上方形成的凸块下金属化结构。
根据本发明的又一方面，提供了一种方法，包括：在第一衬底上方沉积保护层；在所述保护层上方形成凸块下金属化结构；在所述凸块下金属化结构上方形成连接件；以及在所述保护层上方形成第一伪平面，其中所述第一伪平面位于所述连接件和所述第一衬底的边缘之间，并且其中：所述第一伪平面的边缘与第一距中性点距离(DNP)方向形成第一角度，其中所述第一角度小于或者等于约45度。
所述的方法还包括：邻近所述第一伪平面形成第二伪平面，其中所述第一伪平面和所述第二伪平面在所述第一衬底的角部具有共同节点，并且所述第一伪平面的第一边缘和所述第二伪平面的第二边缘形成约等于90度的角。
所述的方法还包括：形成第三伪平面，其中所述第三伪平面位于所述第一伪平面和所述第一衬底的边缘之间。
所述的方法还包括：形成第三伪平面，其中所述第三伪平面位于所述第一伪平面和所述第一衬底的边缘之间，其中，所述第三伪平面的宽度为约20μm至约500μm。
所述的方法还包括：通过回流工艺将第二衬底接合在所述第一衬底上，其中通过所述连接件将所述第二衬底连接至所述第一衬底。
所述的方法还包括：通过回流工艺将第二衬底接合在所述第一衬底上，其中通过所述连接件将所述第二衬底连接至所述第一衬底，其中，所述第一伪平面与所述第二衬底分开大于50μm的水平距离。
附图说明
为了更充分地理解本发明及其优点，现在将参考结合附图所进行的以下描述，其中：
图1示出根据实施例的具有伪导电平面的三维集成电路的截面图；
图2示出根据实施例的图1所示的第一半导体管芯的最上表面的俯视图；
图3示出根据另一实施例的具有伪导电平面的三维集成电路的截面图；以及
图4示出根据又一实施例的具有伪导电平面的三维集成电路的截面图。
除非另有说明，不同附图中的相应标号和符号通常是指相应的部件。绘制附图绘制用于清楚地示出各种实施例的相关方面而不必按比例绘制。
具体实施方式
在下面详细讨论本发明实施例的制造和使用。然而，应该理解，本发明提供了许多可以在各种具体环境中实现的可应用的发明构思。所讨论的具体实施例仅仅是制造和使用本发明的示例性具体方式，而不用于限制本发明的范围。
将就具体环境中的实施例描述本发明，即一种三维集成电路的应力降低装置。然而，本发明还可以适用于各种半导体器件。在下文中，将参考附图详细阐述各种实施例。
图1示出根据实施例的具有伪导电平面的三维集成电路的截面图。如图1所示，三维集成电路100包括第一半导体管芯101以及堆叠在第一半导体管芯101的顶部上的第二半导体管芯150。第二半导体管芯150可以具有类似于第一半导体管芯101的结构。为简明起见，图1中仅示出第一半导体管芯101的详细结构以便示出各种实施例的创新方面。
第一半导体管芯101包括衬底102。衬底102可以由硅形成，但其还可以由其他的III族、IV族和/或V族元素诸如硅、锗、镓、砷和它们的组合形成。衬底102还可以是绝缘体上硅(SOT)的形式。SOI衬底可以包括在绝缘层(例如，埋氧层等)上方形成的半导体材料(例如，硅和/或锗等)层，该绝缘层形成在硅衬底中。此外，可以使用的其他衬底包括多层衬底、梯度衬底和/或混合取向衬底等。
衬底102还可以包括各种电路(未示出)。在衬底102上形成的电路可以是适合于具体应用的任何类型的电路。
根据实施例，电路可以包括诸如晶体管、电容器、电阻器、二极管、光电二极管、熔丝等各种n型金属氧化物半导体(NMOS)和/或p型金属氧化物半导体(PMOS)器件。可以将电路互连起来以执行一种或多种功能。这些功能可以包括存储器结构、处理结构、传感器、放大器、功率分配器、输入/输出电路等。
本领域普通技术人员将认识到，仅出于举例说明的目的，提供以上实例以进一步阐述本发明的应用，并不意味着以任何方式限制本发明。
层间介电层104形成在衬底102的顶部上。层间介电层104可以例如由诸如氧化硅的低K介电材料形成。层间介电层104可以通过本领域中已知的任何合适的方法诸如旋涂、化学汽相沉积(CVD)和等离子体增强化学汽相沉积(PECVD)形成。还应该注意，本领域技术人员将认识到层间介电层104还可以包括多个介电层。
底部金属化层106和顶部金属化层108形成在层间介电层104的上方。如图1所示，底部金属化层106包括第一金属线126。同样地，顶部金属化层108包括第二金属线128。金属线126和128由诸如铜或铜合金等金属材料形成。金属化层106和108可以通过任何合适的技术(例如沉积、镶嵌等)形成。通常，一个或多个金属间介电层和相关的金属化层用于将衬底102中的电路彼此互连起来以形成功能电路以及进一步提供外部电连接。
应该注意，虽然图1示出底部金属化层106和顶部金属化层108，但是本领域技术人员将认识到，可以在底部金属化层106和顶部金属化层108之间形成一个或多个金属间介电层(未示出)和相关的金属化层(未示出)。具体来说，底部金属化层106和顶部金属化层108之间的层可以由交替的电介质(例如，极低k介电材料)层和导电材料(例如，铜)层形成。
介电层110形成在顶部金属化层108的顶部上。如图1所示，顶部金属连接件124嵌入介电层110中。具体来说，顶部金属连接件在金属线128和半导体器件的电连接结构之间提供导电沟道。顶部金属连接件124可以由诸如铜、铜合金、铝、银、金的金属材料和它们的任何组合形成。顶部金属连接件124可以通过诸如CVD的合适的技术形成。可选地，顶部金属连接件124可以通过溅射、电镀等形成。
第一钝化层112形成在介电层110的顶部上。根据实施例，第一钝化层112由诸如未掺杂的硅酸盐玻璃、氮化硅、氧化硅等非有机材料形成。可选地，第一钝化层112可以由诸如碳掺杂的氧化物等低k电介质形成。此外，可以使用诸如多孔碳掺杂的二氧化硅的极低k(ELK)电介质形成第一钝化层112。第一钝化层112可以通过诸如CVD的任何合适的技术形成。如图1所示，可以在第一钝化层112中形成开口。开口用于容纳接合焊盘116，将在下文对其进行详细论述。
第二钝化层114形成在第一钝化层112的顶部上。第二钝化层114可以类似于第一钝化层112，因此为避免不必要的重复在此不再详细论述。如图1所示，接合焊盘116形成在第一钝化层和第二钝化层的开口中。接合焊盘116可以由诸如铜、铜合金、铝、银、金的金属材料以及它们的任何组合和/或它们的多层形成。接合焊盘116可以通过诸如CVD的合适的技术形成。可选地，接合焊盘116可以通过溅射和/或电镀等形成。
接合焊盘116可以被第一钝化层112和第二钝化层114包围。具体来说，接合焊盘116的底部嵌入第一钝化层112中并且接合焊盘116的顶部嵌入第二钝化层114中。第一钝化层112和第二钝化层114与接合焊盘116的边缘重叠并且密封接合焊盘116的边缘从而通过阻止接合焊盘116的边缘受到腐蚀来提高电稳定性。此外，钝化层可以有助于降低半导体器件的漏电流。
聚合物层118形成在第二钝化层114的顶部上。聚合物层118可以由诸如环氧树脂、聚酰亚胺、聚苯并恶唑(PBO)、硅酮、苯并环丁烯(BCB)和/或模塑料等聚合物材料形成。根据各种实施例，聚合物层118可以由PBO形成。为简明起见，在整个说明书中，聚合物层118可以被可选地称为PI层118。聚合物层118可以通过本领域已知的诸如旋涂和/或其他等合适的沉积方法形成。
如果将接合焊盘116重新设置在新的位置，则可以在三维集成电路100中形成再分配层(未示出)。再分配层提供金属线(例如，金属线128)和再分配接合焊盘之间的导电路径。由于再分配层的操作原理是本领域中公知的，因此在此不再详细论述。
图案化PI层118以形成多个开口。而且，在开口的顶部上形成各种凸块下金属(UBM)结构(例如，UBM 120)。使用UBM结构(例如，UBM120)将接合焊盘(例如，接合焊盘116)与各种输入和输出端子(例如，连接件122)连接起来。可以通过诸如电镀的任何合适的技术形成UBM结构。取决于所需的材料，可以可选地使用诸如溅射、蒸发、PECVD等其他形成工艺。
如图1所示，在PI层118的顶部上可以形成多个伪导电平面140。伪导电平面140设置在UBM结构120和第一半导体管芯101的边缘之间。根据实施例，伪导电平面140可以由铜形成。下文将参照图2详细描述伪导电平面140的形状和位置。
连接件122形成在UBM结构120的顶部上。根据实施例，连接件122可以是焊料球。焊料球122可以由任何合适的材料形成。根据实施例，焊料球122可以包含SAC405。SAC405包含95.5％的Sn、4.0％的Ag和0.5％的Cu。
根据实施例，连接件122可以是铜凸块。铜凸块的高度可以为约45nm。根据实施例，可以使用诸如溅射、电镀和光刻的各种半导体封装技术来形成铜凸块。如本领域已知的，为了确保铜凸块和接合焊盘116之间具有可靠的粘附和电气连接，可以在铜凸块和接合焊盘116之间形成另外的层，包括阻挡层、粘附层和晶种层。应该注意，图1示出的连接件仅是实例。本发明适用于各种半导体连接件。
底部填充材料层160可以形成在第一半导体管芯101的顶面和第二半导体管芯150之间的间隙中。根据实施例，底部填充材料160可以是环氧树脂，其分散在第一半导体管芯101的顶面和第二半导体管芯150之间的间隙中。环氧树脂可以以液体形式施用，然后在固化工艺之后可以变硬。
根据另一实施例，底部填充材料层160可以由诸如基于聚合物的材料、基于树脂的材料、聚酰亚胺、环氧树脂和它们的任何组合的可固化材料形成。可以通过旋涂工艺、干膜层压工艺和/或其他等形成底部填充材料层160。具有底部填充材料(例如，底部填充材料160)的一个有利特征是底部填充材料160有助于防止三维集成电路100在诸如热循环工艺的可靠性测试期间碎裂。此外，另一有利特征是底部填充材料160可以帮助在制造三维集成电路100的工艺期间降低机械应力和热应力。
图2示出根据实施例的图1所示的第一半导体管芯的最上表面的俯视图。如图2所示，第一半导体管芯101的顶面可以包括四个角部，也就是角部202、204、206和208。在四个角部之间可以设置多个连接件(例如，连接件222、224和226)。考虑到制造的机械强度和设计，可以不将连接件(例如，连接件222)设置成邻近第一半导体管芯101的边缘。而是，可以在连接件(例如，连接件222、224和226)和第一半导体管芯101的边缘之间设置多个伪铜平面(例如，伪铜平面212和214)。
第一半导体管芯101的顶面的中心点被称为中心点210。第一距中性点距离(DNP)方向216被定义为从第一半导体管芯101的顶面的左上角部(例如，角部202)到第一半导体管芯101的中心点210的方向。
同样地，如图2所示，第二DNP方向232被定义为从第一半导体管芯101的顶面的左下角部(例如，角部206)到第一半导体管芯101的中心点210的方向。第三DNP方向234被定义为从第一半导体管芯101的顶面的右下角部(例如，角部208)到第一半导体管芯101的中心点210的方向。第四DNP方向236被定义为从第一半导体管芯101的顶面的右上角部(例如，角部204)到第一半导体管芯101的中心点210的方向。
根据实施例，为了降低邻近连接件(例如，连接件222)的区域的应力，伪导电平面(例如，伪导电平面214)的形状和位置受到以下限制。也就是，DNP方向与其邻近的伪导电平面的外侧边缘可以形成小于或等于45度的角。例如，在左上角部202中有两个伪导电平面212和214。伪导电平面214的外侧边缘与第一DNP方向216形成角218。根据实施例，角218可以约等于45度。可选地，角218可以小于45度。
在具有传统伪导电平面的半导体器件中，伪导电平面的外侧边缘与其相应的DNP方向之间的角(例如，90度)在热循环或其他可靠性测试期间可以增大围绕邻近于伪导电平面的连接件的应力。具体来说，热循环期间的热膨胀效应可能引起各种应力，包括拉伸应力、压缩应力和/或其他等。这些应力，尤其是邻近半导体器件的角部的应力，可能引起半导体器件角部上方的底部填充层出现各种角裂。这些角裂可能延伸穿过底部填充层并且进一步在衬底上和衬底中引起碎裂。
具有图2所示的角的一个有利特征是伪导电平面和DNP方向之间的角度要求有助于降低应力从而阻止角裂的发生。
图3示出根据另一实施例的具有伪导电平面的三维集成电路的截面图。三维集成电路300类似于图1所示的三维集成电路100，除了图1示出的伪导电平面140被替换成多个伪导电平面(例如，伪导电平面302和304)。如图3所示，可以邻近第一半导体管芯101的边缘设置两个伪导电平面。每个伪导电平面(例如，伪导电平面302)的长度可以介于约20μm至约500μm的范围内。应该注意，虽然图3示出两个伪导电平面，但是三维集成电路300可以容纳任意数量的伪平面。
图4示出根据又一实施例的具有伪导电平面的三维集成电路的截面图。三维集成电路400类似于图1所示的三维集成电路100，除了在伪导电平面402和第二半导体管芯150的右侧边缘之间可以具有排除区域(keep-out region)。如图4所示，伪导电平面402和第二半导体管芯150的右侧边缘之间的排除区域被定义为D。根据实施例，D大于50μm。
尽管已经详细地描述了本发明实施例及其优势，但应该理解，可以在不背离所附权利要求限定的本发明的精神和范围的情况下，进行各种改变、替换和更改。
而且，本申请的范围预期并不限于本说明书中描述的工艺、机器、制造、材料组分、装置、方法和步骤的特定实施例。作为本领域普通技术人员根据本发明应很容易理解，根据本发明可以利用现有的或今后开发的用于执行与本文所述相应实施例基本上相同的功能或者获得基本上相同的结果的工艺、机器、制造、材料组分、装置、方法或步骤。因此，所附权利要求预期在其范围内包括这样的工艺、机器、制造、材料组分、装置、方法或步骤。

Claims (10)

1.一种结构，包括：
多个连接件，形成在第一半导体管芯的顶面上；
第二半导体管芯，形成在所述第一半导体管芯上并且通过所述多个连接件与所述第一半导体管芯连接；以及
第一伪导电平面，形成在所述第一半导体管芯的边缘和所述多个连接件之间，其中所述第一伪导电平面的边缘与第一距中性点距离(DNP)方向形成第一角度，其中所述第一角度小于或者等于约45度。
2.根据权利要求1所述的结构，其中，所述多个连接件由焊料或铜形成。
3.根据权利要求1所述的结构，其中，所述第一伪导电平面由铜形成。
4.根据权利要求1所述的结构，其中，所述第一伪导电平面的边缘与所述第二半导体管芯的边缘分开水平距离，其中所述水平距离大于50μm。
5.根据权利要求1所述的结构，还包括：
第二伪导电平面，形成在所述第一伪导电平面和所述第一半导体管芯的边缘之间。
6.根据权利要求5所述的结构，其中，
所述第一伪导电平面具有约20μm至约500μm的第一宽度；以及
所述第二伪导电平面具有约20μm至约500μm的第二宽度。
7.一种器件，包括：
衬底，包含硅；
第一金属层，形成在所述衬底上方；
第一介电层，形成在所述第一金属层上；
第二金属层，形成在所述第一介电层上；
第一钝化层，形成在所述第二金属层上方；
第二钝化层，形成在所述第一钝化层上方；
接合焊盘，嵌入所述第一钝化层和所述第二钝化层中；
聚合物层，形成在所述第二钝化层上；以及
连接件和第一伪平面，形成在所述聚合物层上方，其中：
所述第一伪平面形成在所述衬底的边缘和所述连接件之间，并且
所述第一伪平面的边缘与第一距中性点距离(DNP)方向形成第一角度，其中所述第一角度小于或者等于约45度。
8.一种方法，包括：
在第一衬底上方沉积保护层；
在所述保护层上方形成凸块下金属化结构；
在所述凸块下金属化结构上方形成连接件；以及
在所述保护层上方形成第一伪平面，其中所述第一伪平面位于所述连接件和所述第一衬底的边缘之间，并且其中：
所述第一伪平面的边缘与第一距中性点距离(DNP)方向形成第一角度，其中所述第一角度小于或者等于约45度。
9.根据权利要求8所述的方法，还包括：
邻近所述第一伪平面形成第二伪平面，其中所述第一伪平面和所述第二伪平面在所述第一衬底的角部具有共同节点，并且所述第一伪平面的第一边缘和所述第二伪平面的第二边缘形成约等于90度的角。
10.根据权利要求8所述的方法，还包括：
通过回流工艺将第二衬底接合在所述第一衬底上，其中通过所述连接件将所述第二衬底连接至所述第一衬底。
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