CN102376679A - 封装基板以及包括该封装基板的倒装芯片封装 - Google Patents

封装基板以及包括该封装基板的倒装芯片封装 Download PDF

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CN102376679A
CN102376679A CN2011102439005A CN201110243900A CN102376679A CN 102376679 A CN102376679 A CN 102376679A CN 2011102439005 A CN2011102439005 A CN 2011102439005A CN 201110243900 A CN201110243900 A CN 201110243900A CN 102376679 A CN102376679 A CN 102376679A
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semiconductor chip
pattern
function
stress
projection
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CN2011102439005A
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CN102376679B (zh
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李钟周
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Samsung Electronics Co Ltd
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Samsung Electronics Co Ltd
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Abstract

本发明提供了封装基板以及包括该封装基板的倒装芯片封装。该封装基板包括绝缘基板、功能图案和主虚设图案。半导体芯片布置在绝缘基板上。功能图案形成在绝缘基板上。功能图案电连接到半导体芯片。主虚设图案沿着应力的路径形成在绝缘基板的在功能图案外面和/或邻近功能图案的部分上，该应力由绝缘基板与半导体芯片的热膨胀系数之间的差异产生，从而将应力从功能图案移走。因此，应力不是集中在功能图案上。从而，防止了由应力引起对功能凸块的损伤。

Description

封装基板以及包括该封装基板的倒装芯片封装
技术领域
示例实施例涉及一种封装基板以及包括该封装基板的倒装芯片封装。更具体地，示例实施例涉及通过导电凸块电连接到半导体芯片的封装基板以及包括该封装基板的倒装芯片封装。
背景技术
可以在半导体基板上进行多个半导体制造工艺以形成多个半导体芯片。为了将半导体芯片安装在印刷电路板(PCB)上，可以在半导体芯片上进行封装工艺以形成半导体封装。
半导体封装可以包括配置为将半导体芯片与封装基板电连接的电连接构件。电连接构件可以包括导电引线和/或导电凸块。
包括导电凸块的半导体封装被称作倒装芯片封装，该导电凸块配置为将封装基板与半导体芯片电连接。
在倒装芯片封装中，半导体芯片与封装基板的热膨胀系数之间的差异可能较大。因此，可能由于在倒装芯片封装的操作期间产生的高热量导致相对大的应力施加到封装基板。应力会损坏导电凸块，使得封装基板与半导体芯片之间的电连接可能被切断。
发明内容
示例实施例提供具有能够减少施加到封装基板的应力的结构的封装基板。
示例实施例还提供包括该封装基板的倒装芯片封装。
根据一些示例实施例，提供一种封装基板。该封装基板包括绝缘基板、功能图案和主虚设图案。半导体芯片布置在绝缘基板上。功能图案形成在绝缘基板上。功能图案电连接到半导体芯片。主虚设图案沿着应力的路径形成在绝缘基板的在功能图案外面和/或邻近功能图案的部分上，该应力由绝缘基板与半导体芯片的热膨胀系数之间的差异产生，从而将应力从功能图案移走。
在一些示例实施例中，主虚设图案可以基本垂直于应力的前进方向。此外，主虚设图案可以具有大于功能图案的面积。
在一些示例实施例中，封装基板还可以包括围绕和/或邻近功能图案的辅助虚设图案。辅助虚设图案可以基本垂直于应力的前进方向。辅助虚设图案可以具有大于功能图案的面积。
在一些示例实施例中，功能图案可以基本平行于应力的前进方向。
根据一些示例实施例，提供一种倒装芯片封装。该倒装芯片封装包括半导体芯片、封装基板、功能凸块和主虚设凸块。封装基板包括绝缘基板、功能图案和主虚设图案。半导体芯片布置在绝缘基板上。功能图案形成在绝缘基板上。功能图案电连接到半导体芯片。主虚设图案形成在绝缘基板的在功能图案外面和/或邻近功能图案的部分上。功能凸块安装在功能图案上以将功能图案与半导体芯片电连接。主虚设凸块安装在主虚设图案上。主虚设凸块沿着由绝缘基板和半导体芯片的热膨胀系数之间的差异产生的应力的路径定位于功能凸块的外面和/或邻近功能凸块，从而将应力从功能图案移走。
在一些示例实施例中，主虚设凸块可以具有大于功能图案的尺寸。浮置焊盘可以插置在主虚设凸块和半导体芯片之间。
在一些示例实施例中，封装基板还可以包括围绕和/或邻近功能图案的辅助虚设图案。辅助虚设凸块可以安装在辅助虚设图案上。辅助虚设凸块可以具有大于功能凸块的尺寸。浮置焊盘可以插置在辅助虚设凸块和半导体芯片之间。
在一些示例实施例中，倒装芯片封装还可以包括形成在封装基板上的模制构件以覆盖半导体芯片。
在一些示例实施例中，倒装芯片封装还可以包括安装在封装基板的下表面上的外部端子。
根据一些示例实施例，提供一种倒装芯片封装。该倒装芯片封装包括第一半导体芯片、第二半导体芯片、封装基板、功能凸块和主虚设凸块。封装基板包括绝缘基板、功能图案和主虚设图案。功能图案形成在绝缘基板上。主虚设图案形成在绝缘基板的在功能图案的外面和/或邻近功能图案的部分上。第一半导体芯片安装在封装基板上。插塞穿过第一半导体芯片形成。功能凸块插置在插塞和功能图案之间以将功能图案与第一半导体芯片电连接。主虚设凸块安装在主虚设图案上。主虚设凸块沿着由绝缘基板和第一半导体芯片的热膨胀系数之间的差异产生的应力的路径定位于功能凸块的外面和/或邻近功能凸块，从而将应力从功能图案移走。
在一些示例实施例中，第一半导体芯片可以具有面朝下的结构，其中有源区域可以布置为面对封装基板。
在一些示例实施例中，第一半导体芯片可以具有面朝上的结构，其中有源区域可以布置为远离封装基板。
在一些示例实施例中，插塞可以位于第一半导体芯片的不与第二半导体芯片接触的边缘部分。
在一些示例实施例中，插塞可以位于第一半导体芯片的与第二半导体芯片接触的中央部分。
根据一些示例实施例，提供一种封装基板，该封装基板包括：绝缘基板，其上布置半导体芯片；功能图案，形成在绝缘基板上，其中功能图案电连接到半导体芯片；以及主虚设图案，形成在绝缘基板的在功能图案外面和/或邻近功能图案的部分上。主虚设图案关于绝缘基板上的应力方向不同于功能图案取向，该应力由绝缘基板和半导体芯片的热膨胀系数的差异产生。
根据一些示例实施例，提供一种制造封装基板的方法，该方法包括：将半导体芯片布置在绝缘基板上；在绝缘基板上形成功能图案，其中功能图案电连接到半导体芯片；以及在绝缘基板的在功能图案外面和/或邻近功能图案的部分上形成主虚设图案，其中主虚设图案沿着绝缘基板上的应力路径取向，该应力由绝缘基板和半导体芯片的热膨胀系数的差异产生。
根据一些示例实施例，应力集中在布置在功能图案外面和/或邻近功能图案布置的主虚设图案上。因此，应力没有集中在功能图案上。结果，可以防止由应力引起的对功能凸块的损伤。
附图说明
从以下结合附图的详细描述，示例实施例将被更清楚地理解。图1至图10表示如这里所述的非限制性的示例实施例。
图1是示出根据一些示例实施例的封装基板的平面图；
图2是图1中的部分“II”的放大平面图；
图3是示出根据一些示例实施例的封装基板的平面图；
图4是图3中的部分“IV”的放大平面图；
图5是示出根据一些示例实施例的倒装芯片封装的截面图；
图6是图5中的部分“VI”的放大截面图；
图7是示出根据一些示例实施例的倒装芯片封装的截面图；
图8是示出根据一些示例实施例的倒装芯片封装的截面图；
图9是示出根据一些示例实施例的倒装芯片封装的截面图；以及
图10是示出根据一些示例实施例的倒装芯片封装的截面图；
具体实施方式
在下文将参照附图更全面地描述各个示例实施例，附图中示出了一些示例实施例。然而，本发明构思可以以许多不同的形式实施，而不应被解释为限于这里阐述的示例实施例。在附图中，为清晰起见，层和区域的尺寸及相对尺寸可以被夸大。
应当理解，当称一元件或层在另一元件或层“上”、“连接到”或“耦接到”另一元件或层时，它可以直接在另一元件或层上、直接连接到或耦接到另一元件或层，或者可以存在插入的元件或层。相似的附图标记会始终指代相似的元件。
图1是示出根据一些示例实施例的封装基板的平面图，图2是图1中的部分“II”的放大平面图。
参照图1和图2，封装基板100包括绝缘基板110、功能图案120、主虚设图案130和辅助虚设图案132。
在一些示例实施例中，绝缘基板110具有矩形形状。绝缘基板110支撑半导体芯片。半导体芯片布置在绝缘基板110的上表面上。特别地，根据实施例，半导体芯片布置在绝缘基板110的上表面的中央部分上。
在一些示例实施例中，绝缘基板110包括绝缘材料，诸如氧化物。半导体芯片包括硅。由于氧化物和硅的热膨胀系数之间的差异大，所以绝缘基板110和半导体芯片的热膨胀系数之间的差异也大。当绝缘基板110的上表面上的半导体芯片工作时，高的热量施加到半导体芯片和绝缘基板110。因此，应力沿图1中的箭头施加到绝缘基板110。也就是，绝缘基板110在箭头的方向上膨胀。
功能图案120布置在绝缘基板110的上表面上。功能凸块(未示出)安装在功能图案120上。因此，半导体芯片经由功能凸块电连接到功能图案120。在一些示例实施例中，功能图案120布置在绝缘基板110的上表面的中央部分和边缘部分上。在绝缘基板110的上表面的中央部分上的功能图案120接收来自半导体芯片的信号。在绝缘基板110的上表面的边缘部分上的功能图案120用于供电、接地等。
在一些示例实施例中，功能图案120彼此平行。特别地，功能图案120平行于绝缘基板110的侧面。
主虚设图案130布置在绝缘基板110的上表面的边缘部分上。主虚设凸块(未示出)安装在主虚设图案130上。主虚设凸块减轻施加到绝缘基板110的至少一些应力。例如，应力集中在主虚设凸块上，使得主虚设凸块减轻施加到功能凸块的应力。
应力沿应力的前进方向(也就是，如箭头所示的绝缘基板110的膨胀方向)逐渐增加。为了有效减轻施加到功能图案120的应力，主虚设图案130布置在功能图案120的外面和/或邻近功能图案120使得应力的前进方向经过主虚设图案130。主虚设图案130中的至少一些比功能图案120定位得更靠近绝缘基板110的侧面。
此外，为了有效减轻施加到功能图案120的应力，主虚设图案130具有应力集中在其上的形状。在一些示例实施例中，主虚设图案130基本垂直于应力的前进方向布置。也就是，主虚设图案130具有基本垂直于应力的前进方向的长度方向。基本垂直于应力的前进方向的主虚设图案130阻碍了应力的前进。因此，应力集中在主虚设图案130上。结果，应力集中在主虚设图案130上的虚设凸块上，而不是集中在功能图案上的功能凸块上。
在一些示例实施例中，主虚设凸块不电连接到半导体芯片。因此，其中主虚设凸块没有被电连接的主虚设图案130没有电连接到半导体芯片。因此，尽管虚设凸块会由于应力而损坏，但是如果虚设凸块没有电连接到半导体芯片，则它将对半导体芯片的工作没有影响。
通过邻近功能凸块布置主虚设凸块，有效防止了在功能凸块上的应力集中。此外，辅助虚设图案132围绕功能图案120布置。辅助虚设凸块(未示出)安装在辅助虚设图案132上。
在一些示例实施例中，辅助虚设图案132具有与主虚设图案130基本相同的面积。此外，辅助虚设图案132基本垂直于应力的前进方向布置。
在一些示例实施例中，通过增大虚设凸块的尺寸来减轻应力。由于虚设凸块的尺寸取决于主虚设图案130和辅助虚设图案132的面积，所以主虚设图案130和辅助虚设图案132的面积大于功能图案120的面积。
可选地，尽管没有在附图中示出，为了加强功能图案120相对于应力的强度，功能图案120连接到相邻的主虚设图案130和辅助虚设图案132。
在一些示例实施例中，如图1和图2所示的主虚设图案130、辅助虚设图案132和功能图案120的布置和方向基于定位在绝缘基板110的上表面的中央部分上的半导体芯片。可选地，由于应力的前进方向受到绝缘基板110上的半导体芯片的位置影响，所以主虚设图案130、辅助虚设图案132和功能图案120的布置和方向可以根据绝缘基板上的半导体芯片的位置而改变。
参照图1和图2，应力集中在功能图案外面的主虚设图案和/或邻近功能图案的主虚设图案。此外，应力更多地集中在基本垂直于应力的前进方向的主虚设图案上。因此，功能图案上的应力被抑制或减少。
图3是示出根据一些示例实施例的封装基板的平面图，图4是图3中的部分“IV”的放大平面图。
此示例实施例的封装基板100a包括与图1中的封装基板100基本相同的元件，除了功能图案之外。
参照图3和图4，本示例实施例的功能图案120a基本平行于应力的前进方向布置。基本平行于应力的前进方向的功能图案120a不阻碍应力的前进。因此，应力没有集中在功能图案120a上，功能图案120a具有基本平行于应力的前进方向的长度方向。因而，由于应力没有集中在功能图案120a上，所以应力不集中在安装在功能图案120a上的功能凸块上。
根据本示例实施例，功能图案基本平行于应力的前进方向，使得应力不集中在功能图案上。因而，可以抑制由应力引起的对功能凸块的损坏。
图5是示出根据一些示例实施例的倒装芯片封装的截面图，图6是图5中的部分“VI”的放大截面图。
参照图5和图6，本示例实施例的倒装芯片封装200包括封装基板100、半导体芯片210、功能凸块220、主虚设凸块230、辅助虚设凸块232、模制构件240和外部端子250。
本示例实施例的封装基板100包括与图1中的封装基板100基本相同的元件。可选地，倒装芯片封装200可以包括代替图1中的封装基板100的封装基板100a。
半导体芯片210布置在封装基板100上。在一些示例实施例中，半导体芯片210具有其中布置接合焊盘212的有源区域。有源区域电连接到半导体芯片210中的结构。有源区域位于半导体芯片210的下表面上。也就是，有源区域面向封装基板100布置。因此，具有有源区域的半导体芯片210可以相应于面朝下的半导体芯片。
此外，半导体芯片210包括浮置焊盘214。浮置焊盘214不与半导体芯片210中的结构电连接。在一些示例实施例中，浮置焊盘214包括金属。
功能凸块220插置在半导体芯片210与封装基板100之间。在一些示例实施例中，功能凸块220插置在半导体芯片210的接合焊盘212与封装基板100的功能图案120之间以将接合焊盘212与功能图案120电连接。因此，来自半导体芯片210的电信号通过接合焊盘212和功能凸块220传输到封装基板100的功能图案120。
当倒装芯片封装200包括图3的封装基板100a时，应力没有集中在基本平行于应力的前进方向的功能图案120a上。因此，应力也不集中在功能图案120a上的功能凸块220上。因而，由应力引起的对功能凸块220的损伤被抑制或减少。
主虚设凸块230插置在半导体芯片210与封装基板100之间。在一些示例实施例中，主虚设凸块230插置在半导体芯片210的下表面上的钝化层(未示出)和封装基板100的主虚设图案130之间。换句话说，主虚设凸块230安装在主虚设图案130上。由于主虚设凸块230没有与半导体芯片210中的结构电连接，所以来自半导体芯片210的电信号没有传输到主虚设图案130。
主虚设凸块230在功能凸块220外面和/或邻近功能凸块220布置。因而，施加到功能凸块220的应力集中在主虚设凸块230上。此外，由于主虚设图案130基本垂直于应力的前进方向，所以应力集中在主虚设图案130上。因此，应力更多地集中在主虚设图案130上的主虚设凸块230上。也就是，应力集中在主虚设凸块230上，而不是在功能凸块220上。因而，由应力引起的对功能凸块220的损伤被抑制。
在一些示例实施例中，辅助虚设凸块232安装在辅助虚设图案132上。根据实施例，辅助虚设凸块232围绕功能凸块220中的一些或每个。功能凸块220附近的辅助虚设凸块232可以有效吸收朝向功能凸块220取向的应力。
在一些示例实施例中，主虚设凸块230和辅助虚设凸块232并不对应于半导体芯片210与封装基板100之间的电连接。因此，即使主虚设凸块230和辅助虚设凸块232被损坏，在半导体芯片与封装基板之间流动的电信号也没有中断。
在一些示例实施例中，如上所述，主虚设图案130和辅助虚设图案132具有比功能图案120大的面积。相应地，主虚设凸块230和辅助虚设凸块232也具有比功能凸块220大的尺寸。因而，较大的主虚设凸块230和较大的辅助虚设凸块232有效减轻了功能凸块220上的应力。
在一些示例实施例中，主虚设凸块230和辅助虚设凸块232固定到半导体芯片210的浮置焊盘214。固定到浮置焊盘214的主虚设凸块230和辅助虚设凸块232具有比固定到钝化层的虚设凸块更大的接合强度。因此，固定到浮置焊盘214的主虚设凸块230和辅助虚设凸块232比固定到没有浮置焊盘214的钝化层的那些虚设凸块更有效地减轻应力。
模制构件240形成在封装基板100上以覆盖半导体芯片210。在一些示例实施例中，模制构件240保护封装基板100的功能图案120、半导体芯片210和功能凸块220免受外部环境影响。根据实施例，模制构件240包括环氧模制化合物(EMC)。
外部端子250安装在封装基板100的下表面上。根据实施例，外部端子250电连接到封装基板100的功能图案120。因此，来自半导体芯片210的电信号通过接合焊盘212、功能凸块220和功能图案120传输到外部端子250。在一些示例实施例中，外部端子250包括焊球。
根据示例实施例，应力集中在虚设凸块上，而不是功能凸块上。因此，由应力引起的对功能凸块的损伤被抑制。
图7是示出根据一些示例实施例的倒装芯片封装的截面图。
本示例实施例的倒装芯片封装基板200a包括与图5中的封装基板200基本相同的元件，并且还包括第二半导体芯片。可选地，倒装芯片封装200a可以包括图3中的封装基板100a来代替图1中的封装基板100。
参照图7，本示例实施例的倒装芯片封装200a还包括堆叠在第一半导体芯片210上的第二半导体芯片260。本示例实施例的倒装芯片封装200a对应于具有多个半导体芯片依次堆叠的结构的多芯片封装。
在一些示例实施例中，第二半导体芯片260经由第二功能凸块270与第一半导体芯片210电连接。第一半导体芯片210包括构造为与第二功能凸块270电接触的插塞216。插塞216在竖直方向上穿过第一半导体芯片210形成以将第二功能凸块270与第一半导体芯片210的接合焊盘212电连接。
在一些示例实施中，插塞216从第一功能凸块220在竖直方向上延伸。因此，插塞216位于主虚设凸块230内侧。因而，主虚设凸块230保护插塞216和第一功能凸块220免受应力影响。
图8是示出根据一些示例实施例的倒装芯片封装的截面图。
本示例实施例的倒装芯片封装基板200b包括与图7中的封装基板200a基本相同的元件，除了第一半导体芯片之外。
参照图8，本示例实施例的倒装芯片封装200b对应于存储器-LSI型封装。也就是，第一半导体芯片210包括逻辑芯片，第二半导体芯片260包括存储器芯片。
第一半导体芯片210包括插塞216b。插塞216b竖直地设置在第一半导体芯片210的不与第二半导体芯片260接触的边缘部分中。因此，插塞216b不是布置在第一半导体芯片210的中央部分中。
图9是示出根据一些示例实施例的倒装芯片封装的截面图。
本示例实施例的倒装芯片封装基板200c包括与图7中的封装基板200a基本相同的元件，除了第一半导体芯片和虚设凸块之外。
参照图9，插塞216c仅布置在第一半导体芯片210的中央部分中。也就是，插塞216c不是布置在第一半导体芯片210的边缘部分中。
在一些示例实施例中，第一半导体芯片210的边缘部分是脆弱的。因而，第一半导体芯片210向上弯曲。为了防止第一半导体芯片210弯曲，虚设凸块230插置在第一半导体芯片210的边缘部分与封装基板100之间。
在一些示例实施例中，由于虚设凸块230布置在功能凸块220外面和/或邻近功能凸块220，所以虚设凸块230减轻了施加到功能凸块220的应力，以及防止第一半导体芯片210弯曲。功能凸块220接触插塞216c。
图10是示出根据一些示例实施例的倒装芯片封装的截面图。
参照图10，本示例实施例的倒装芯片封装300包括封装基板100、第一半导体芯片310、第二半导体芯片360、功能凸块320、主虚设凸块330、辅助虚设凸块332、模制构件340和外部端子350。
在一些示例实施例中，本示例实施例的封装基板100包括与图1中的封装基板100基本相同的元件。可选地，倒装芯片封装300可以包括图3中的封装基板100a来代替图1中的封装基板100。
第一半导体芯片310布置在封装基板100上。在一些示例实施例中，第一半导体芯片310包括其中布置接合焊盘312的有源区域。有源区域电连接到第一半导体芯片310中的结构。有源区域位于第一半导体芯片310的上表面上。也就是，有源区域远离封装基板100布置。因此，具有有源区域的第一半导体芯片310可以对应于面朝上的半导体芯片。
插塞316穿过第一半导体芯片310竖直地形成。插塞316电连接到接合焊盘312。插塞316通过第一半导体芯片310的下表面暴露。
此外，第一半导体芯片310包括浮置焊盘314。浮置焊盘314不与第一半导体芯片310中的结构电连接。在一些示例实施例中，浮置焊盘314包括金属。
功能凸块320插置在第一半导体芯片310和封装基板100之间。在一些示例实施例中，功能凸块320插置在第一半导体芯片310的插塞316和封装基板100的功能图案120之间以经由插塞316将接合焊盘312与功能图案120电连接。因此，来自第一半导体芯片310的电信号通过接合焊盘312、插塞316和功能凸块320传输到封装基板100的功能图案120。
主虚设凸块330安装在主虚设图案130上。因此，主虚设凸块330布置在功能凸块320外面和/或邻近功能凸块320。辅助虚设凸块332安装在辅助虚设图案132上。根据实施例，辅助虚设凸块332围绕功能凸块320。在一些示例实施例中，主虚设凸块330和辅助虚设凸块332具有比功能凸块320大的尺寸。此外，主虚设凸块330和辅助虚设凸块332固定到第一半导体芯片310的浮置焊盘314。
第二半导体芯片360堆叠在第一半导体芯片310上。第二半导体芯片360通过第二功能凸块370电连接到第一半导体芯片310的接合焊盘312。
模制构件340形成在封装基板100上以覆盖第一半导体芯片310和第二半导体芯片360。外部端子350安装在封装基板100的下表面上。
根据这些示例实施例，应力集中在邻近功能凸块和/或在功能凸块外面布置的主虚设图案上。此外，应力也被邻近功能图案的辅助虚设图案吸收。因此，应力不集中在功能图案上。因而，由应力引起的对功能凸块的损伤被抑制。
以上是对示例实施例的说明，而不应解释为对其的限制。尽管已经描述了几个示例实施例，但是本领域技术人员将容易地理解，在示例实施例中可以有许多修改，而都在本质上不背离本发明构思的新颖教导。因而，所有这样的修改都旨在被包括在本发明构思的由权利要求书所定义的范围内。
本申请要求于2010年8月24日在韩国知识产权局(KIPO)提交的韩国专利申请No.2010-81857的优先权，其内容通过引用整体结合于此。

Claims (29)

1.一种封装基板，包括：
绝缘基板，半导体芯片布置在该绝缘基板上；
功能图案，形成在所述绝缘基板上，其中所述功能图案电连接到所述半导体芯片；以及
主虚设图案，形成在所述绝缘基板的在所述功能图案外面和/或邻近所述功能图案的部分上，其中所述主虚设图案沿着所述绝缘基板上的应力的路径取向，该应力由所述绝缘基板与所述半导体芯片的热膨胀系数之间的差异产生。
2.如权利要求1所述的封装基板，其中所述主虚设图案垂直于所述应力的方向。
3.如权利要求1所述的封装基板，其中所述主虚设图案具有大于所述功能图案的面积。
4.如权利要求1所述的封装基板，还包括邻近所述功能图案的辅助虚设图案。
5.如权利要求4所述的封装基板，其中所述辅助虚设图案垂直于所述应力的方向。
6.如权利要求4所述的封装基板，其中所述辅助虚设图案具有大于所述功能图案的面积。
7.如权利要求1所述的封装基板，其中所述功能图案平行于应力的方向。
8.一种倒装芯片封装，包括：
半导体芯片；
封装基板，包括其上布置所述半导体芯片的绝缘基板、形成在所述绝缘基板上的功能图案以及形成在所述绝缘基板的一部分上的主虚设图案；
功能凸块，安装在所述功能图案上以将所述半导体芯片与所述功能图案电连接；以及
主虚设凸块，安装在所述主虚设图案上，该主虚设凸块定位于所述功能凸块的外面和/或邻近所述功能凸块，其中所述主虚设图案沿着所述绝缘基板上的应力的路径取向，该应力由所述绝缘基板与所述半导体芯片的热膨胀系数之间的差异产生。
9.如权利要求8所述的倒装芯片封装，其中所述主虚设凸块具有大于所述功能凸块的尺寸。
10.如权利要求8所述的倒装芯片封装，还包括在所述主虚设凸块和所述半导体芯片之间的浮置焊盘。
11.如权利要求8所述的倒装芯片封装，其中所述封装基板还包括邻近所述功能图案的辅助虚设图案，辅助虚设凸块安装在所述辅助虚设图案上。
12.如权利要求11所述的倒装芯片封装，其中所述辅助虚设凸块具有大于所述功能凸块的尺寸。
13.如权利要求11所述的倒装芯片封装，还包括插置在所述辅助虚设凸块和所述半导体芯片之间的浮置焊盘。
14.如权利要求8所述的倒装芯片封装，还包括模制构件，该模制构件形成在所述封装基板上并覆盖所述半导体芯片。
15.如权利要求8所述的倒装芯片封装，还包括安装在所述封装基板的下表面上的外部端子。
16.一种倒装芯片封装，包括：
封装基板包括绝缘基板、形成在所述绝缘基板上的功能图案以及形成在所述绝缘基板的一部分上的主虚设图案；
第一半导体芯片，安装在所述封装基板上，所述第一半导体芯片具有穿过所述第一半导体芯片形成的插塞；
第二半导体芯片，堆叠在所述第一半导体芯片上；
功能凸块，在所述插塞和所述功能图案之间以将所述第一半导体芯片与所述功能图案电连接；以及
主虚设凸块，安装在所述主虚设图案上，该主虚设凸块定位于所述功能凸块的外面和/或邻近所述功能凸块，其中所述主虚设凸块沿着所述绝缘基板上的应力的路径取向，该应力由所述绝缘基板和所述第一半导体芯片的热膨胀系数之间的差异产生。
17.如权利要求16所述的倒装芯片封装，其中所述第一半导体芯片的有源区域面向所述封装基板布置。
18.如权利要求16所述的倒装芯片封装，其中所述第一半导体芯片的有源区域远离所述封装基板布置。
19.如权利要求16所述的倒装芯片封装，其中所述插塞布置在所述第一半导体芯片的不与所述第二半导体芯片接触的边缘部分中。
20.如权利要求16所述的倒装芯片封装，其中所述插塞布置在所述第一半导体芯片的与所述第二半导体芯片接触的中央部分中。
21.一种封装基板，包括：
绝缘基板，其上布置半导体芯片；
功能图案，形成在所述绝缘基板上，其中所述功能图案电连接到所述半导体芯片；以及
主虚设图案，形成在所述绝缘基板的在所述功能图案外面和/或邻近所述功能图案的部分上，其中所述主虚设图案关于所述绝缘基板上的应力方向不同于所述功能图案取向，该应力由所述绝缘基板和所述半导体芯片的热膨胀系数的差异产生。
22.如权利要求21所述的封装基板，其中所述主虚设图案垂直于所述应力的方向。
23.如权利要求21所述的封装基板，其中所述主虚设图案具有大于所述功能图案的面积。
24.如权利要求21所述的封装基板，其中所述功能图案平行于所述应力的方向。
25.一种制造封装基板的方法，包括：
将半导体芯片布置在绝缘基板上；
在所述绝缘基板上形成功能图案，其中所述功能图案电连接到所述半导体芯片；以及
在所述绝缘基板的在所述功能图案外面和/或邻近所述功能图案的部分上形成主虚设图案，其中所述主虚设图案沿着所述绝缘基板上的应力路径取向，该应力由所述绝缘基板和所述半导体芯片的热膨胀系数的差异产生。
26.如权利要求25所述的方法，其中所述主虚设图案关于所述应力的方向不同于所述功能图案取向。
27.如权利要求25所述的方法，其中所述主虚设图案垂直于所述应力的方向。
28.如权利要求25所述的方法，其中所述主虚设图案具有大于所述功能图案的面积。
29.如权利要求25所述的方法，其中所述功能图案平行于所述应力的方向。
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