CN108735616B - 半导体装置结构的形成方法 - Google Patents

半导体装置结构的形成方法 Download PDF

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Publication number
CN108735616B
CN108735616B CN201711219754.6A CN201711219754A CN108735616B CN 108735616 B CN108735616 B CN 108735616B CN 201711219754 A CN201711219754 A CN 201711219754A CN 108735616 B CN108735616 B CN 108735616B
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conductive bumps
semiconductor structure
chips
central
conductive
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CN108735616A (zh
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施孟甫
黄震麟
李建成
朱则荣
陈文明
刘国洲
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Abstract

提供半导体装置结构的形成方法，此方法包含提供半导体结构，半导体结构具有中央部分和围绕中央部分的周边部分。此方法包含在半导体结构的表面上方形成多个第一导电凸块和多个虚设导电凸块，第一导电凸块在中央部分上方并电性连接至半导体结构，虚设导电凸块在周边部分上方并与半导体结构电性绝缘，第一导电凸块的每一个具有第一厚度和第一宽度，虚设导电凸块的每一个具有第二厚度和第二宽度，第二厚度小于第一厚度，且第二宽度大于第一宽度。

Description

半导体装置结构的形成方法
技术领域
本公开实施例涉及半导体技术，且特别涉及半导体装置结构的形成方法。
背景技术
半导体集成电路(integrated circuit，IC)工业已经历了快速成长。在集成电路材料和设计上的技术进步产生了数代集成电路，每一代都比前一代具有更小且更复杂的电路。然而，这些进步增加了加工与制造集成电路的复杂性。
在集成电路的发展史中，功能密度(即每一芯片区互连的装置数目)增加，同时几何尺寸(即制造过程中所产生的最小的组件(或线路))缩小。此元件尺寸微缩化的工艺一般来说具有增加生产效率与降低相关费用的益处。
然而，由于部件(feature)尺寸持续缩减，制造工艺持续变的更加难以实施。因此，形成越来越小的尺寸的可靠的半导体装置是个挑战。
发明内容
在一些实施例中，提供一种半导体装置结构的形成方法，此方法包含提供半导体结构，其中半导体结构具有中央部分和围绕中央部分的周边部分；以及在半导体结构的表面上方形成多个第一导电凸块和多个虚设导电凸块，其中第一导电凸块在中央部分上方并电性连接至半导体结构，虚设导电凸块在周边部分上方并与半导体结构电性绝缘，第一导电凸块的每一个具有第一厚度和第一宽度，虚设导电凸块的每一个具有第二厚度和第二宽度，第二厚度小于第一厚度，且第二宽度大于第一宽度。
在一些其他实施例中，提供一种半导体装置结构的形成方法，此方法包含提供半导体结构，其中半导体结构具有中央部分和围绕中央部分的周边部分；以及在半导体结构的表面上形成多个第一导电凸块和多个虚设导电凸块，其中第一导电凸块在中央部分上方并电性连接至半导体结构，虚设导电凸块在周边部分上方并与半导体结构电性绝缘，第一导电凸块的每一个具有第一厚度，虚设导电凸块的每一个具有第二厚度，第二厚度小于第一厚度，且虚设导电凸块与半导体结构之间的接触面积大于第一导电凸块与半导体结构之间的接触面积。
在另外一些实施例中，提供一种半导体装置结构的形成方法，此方法包含提供半导体结构，其中半导体结构具有中央部分和围绕中央部分的周边部分；以及在半导体结构的表面上方形成多个第一导电凸块和多个虚设导电凸块，其中第一导电凸块在中央部分上方并电性连接至半导体结构，虚设导电凸块在周边部分上方并与半导体结构电性绝缘，第一导电凸块的每一个具有第一厚度，虚设导电凸块的每一个具有第二厚度，第二厚度小于第一厚度，且虚设导电凸块的宽度大于第一导电凸块的相邻两者之间的距离。
附图说明
根据以下的详细说明并配合所附附图可以更加理解本公开实施例。应注意的是，根据本产业的标准惯例，图示中的各种部件并未必按照比例绘制。事实上，可能任意的放大或缩小各种部件的尺寸，以做清楚的说明。
图1A-1I为依据一些实施例的形成半导体装置结构的工艺的各种阶段的剖面示意图。
图1A-1到图1D-1为依据一些实施例的图1A-图1D的半导体装置结构的上视图。
图1A-2为依据一些实施例，沿图1A-1的线II-II’，半导体装置结构的剖面示意图。
图1I-1为依据一些实施例的图1I的半导体装置结构的上视图。
图2为依据一些实施例的半导体装置结构的上视图。
图3为依据一些实施例的半导体装置结构的上视图。
附图标记说明：
110 半导体结构
110C 中央部分
110P 周边部分
110a 中央芯片
110b 周边芯片
111、142 半导体基底
111a、111b 表面
112、114c 导通孔
113 绝缘层
114 重布线结构
114a、146、220 介电层
114b 线路层
116 第一导电垫
118 第二导电垫
119 介电层
119a、124a、124b、146a 开口
122、152 凸块下金属层
124 掩模层
126、128、154 导电层
130、160、170 焊料层
140 芯片
144、210 导电垫
150、230、B 导电凸块
150a、S1、S2 顶表面
180 底部填充层
190 模塑层
300 芯片封装体
DB 虚设导电凸块
Rc 中央芯片区域
Rp 周边芯片区域
SC 切割道
D1、D2、D3、D4 距离
G1、G2 间隙
H1、H2 高度
S3、S4 底表面
SW 弯曲侧壁
T1、T2 厚度
W1、W2、W3、W4 宽度
具体实施方式
要了解的是以下的公开内容提供许多不同的实施例或范例，以实施提供的主体的不同部件。以下叙述各个构件及其排列方式的特定范例，以求简化公开内容的说明。当然，这些仅为范例并非用以限定本公开实施例。例如，以下的公开内容叙述了将一第一部件形成于一第二部件之上或上方，即表示其包含了所形成的上述第一部件与上述第二部件是直接接触的实施例，亦包含了尚可将附加的部件形成于上述第一部件与上述第二部件之间，而使上述第一部件与上述第二部件可能未直接接触的实施例。此外，公开内容中不同范例可能使用重复的参考符号及/或用字。这些重复符号或用字是为了简化与清晰的目的，并非用以限定各个实施例及/或所述外观结构之间的关系。
再者，为了方便描述附图中一元件或部件与另一(复数)元件或(复数)部件的关系，可使用空间相关用语，例如“在...之下”、“下方”、“下部”、“上方”、“上部”及类似的用语。除了附图所绘示的方位之外，空间相关用语也涵盖装置在使用或操作中的不同方位。所述装置也可被另外定位(例如，旋转90度或者位于其他方位)，并对应地解读所使用的空间相关用语的描述。应当理解的是，可提供额外的操作于本公开实施例的方法之前、本公开实施例的方法中和本公开实施例的方法之后，且在本公开实施例的方法的其他实施例中，可取代或消除所述的一些操作。
也可包含其他部件和工艺，举例来说，可包含测试结构来帮助三维(3D)封装或三维集成电路(3DIC)装置的验证测试。举例来说，测试结构可包含形成于重布线层中或基底上的测试垫，以允许三维封装或三维集成电路的测试、探针及/或探针卡和类似物的使用。可实施验证测试于中间结构和最终结构。此外，此处公开的结构和方法可与包含良好晶粒的中间验证(intermediate verification)的测试方法结合使用，以增加产率并降低成本。
图1A-1I为依据一些实施例的形成半导体装置结构的工艺的各种阶段的剖面示意图。图1A-1到图1D-1为依据一些实施例的图1A-图1D的半导体装置结构的上视图。图1A-图1D为依据一些实施例，沿图1A-1到图1D-1的线I-I’，半导体装置结构的剖面示意图。图1A-2为依据一些实施例，沿图1A-1的线II-II’，半导体装置结构的剖面示意图。
依据一些实施例，如图1A、图1A-1和图1A-2所示，提供半导体结构110。在一些实施例中，半导体结构110为晶片。依据一些实施例，半导体结构110包含半导体基底111、导通孔112、重布线结构114、第一导电垫116、第二导电垫118和介电层119。
依据一些实施例，半导体基底111具有表面(有时也被称为顶表面)111a和111b。在一些实施例中，半导体基底111由包含单晶、多晶或非晶结构中的硅或锗的元素半导体材料制成。
在一些其他实施例中，半导体基底111由化合物半导体(例如碳化硅、砷化镓、磷化镓、磷化铟或砷化铟)、合金半导体(例如SiGe或GaAsP)或前述的组合制成。半导体基底111也可包含多层半导体、绝缘层上覆半导体(semiconductor on insulator，SOI)(例如绝缘层上覆硅或绝缘层上覆锗)或前述的组合。
在一些实施例中，半导体结构110为中介层晶片。依据一些实施例，导通孔112形成于半导体结构110中。导通孔112可形成为从表面111a延伸至半导体基底111中。
依据一些实施例，绝缘层113形成于导通孔112与半导体基底111之间。依据一些实施例，绝缘层113被配置使导通孔112与半导体基底111电性绝缘。
在一些其他实施例中，半导体结构110为包含有源装置或电路的装置晶片。有源装置可包含形成于表面111a上的晶体管(未显示)。依据一些实施例，半导体结构110也可包含形成于半导体基底111中或半导体基底111上方的无源装置(未显示)。无源装置包含电阻、电容或其他合适的无源装置。
依据一些实施例，重布线结构114形成于半导体基底111上方。依据一些实施例，第一导电垫116和第二导电垫118形成于重布线结构114上方。
依据一些实施例，重布线结构114包含介电层114a、线路层114b和导通孔114c。依据一些实施例，介电层114a形成于表面111a上方。依据一些实施例，线路层114b形成于介电层114a中。
依据一些实施例，如图1A和图1A-2所示，导通孔114c在不同的线路层114b之间和线路层114b、第一导电垫116与第二导电垫118之间电性连接。为了简洁起见，依据一些实施例，图1A和图1A-2仅显示其中一种线路层114b。依据一些实施例，导通孔112通过线路层114b和导通孔114c分别电性连接至第一导电垫116和第二导电垫118。
依据一些实施例，介电层119形成于介电层114a上方。依据一些实施例，介电层119覆盖整个第二导电垫118。依据一些实施例，介电层119具有多个开口119a各自暴露出第一导电垫116。
依据一些实施例，半导体结构110具有中央部分110C和围绕中央部分110C的周边部分110P。依据一些实施例，第一导电垫116形成于中央部分110C的半导体基底111上方。依据一些实施例，第二导电垫118形成于周边部分110P的半导体基底111上方。
依据一些实施例，如图1A和图1A-1所示，半导体结构110具有芯片区域R。在一些实施例中，预定的切割道SC在芯片区域R之间。依据一些实施例，芯片区域R包含中央芯片区域Rc和周边芯片区域Rp。依据一些实施例，第一导电垫116形成于中央芯片区域Rc中。依据一些实施例，第二导电垫118形成于周边芯片区域Rp中。
依据一些实施例，如图1B和图1B-1所示，凸块下金属(under bump metallurgy，UBM)层122形成于介电层119和第一导电垫116上。依据一些实施例，凸块下金属层122直接接触介电层119和第一导电垫116。依据一些实施例，凸块下金属层122包含扩散阻挡层(未显示)和籽晶层(未显示)。
依据一些实施例，籽晶层形成于扩散阻挡层上方。扩散阻挡层可为钛层、氮化钛层、钽层或氮化钽层。籽晶层的材料可包含铜或铜合金。籽晶层的材料可包含其他金属，例如银、金、铝和前述的组合。在一些其他实施例中，不形成扩散阻挡层。
依据一些实施例，如图1B和图1B-1所示，掩模层124形成于凸块下金属层122上方。依据一些实施例，掩模层124具有开口124a和124b。依据一些实施例，开口124a在中央芯片区域Rc中。依据一些实施例，开口124a暴露出第一导电垫116上方的凸块下金属层122。
依据一些实施例，开口124b在周边芯片区域Rp中。依据一些实施例，开口124b暴露出周边芯片区域Rp中的凸块下金属层122。依据一些实施例，开口124a具有宽度W1。依据一些实施例，开口124b具有宽度W2。在一些实施例中，宽度W1等于全部开口124a的平均宽度。在一些实施例中，宽度W2等于全部开口124b的平均宽度。
依据一些实施例，宽度W2大于宽度W1。在一些实施例中，宽度W2与宽度W1的比率在约2至约10的范围内。依据一些实施例，宽度W2与宽度W1的比率在约4至约6的范围内。依据一些实施例，宽度W1在约20μm至约45μm的范围内。依据一些实施例，宽度W2在约100μm至约250μm的范围内。在一些实施例中，开口124b的开口面积大于开口124a的开口面积。依据一些实施例，掩模层124包含聚合物材料，例如光致抗蚀剂材料。
开口124a在其中一个中央芯片区域Rc具有第一总开口面积，且此中央芯片区域Rc具有第一面积。依据一些实施例，掩模层124在一个中央芯片区域Rc中的第一开口比率等于第一总开口面积与第一面积的比率。
开口124b在其中一个周边芯片区域Rp具有第二总开口面积，且此周边芯片区域Rp具有第二面积。依据一些实施例，掩模层124在一个周边芯片区域Rp中的第二开口比率等于第二总开口面积与第二面积的比率。
依据一些实施例，第一开口比率接近或等于第二开口比率，以改善后续电镀工艺期间电力线分布的均匀性。在一些实施例中，第一开口比率与第二开口比率之间的差异在约-0.1至约0.1的范围内。
依据一些实施例，如图1C和图1C-1所示，导电层126形成于开口124a中，导电层128形成于开口124b中。依据一些实施例，导电层126比导电层128厚。导电层126和128包含铜或其他合适的导电材料。
依据一些实施例，导电层126和128由相同的材料制成。依据一些实施例，导电层126和128的形成包含实施电镀工艺或其他合适的工艺。依据一些实施例，导电层126和128在相同的工艺(例如相同的电镀工艺)中形成。依据一些实施例，导电层126和128同时形成。
依据一些实施例，如图1D和图1D-1所示，移除掩模层124和掩模层124下的凸块下金属层122。依据一些实施例，在移除工艺之后，导电层126和其下的凸块下金属层122共同形成导电凸块B。
依据一些实施例，导电凸块B形成于第一导电垫116的顶表面116a上方。依据一些实施例，导电凸块B电性连接至第一导电垫116。依据一些实施例，导电凸块B直接接触第一导电垫116。
依据一些实施例，导电层128和其下的凸块下金属层122共同形成虚设(dummy)导电凸块DB。依据一些实施例，虚设导电凸块DB围绕导电凸块B。依据一些实施例，整个虚设导电凸块DB形成于介电层119的顶表面119b上。
依据一些实施例，虚设导电凸块DB直接接触介电层119。依据一些实施例，虚设导电凸块DB通过介电层119与其下的第二导电垫118电性绝缘。
依据一些实施例，每一导电凸块B具有厚度T1和宽度W3。依据一些实施例，每一虚设导电凸块DB具有厚度T2和宽度W4。依据一些实施例，宽度W4大于宽度W3。在一些实施例中，宽度W4与宽度W3的比率在约2至约10的范围内。依据一些实施例，宽度W4与宽度W3的比率在约4至约6的范围内。
依据一些实施例，宽度W3在约20μm至约45μm的范围内。依据一些实施例，宽度W4在约100μm至约250μm的范围内。
依据一些实施例，厚度T2小于厚度T1。在一些实施例中，厚度T1与厚度T2的比率在约5至约15的范围内。依据一些实施例，厚度T1在约25μm至约40μm的范围内。依据一些实施例，厚度T2在约2μm至约20μm的范围内。依据一些实施例，厚度T2在约2μm至约5μm的范围内。
在一些实施例中，厚度T1和T2分别为导电凸块B和虚设导电凸块DB的最大厚度。在一些实施例中，宽度W3和W4分别为导电凸块B和虚设导电凸块DB的最大宽度。
在一些实施例中，导电凸块B的顶表面S1相对于第一导电垫116的顶表面116a具有高度H1。依据一些实施例，高度H1等于顶表面S1与顶表面116a之间的距离。
在一些实施例中，虚设导电凸块DB的顶表面S2相对于介电层119的顶表面119b具有高度H2。依据一些实施例，高度H2等于顶表面S2与顶表面119b之间的距离。依据一些实施例，高度H2小于高度H1。也就是说，依据一些实施例，顶表面S1和S2并非共平面。再者，依据一些实施例，导电凸块B的底表面S3和虚设导电凸块DB的底表面S4并非共平面。
依据一些实施例，高度H1在约25μm至约40μm的范围内。依据一些实施例，高度H2在约2μm至约20μm的范围内。依据一些实施例，高度H2在约2μm至约5μm的范围内。
在一些实施例中，虚设导电凸块DB与半导体结构110之间的接触面积大于导电凸块B与半导体结构110之间的接触面积。虚设导电凸块DB与半导体结构110之间大的接触面积可改善虚设导电凸块DB与半导体结构110之间的粘着力。
因此，依据一些实施例，在后续工艺期间，可防止有着大的接触面积和较小高度H2的虚设导电凸块DB从介电层119脱落。因此，依据一些实施例，改善了产率。
依据一些实施例，导电凸块B形成于中央部分110C上方并电性连接至半导体结构110。依据一些实施例，虚设导电凸块DB在周边部分110P上方并与半导体结构110电性绝缘。
依据一些实施例，导电凸块B在中央芯片区域Rc中。依据一些实施例，虚设导电凸块DB在周边芯片区域Rp中。在一些实施例中，在一个周边芯片区域Rp中的虚设导电凸块DB的数量少于在一个中央芯片区域Rc中的导电凸块B的数量。
在一些实施例中，如图1D-1所示，在一个周边芯片区域Rp中的两相邻虚设导电凸块DB之间的最小距离D2大于在一个中央芯片区域Rc中的两相邻导电凸块B之间的最小距离D1。
依据一些实施例，最小距离D1大于25μm。依据一些实施例，最小距离D1在约25μm至约200μm的范围内。依据一些实施例，最小距离D2大于100μm。依据一些实施例，最小距离D2在约100μm至约300μm的范围内。在一些实施例中，虚设导电凸块DB的宽度W4大于两相邻导电凸块B之间的距离D1。
在一些实施例中，虚设导电凸块DB的顶表面面积大于导电凸块B的顶表面面积。在一些实施例中，在一个中央芯片区域Rc中的导电凸块B的总顶表面面积大于在一个周边芯片区域Rp中的虚设导电凸块DB的总顶表面面积。
依据一些实施例，如图1D和图1D-1所示，焊料层130形成于导电凸块B的顶表面S1和虚设导电凸块DB的顶表面S2上方。依据一些实施例，焊料层130直接接触导电凸块B和虚设导电凸块DB。
焊料层130可为由例如SnAg形成的无铅预焊料(pre-solder)层，或包括锡、铅、铜、镍、铋或前述的组合的焊料层。在一些实施例中，助焊(flux)层(未显示)形成于焊料层130和导电凸块B上方以降低焊料层130的熔点。
在一些实施例中，虚设导电凸块DB与预定切割道SC之间的最小距离D3大于导电凸块B与预定切割道SC之间的最小距离D4。依据一些实施例，最小距离D3在约100μm至约200μm的范围内。依据一些实施例，最小距离D4在约70μm至约150μm的范围内。
虚设导电凸块DB为圆形、环形(如图2所示)、长条形(如图3所示)或其他合适的形状。为了简洁起见，图2-图3不显示焊料层130。依据一些实施例，如图2所示，仅一个虚设导电凸块DB形成于一个周边芯片区域Rp中。
依据一些实施例，如图1E所示，提供芯片140。为了简洁起见，依据一些实施例，图1E仅显示其中一个芯片140。依据一些实施例，芯片140包含半导体基底142、导电垫144和介电层146。
依据一些实施例，导电垫144形成于半导体基底142上方。依据一些实施例，介电层146形成于半导体基底142上方。依据一些实施例，介电层146具有开口146a暴露出其下的导电垫144。
依据一些实施例，如图1E所示，导电凸块150形成于导电垫144上。依据一些实施例，导电凸块150包含凸块下金属层152和导电层154。依据一些实施例，导电层154形成于凸块下金属层152上方。
依据一些实施例，凸块下金属层152可包含扩散阻挡层(未显示)和籽晶层(未显示)。扩散阻挡层可为钛层、氮化钛层、钽层或氮化钽层。
籽晶层的材料可包含铜或铜合金。籽晶层的材料可包含其他金属，例如银、金、铝和前述的组合。在一些其他实施例中，不形成扩散阻挡层。导电层154包含铜或其他合适的导电材料。
依据一些实施例，如图1E所示，焊料层160形成于导电凸块150的顶表面150a上方。焊料层160可为由例如SnAg形成的无铅预焊料层，或包括锡、铅、铜、镍、铋或前述的组合的焊料层。在一些实施例中，助焊(flux)层(未显示)形成于焊料层160和导电凸块150上方以降低焊料层160的熔点。
依据一些实施例，如图1F所示，将芯片140翻转，以通过芯片140与半导体结构110之间的导电凸块150和B接合至半导体结构110。依据一些实施例，接合工艺包含将焊料层160接合至焊料层130，并将焊料层130和160回焊(reflow)，以形成焊料层170于导电凸块150与导电凸块B之间。
依据一些实施例，在回焊工艺之后，实施清洁工艺(或清洗工艺)于芯片140和半导体结构110上方，以移除助焊层。由于虚设导电凸块DB具有(在虚设导电凸块DB与半导体结构110之间)大的接触面积和较低高度H2，因此在清洁工艺之后可保留虚设导电凸块DB。因此，依据一些实施例，改善了清洁工艺的产率。
再者，依据一些实施例，由于虚设导电凸块DB的宽度W4大于两相邻导电凸块B之间的距离D1，因此即使虚设导电凸块DB从介电层119脱落，虚设导电凸块DB不会落入导电凸块B之间的间隙G1。
依据一些实施例，如图1G所示，底部填充层180形成于半导体结构110与每一芯片140之间的间隙G2中。依据一些实施例，底部填充层180包含聚合物材料。
依据一些实施例，如图1G所示，模塑层190形成于半导体结构110上方以围绕芯片140以及导电凸块B和150。依据一些实施例，模塑层190包含聚合物材料。
依据一些实施例，如图1H所示，移除半导体基底111的下部。依据一些实施例，此移除工艺包含化学机械研磨工艺。
依据一些实施例，在移除工艺之后，暴露出导通孔112和绝缘层113。依据一些实施例，导通孔112和绝缘层113穿透半导体基底111。依据一些实施例，当半导体基底111为硅基底时，导通孔112也可被称为基底通孔电极或硅通孔电极。
依据一些实施例，如图1H所示，导电垫210形成于导通孔112上方。依据一些实施例，如图1H所示，介电层220形成于半导体基底111的表面111b上方。依据一些实施例，如图1H所示，导电凸块230形成于导电垫210上方。导电凸块230包含锡、铜或其他合适的导电材料。
依据一些实施例，图1I-1为依据一些实施例的图1I的半导体装置结构的上视图。依据一些实施例，如图1I和图1I-1所示，实施切割工艺以沿预定地切割道SC切割穿透介电层220、半导体结构110和模塑层190，以形成芯片封装体300。
依据一些实施例，在切割工艺之后，将半导体结构110切割为个别的中央芯片110a和周边芯片110b。依据一些实施例，每一芯片封装体300包含一个中央芯片110a、一个芯片140、中央芯片110a与芯片140之间的导电凸块150和B以及焊料层170。
依据一些实施例，在芯片封装体300中，中央芯片110a的表面111a上方的导电凸块B具有第一总顶表面面积。依据一些实施例，中央芯片110a具有第一顶表面面积。依据一些实施例，周边芯片110b的表面111b上方的虚设导电凸块DB具有第二总顶表面面积。依据一些实施例，周边芯片110b具有第二顶表面面积。
在一些实施例中，第一总顶表面面积与第一顶表面面积的第一比率接近或等于第二总顶表面面积与第二顶表面面积的第二比率。在一些实施例中，第一总顶表面面积与第一顶表面面积的第一比率与第二总顶表面面积与第二顶表面面积的第二比率之间的差异在约-0.1至约0.1的范围内。依据一些实施例，周边芯片110b具有弯曲侧壁SW。
依据一些实施例，提供半导体装置结构的形成方法。这些(用于形成半导体装置结构的)方法分别形成导电凸块和虚设导电凸块于晶片的中央区域和周边区域上方。虚设导电凸块相对于导电凸块具有(在凸块与晶片之间)较大的接触面积和较小的高度。因此，在后续的工艺期间，可防止虚设导电凸块从晶片脱落。因此，改善了产率。
依据一些实施例，提供半导体装置结构的形成方法，此方法包含提供半导体结构，半导体结构具有中央部分和围绕中央部分的周边部分。此方法包含在半导体结构的表面上方形成多个第一导电凸块和多个虚设导电凸块，第一导电凸块在中央部分上方并电性连接至半导体结构，虚设导电凸块在周边部分上方并与半导体结构电性绝缘，第一导电凸块的每一个具有第一厚度和第一宽度，虚设导电凸块的每一个具有第二厚度和第二宽度，第二厚度小于第一厚度，且第二宽度大于第一宽度。
在一些实施例中，该半导体结构为一晶片。
在一些实施例中，该半导体结构包括多个芯片区域，多个预定的切割道在所述多个芯片区域之间，所述多个芯片区域包括多个中央芯片区域和多个周边芯片区域，所述多个第一导电凸块在所述多个中央芯片区域中，所述多个虚设导电凸块在所述多个周边芯片区域中，且该方法还包括:在多个芯片上方形成多个第二导电凸块；通过所述多个芯片与该半导体结构之间的所述多个第二导电凸块和所述多个第一导电凸块将所述多个芯片接合至该半导体结构；以及沿所述多个预定的切割道将该半导体结构切割为个别的多个中央芯片和多个周边芯片，以产生多个芯片封装体，所述多个芯片封装体的每一个包括所述多个中央芯片的其中一个、所述多个芯片的其中一个以及在所述多个中央芯片的其中一个与所述多个芯片的其中一个之间的所述多个第二导电凸块和所述多个第一导电凸块。
在一些实施例中，半导体装置结构的形成方法还包括:在所述多个芯片接合至该半导体结构之后，在所述多个芯片与该半导体结构上方实施一清洁工艺；以及在该半导体结构与所述多个芯片的每一个之间的一间隙中形成一底部填充层。
在一些实施例中，该中央芯片的一第一顶表面上方的所述多个第一导电凸块具有一第一总顶表面面积，该中央芯片具有一第一顶表面面积，该周边芯片的一第二顶表面上方的所述多个虚设导电凸块具有一第二总顶表面面积，该周边芯片具有一第二顶表面面积，该第一总顶表面面积与该第一顶表面面积的一第一比率与该第二总顶表面面积与该第二顶表面面积的一第二比率之间的差异在约-0.1至约0.1的范围内。
在一些实施例中，在所述多个周边芯片区域的其中一个中的所述多个虚设导电凸块的数量小于所述多个中央芯片区域的其中一个中的所述多个第一导电凸块的数量。
在一些实施例中，所述多个周边芯片区域的其中一个中的所述多个虚设导电凸块之间的最小距离大于所述多个中央芯片区域的其中一个中的所述多个第一导电凸块之间的最小距离。
在一些实施例中，该第一导电凸块的一第一顶表面相对于该表面具有一第一高度，该虚设导电凸块的一第二顶表面相对于该表面具有一第二高度，且该第二高度小于该第一高度。
依据一些实施例，提供半导体装置结构的形成方法，此方法包含提供半导体结构，半导体结构具有中央部分和围绕中央部分的周边部分。此方法包含在半导体结构的表面上形成多个第一导电凸块和多个虚设导电凸块，第一导电凸块在中央部分上方并电性连接至半导体结构，虚设导电凸块在周边部分上方并与半导体结构电性绝缘，第一导电凸块的每一个具有第一厚度，虚设导电凸块的每一个具有第二厚度，第二厚度小于第一厚度，且虚设导电凸块与半导体结构之间的接触面积大于第一导电凸块与半导体结构之间的接触面积。
在一些实施例中，该虚设导电凸块的一顶表面面积大于该第一导电凸块的一顶表面面积。
在一些实施例中，该半导体结构包括一基底、多个第一导电垫、多个第二导电垫和一介电层，所述多个第一导电垫在该中央部分的该基底上方，所述多个第二导电垫在该周边部分的该基底上方，该介电层在该基底上方并覆盖整个所述多个第二导电垫，所述多个第一导电凸块形成于所述多个第一导电垫上并电性连接至所述多个第一导电垫，且整个所述多个虚设导电凸块形成于该介电层上并与所述多个第二导电垫电性绝缘。
在一些实施例中，所述多个第一导电凸块直接接触所述多个第一导电垫，且所述多个虚设导电凸块直接接触该介电层。
在一些实施例中，该半导体结构还包括多个导通孔穿透该基底并电性连接至所述多个第一导电垫。
在一些实施例中，该半导体结构包括多个芯片区域，多个预定的切割道在所述多个芯片区域之间，所述多个芯片区域包括多个中央芯片区域和多个周边芯片区域，所述多个第一导电凸块在所述多个中央芯片区域中，所述多个虚设导电凸块在所述多个周边芯片区域中，且该方法还包括:在多个芯片上方形成多个第二导电凸块；通过所述多个芯片与该半导体结构之间的所述多个第二导电凸块和所述多个第一导电凸块将所述多个芯片接合至该半导体结构；以及沿所述多个预定的切割道将该半导体结构切割为个别的多个中央芯片和多个周边芯片，以产生多个芯片封装体，所述多个芯片封装体的每一个包括所述多个中央芯片的其中一个、所述多个芯片的其中一个以及在所述多个中央芯片的其中一个与所述多个芯片的其中一个之间的所述多个第二导电凸块和所述多个第一导电凸块。
在一些实施例中，该周边芯片具有一弯曲侧壁。
依据一些实施例，提供半导体装置结构的形成方法，此方法包含提供半导体结构，半导体结构具有中央部分和围绕中央部分的周边部分。此方法包含在半导体结构的表面上方形成多个第一导电凸块和多个虚设导电凸块，第一导电凸块在中央部分上方并电性连接至半导体结构，虚设导电凸块在周边部分上方并与半导体结构电性绝缘，第一导电凸块的每一个具有第一厚度，虚设导电凸块的每一个具有第二厚度，第二厚度小于第一厚度，且虚设导电凸块的宽度大于第一导电凸块的相邻两者之间的距离。
在一些实施例中，该半导体结构包括多个芯片区域，多个预定的切割道在所述多个芯片区域之间，所述多个芯片区域包括多个中央芯片区域和多个周边芯片区域，所述多个第一导电凸块在所述多个中央芯片区域中，所述多个虚设导电凸块在所述多个周边芯片区域中，且该方法还包括:在多个芯片上方形成多个第二导电凸块；通过所述多个芯片与该半导体结构之间的所述多个第二导电凸块和所述多个第一导电凸块将所述多个芯片接合至该半导体结构；以及沿所述多个预定的切割道将该半导体结构切割为个别的多个中央芯片和多个周边芯片，以产生多个芯片封装体，所述多个芯片封装体的每一个包括所述多个中央芯片的其中一个、所述多个芯片的其中一个以及在所述多个中央芯片的其中一个与所述多个芯片的其中一个之间的所述多个第二导电凸块和所述多个第一导电凸块。
在一些实施例中，该中央芯片区域中的所述多个第一导电凸块的一第一总顶表面面积大于该周边芯片区域中的所述多个虚设导电凸块的一第二总顶表面面积。
在一些实施例中，在所述多个周边芯片区域中的所述多个虚设导电凸块的数量小于所述多个中央芯片区域的所述多个第一导电凸块的数量。
在一些实施例中，半导体装置结构的形成方法还包括:在所述多个芯片接合至该半导体结构之后，在所述多个芯片和该半导体结构上方实施一清洗工艺；在该半导体结构与所述多个芯片的每一个之间的一间隙中形成一底部填充层；以及在该半导体结构上方形成一模塑层以围绕所述多个芯片、所述多个第二导电凸块和所述多个第一导电凸块，其中切割该半导体结构的步骤还包括:切割所述多个芯片之间的该模塑层。
前述内文概述了许多实施例的特征，使本领域技术人员可以从各个方面更佳地了解本公开实施例。本领域技术人员应可理解，且可轻易地以本公开实施例为基础来设计或修饰其他工艺及结构，并以此达到相同的目的及/或达到与在此介绍的实施例等相同的优点。本领域技术人员也应了解这些相等的结构并未背离本公开的发明精神与范围。在不背离本公开的发明精神与范围的前提下，可对本公开进行各种改变、置换或修改。

Claims (17)

1.一种半导体装置结构的形成方法，包括:
提供一半导体结构，其中该半导体结构具有一中央部分和围绕该中央部分的一周边部分；以及
在该半导体结构的一表面上方形成多个第一导电凸块和多个虚设导电凸块，
其中所述多个第一导电凸块在该中央部分上方并电性连接至该半导体结构，所述多个虚设导电凸块在该周边部分上方并与该半导体结构电性绝缘，所述多个第一导电凸块的每一个具有一第一厚度和一第一宽度，所述多个虚设导电凸块的每一个具有一第二厚度和一第二宽度，该第二厚度小于该第一厚度，且该第二宽度大于该第一宽度；
其中该半导体结构包括多个芯片区域，多个预定的切割道在所述多个芯片区域之间，所述多个芯片区域包括多个中央芯片区域和多个周边芯片区域，所述多个第一导电凸块在所述多个中央芯片区域中，所述多个虚设导电凸块在所述多个周边芯片区域中，且该方法还包括:
在多个芯片上方形成多个第二导电凸块；
通过所述多个芯片与该半导体结构之间的所述多个第二导电凸块和所述多个第一导电凸块将所述多个芯片接合至该半导体结构；以及
沿所述多个预定的切割道将该半导体结构切割为个别的多个中央芯片和多个周边芯片，以产生多个芯片封装体，所述多个芯片封装体的每一个包括所述多个中央芯片的其中一个、所述多个芯片的其中一个以及在所述多个中央芯片的其中一个与所述多个芯片的其中一个之间的所述多个第二导电凸块和所述多个第一导电凸块。
2.如权利要求1所述的半导体装置结构的形成方法，其中该半导体结构为一晶片。
3.如权利要求1所述的半导体装置结构的形成方法，还包括:
在所述多个芯片接合至该半导体结构之后，在所述多个芯片与该半导体结构上方实施一清洁工艺；以及
在该半导体结构与所述多个芯片的每一个之间的一间隙中形成一底部填充层。
4.如权利要求1所述的半导体装置结构的形成方法，其中该中央芯片的一第一顶表面上方的所述多个第一导电凸块具有一第一总顶表面面积，该中央芯片具有一第一顶表面面积，该周边芯片的一第二顶表面上方的所述多个虚设导电凸块具有一第二总顶表面面积，该周边芯片具有一第二顶表面面积，该第一总顶表面面积与该第一顶表面面积的一第一比率与该第二总顶表面面积与该第二顶表面面积的一第二比率之间的差异在约-0.1至约0.1的范围内。
5.如权利要求1所述的半导体装置结构的形成方法，其中在所述多个周边芯片区域的其中一个中的所述多个虚设导电凸块的数量小于所述多个中央芯片区域的其中一个中的所述多个第一导电凸块的数量。
6.如权利要求1所述的半导体装置结构的形成方法，其中所述多个周边芯片区域的其中一个中的所述多个虚设导电凸块之间的最小距离大于所述多个中央芯片区域的其中一个中的所述多个第一导电凸块之间的最小距离。
7.如权利要求1所述的半导体装置结构的形成方法，其中该第一导电凸块的一第一顶表面相对于该表面具有一第一高度，该虚设导电凸块的一第二顶表面相对于该表面具有一第二高度，且该第二高度小于该第一高度。
8.一种半导体装置结构的形成方法，包括:
提供一半导体结构，其中该半导体结构具有一中央部分和围绕该中央部分的一周边部分；以及
在该半导体结构的一表面上形成多个第一导电凸块和多个虚设导电凸块，
其中所述多个第一导电凸块在该中央部分上方并电性连接至该半导体结构，所述多个虚设导电凸块在该周边部分上方并与该半导体结构电性绝缘，所述多个第一导电凸块的每一个具有一第一厚度，所述多个虚设导电凸块的每一个具有一第二厚度，该第二厚度小于该第一厚度，且该虚设导电凸块与该半导体结构之间的接触面积大于该第一导电凸块与该半导体结构之间的接触面积；
其中该半导体结构包括多个芯片区域，多个预定的切割道在所述多个芯片区域之间，所述多个芯片区域包括多个中央芯片区域和多个周边芯片区域，所述多个第一导电凸块在所述多个中央芯片区域中，所述多个虚设导电凸块在所述多个周边芯片区域中，且该方法还包括:
在多个芯片上方形成多个第二导电凸块；
通过所述多个芯片与该半导体结构之间的所述多个第二导电凸块和所述多个第一导电凸块将所述多个芯片接合至该半导体结构；以及
沿所述多个预定的切割道将该半导体结构切割为个别的多个中央芯片和多个周边芯片，以产生多个芯片封装体，所述多个芯片封装体的每一个包括所述多个中央芯片的其中一个、所述多个芯片的其中一个以及在所述多个中央芯片的其中一个与所述多个芯片的其中一个之间的所述多个第二导电凸块和所述多个第一导电凸块。
9.如权利要求8所述的半导体装置结构的形成方法，其中该虚设导电凸块的一顶表面面积大于该第一导电凸块的一顶表面面积。
10.如权利要求8所述的半导体装置结构的形成方法，其中该半导体结构包括一基底、多个第一导电垫、多个第二导电垫和一介电层，所述多个第一导电垫在该中央部分的该基底上方，所述多个第二导电垫在该周边部分的该基底上方，该介电层在该基底上方并覆盖整个所述多个第二导电垫，所述多个第一导电凸块形成于所述多个第一导电垫上并电性连接至所述多个第一导电垫，且整个所述多个虚设导电凸块形成于该介电层上并与所述多个第二导电垫电性绝缘。
11.如权利要求10所述的半导体装置结构的形成方法，其中所述多个第一导电凸块直接接触所述多个第一导电垫，且所述多个虚设导电凸块直接接触该介电层。
12.如权利要求10所述的半导体装置结构的形成方法，其中该半导体结构还包括多个导通孔穿透该基底并电性连接至所述多个第一导电垫。
13.如权利要求8所述的半导体装置结构的形成方法，其中该周边芯片具有一弯曲侧壁。
14.一种半导体装置结构的形成方法，包括:
提供一半导体结构，其中该半导体结构具有一中央部分和围绕该中央部分的一周边部分；以及
在该半导体结构的一表面上方形成多个第一导电凸块和多个虚设导电凸块，
其中所述多个第一导电凸块在该中央部分上方并电性连接至该半导体结构，所述多个虚设导电凸块在该周边部分上方并与该半导体结构电性绝缘，所述多个第一导电凸块的每一个具有一第一厚度，所述多个虚设导电凸块的每一个具有一第二厚度，该第二厚度小于该第一厚度，且该虚设导电凸块的宽度大于所述多个第一导电凸块的相邻两者之间的距离；
其中该半导体结构包括多个芯片区域，多个预定的切割道在所述多个芯片区域之间，所述多个芯片区域包括多个中央芯片区域和多个周边芯片区域，所述多个第一导电凸块在所述多个中央芯片区域中，所述多个虚设导电凸块在所述多个周边芯片区域中，且该方法还包括:
在多个芯片上方形成多个第二导电凸块；
通过所述多个芯片与该半导体结构之间的所述多个第二导电凸块和所述多个第一导电凸块将所述多个芯片接合至该半导体结构；以及
沿所述多个预定的切割道将该半导体结构切割为个别的多个中央芯片和多个周边芯片，以产生多个芯片封装体，所述多个芯片封装体的每一个包括所述多个中央芯片的其中一个、所述多个芯片的其中一个以及在所述多个中央芯片的其中一个与所述多个芯片的其中一个之间的所述多个第二导电凸块和所述多个第一导电凸块。
15.如权利要求14所述的半导体装置结构的形成方法，其中该中央芯片区域中的所述多个第一导电凸块的一第一总顶表面面积大于该周边芯片区域中的所述多个虚设导电凸块的一第二总顶表面面积。
16.如权利要求14所述的半导体装置结构的形成方法，其中在所述多个周边芯片区域中的所述多个虚设导电凸块的数量小于所述多个中央芯片区域的所述多个第一导电凸块的数量。
17.如权利要求14所述的半导体装置结构的形成方法，还包括:
在所述多个芯片接合至该半导体结构之后，在所述多个芯片和该半导体结构上方实施一清洗工艺；
在该半导体结构与所述多个芯片的每一个之间的一间隙中形成一底部填充层；以及
在该半导体结构上方形成一模塑层以围绕所述多个芯片、所述多个第二导电凸块和所述多个第一导电凸块，其中切割该半导体结构的步骤还包括:
切割所述多个芯片之间的该模塑层。
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