TWI517276B - 封裝結構 - Google Patents

封裝結構 Download PDF

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Publication number
TWI517276B
TWI517276B TW102128800A TW102128800A TWI517276B TW I517276 B TWI517276 B TW I517276B TW 102128800 A TW102128800 A TW 102128800A TW 102128800 A TW102128800 A TW 102128800A TW I517276 B TWI517276 B TW I517276B
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Taiwan
Prior art keywords
metal
bump
substrate
region
layer
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TW102128800A
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English (en)
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TW201409588A (zh
Inventor
林俊成
蔡柏豪
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台灣積體電路製造股份有限公司
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Publication of TW201409588A publication Critical patent/TW201409588A/zh
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Publication of TWI517276B publication Critical patent/TWI517276B/zh

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    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
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Description

封裝結構
本發明係有關於封裝結構，特別係有關於一種具有凸塊結構的封裝結構。
半導體封裝使用凸塊以建立晶片的輸入/輸出墊與基底之間的電性接觸。結構上來說，凸塊結構包括凸塊以及凸塊下金屬，此凸塊下金屬位於凸塊及輸入/輸出墊之間。根據凸塊的材料與形狀，此凸塊可分為焊接球、柱狀凸塊及具有混合金屬的金屬凸塊。近來，電子元件使用柱狀凸塊而不是焊接球以達到更細微的間距並使凸塊橋接的可能性變得最小，降低電路的電容負載並使電子元件得以於更高的頻率下運作。在覆蓋凸塊結構及連接電子元件時仍然需要焊接合金。假設使用適當的製程，柱狀凸塊幾乎可依據間距的考量而設於晶片上的任何位置。此外，可使用冗餘凸塊以增加對稱性、機械安定性、額外的熱安排或使互連最佳化以降低電感並增加元件運作速度。
根據某些實施例，封裝結構包括：第一基底，具有第一區及第二區，並包括金屬墊，位於第一區中的第一基底上；第一金屬柱，位於金屬墊上；鈍化層，位於第二區中的第一基底上；及第二金屬柱，位於第二區中的鈍化層上；以及第 二基底，包括第一連接器及第二連接器；其中第一基底結合至第二基底，其中第一焊接區形成於第一金屬柱與第一連接器之間，第二焊接區形成於第二金屬柱與第二連接器之間；以及其中第一金屬柱之厚度大於第二金屬柱之厚度。
根據某些實施例，封裝結構包括：第一基底，具有第一區及第二區，並包括金屬墊，位於第一區中的第一基底上；第一金屬柱，位於金屬墊上並電性連接金屬墊；鈍化層，位於第二區中的第一基底上；及第二金屬柱，位於第二區中的鈍化層上；以及第二基底，具有相反第一側及第二側，並包括第一連接器及第二連接器於第一側上；其中第一基底結合至第二基底的第一側，其中第一焊接區形成於第一金屬柱與第一連接器之間，第二焊接區形成於第二金屬柱與第二連接器之間；以及其中第一焊接區之厚度大於第二焊接區之厚度。
根據某些實施例，封裝結構之製造方法包括：提供半導體基底，具有第一區及第二區；形成金屬墊於半導體基底之第一區上；形成鈍化層於金屬墊及第一區與第二區中的半導體基底上；圖案化鈍化層以露出部分金屬墊；形成凸塊下金屬層於鈍化層及金屬墊的露出部分上；形成第一金屬柱於凸塊下金屬層上，且位於金屬墊的露出部分的上方；及形成第二金屬柱於凸塊下金屬層上，且位於第二區中的鈍化層的上方；其中第一金屬柱之厚度大於或等於第二金屬柱之厚度。
10‧‧‧第一基底
11‧‧‧半導體基底
12‧‧‧積體電路裝置
14‧‧‧互連結構
16‧‧‧金屬墊
16P‧‧‧連接部份
18‧‧‧鈍化層
18A‧‧‧介電層
18B‧‧‧第一聚合物層
18C‧‧‧第二聚合物層
18D‧‧‧聚合物緩衝物
18D1‧‧‧聚合物緩衝物
18D2‧‧‧第二聚合物層18C殘留於聚合物緩衝物18D1上的 部分
18P‧‧‧接著部分
19A‧‧‧開口
19B‧‧‧開口
19C‧‧‧開口
19d‧‧‧開口
19e‧‧‧開口
20‧‧‧凸塊下金屬層
20A‧‧‧第一凸塊下金屬層
20AT‧‧‧第一凸塊下金屬層20A之頂面
20AB‧‧‧第一凸塊下金屬層20A之底面
20D‧‧‧第二凸塊下金屬層
20DB‧‧‧第二凸塊下金屬層20D之底面
22A‧‧‧第一金屬柱
22AT‧‧‧第一金屬柱22A的頂面
22D‧‧‧第二金屬柱
22DT‧‧‧第二金屬柱22D的頂面
24A‧‧‧第一金屬蓋層
24AT‧‧‧第一金屬蓋層24A的頂面
24D‧‧‧第二金屬蓋層
24DT‧‧‧第二金屬蓋層24D的頂面
26A‧‧‧第一焊接蓋層
26AT‧‧‧第一焊接蓋層26A的頂面
26D‧‧‧第二焊接蓋層
26DT‧‧‧第二焊接蓋層26D之頂面
28A‧‧‧第一凸塊結構
28AT‧‧‧第一凸塊結構28A之頂部
28AB‧‧‧第一凸塊結構28A之底部
28D‧‧‧第二凸塊結構
28DT‧‧‧第二凸塊結構28D之頂部
28DB‧‧‧第二凸塊結構28D之底部
100‧‧‧半導體晶片
100A、100B、100C、100D、100E、100F、100G、100H、100I‧‧‧半導體晶片
110‧‧‧第一區
120‧‧‧第二區
200‧‧‧第二基底
200S1‧‧‧第一側
200S2‧‧‧第二側
202‧‧‧導孔
204‧‧‧第一接觸墊
206‧‧‧第一介電層
208A‧‧‧第一連接器
208B‧‧‧第二連接器
210‧‧‧第二接觸墊
212‧‧‧第二介電層
214‧‧‧連接器
300A、300B、300C、300D、300E、300F、300G、300H、 300I‧‧‧封裝結構
302‧‧‧第一焊接區
304‧‧‧第二焊接區
M1‧‧‧第一金屬堆疊
M2‧‧‧第二金屬堆疊
W1‧‧‧第一橫向尺寸
W2‧‧‧第二橫向尺寸
HA‧‧‧第一凸塊高度
HD‧‧‧第二凸塊高度
H1‧‧‧第一凸塊高度
H2‧‧‧第二凸塊高度
T22A、T24A、T26A、T22D、T24D、T26D‧‧‧厚度
T304 T302‧‧‧厚度
第1圖係根據某些實施例之具有多個凸塊結構之半導體晶 片的平面圖；第2圖係根據某些實施例之延著第1圖線段I-I之半導體晶片上的凸塊結構的剖面圖；第3A至3D圖係根據某些實施例之製造凸塊結構的各階段的剖面圖；第4圖係根據某些實施例之具有第3D圖所示之半導體晶片的封裝結構的剖面圖；第5A圖係根據某些實施例之半導體晶片上的凸塊結構的剖面圖；第5B圖係根據某些實施例之具有第5A圖所示之半導體晶片的封裝結構的剖面圖；第6A圖係根據某些實施例之半導體晶片上的凸塊結構的剖面圖；第6B圖係根據某些實施例之具有第6A圖所示之半導體晶片的封裝結構的剖面圖；第7A至7C圖係根據某些實施例之製造凸塊結構的各階段的剖面圖；第8圖係根據某些實施例之具有第7C圖所示之半導體晶片的封裝結構的剖面圖；第9A圖係根據某些實施例之半導體晶片上的凸塊結構的剖面圖；第9B圖係根據某些實施例之具有第9A圖所示之半導體晶片的封裝結構的剖面圖；第10A圖係根據某些實施例之半導體晶片上的凸塊結構的 剖面圖；第10B圖係根據某些實施例之具有第10A圖所示之半導體晶片的封裝結構的剖面圖；第11A至11B圖係根據某些實施例之製造凸塊結構的各階段的剖面圖；第12圖係根據某些實施例之具有第11B圖所示之半導體晶片的封裝結構的剖面圖；第13A圖係根據某些實施例之半導體晶片上的凸塊結構的剖面圖；第13B圖係根據某些實施例之具有第13A圖所示之半導體晶片的封裝結構的剖面圖；第14A圖係根據某些實施例之半導體晶片上的凸塊結構的剖面圖；第14B圖係根據某些實施例之具有第14A圖所示之半導體晶片的封裝結構的剖面圖。
應了解的是，以下之敘述提供許多不同的實施例或例子，用以實施本發明之不同樣態。以下所述特定的元件及排列方式儘為簡單描述本發明。當然，這些僅用以舉例而非本發明之限定。此外，在不同實施例中可能使用重複的標號或標示。這些重複僅為了簡單清楚地敘述本發明，不代表所討論之不同實施例及/或結構之間具有任何關連性。再者，當述及一第一材料層位於一第二材料層上或之上時，包括第一材料層與第二材料層直接接觸之情形。或者，亦可能間隔有一或更多其 它材料層之情形，在此情形中，第一材料層與第二材料層之間可能不直接接觸。
第1圖係根據某些實施例之具有多個凸塊結構之半導體晶片的平面圖。
如第1圖所示，半導體晶片100至少包括第一區110及第二區120，其中多個第一凸塊結構28A形成於第一區110上，多個第二凸塊結構28D形成於第二區120上。在一實施例中，第一區110位於半導體晶片100之中間區，第二區120位於半導體晶片100之周邊區。在某些實施例中，第一凸塊結構28A及第二凸塊結構28D係柱狀凸塊結構。在一實施例中，凸塊結構28A或28D之平面輪廓為方形。根據某些實施例，凸塊結構28A或28D之平面輪廓可為圓形、矩形、橢圓形、八邊形或其它相似結構。具有第一橫向尺寸W1(亦稱為第一凸塊結構之直徑或寬度)的第一凸塊結構28A在第一區110中具有第一凸塊密度；具有第二橫向尺寸W2(亦稱為第二凸塊結構之直徑或寬度)的第二凸塊結構28D在第二區120中具有第二凸塊密度。在一實施例中，第一凸塊密度與第二凸塊密度不同，而在另一實施例中，第一凸塊密度與第二凸塊密度相同。在一實施例中，第一凸塊結構28A的第一橫向尺寸W1在第一區110中相同；第二凸塊結構28D的第二橫向尺寸W2在第二區120中相同。在一實施例中，第一橫向尺寸W1與第二橫向尺寸W2不同。而在另一實施例中，第一橫向尺寸W1與第二橫向尺寸W2相同。舉例來說，半導體晶片100可為邏輯晶片或記憶體晶片。在一實施例中，第一凸塊結構28A係主動凸塊，例如為訊號凸塊；而第二凸塊 28D可為冗餘凸塊，其不提供晶片100與任何基底間的電性連接。在某些實施例中，如第1圖所示，第一區110小於第二區120，第一凸塊密度大於第二凸塊密度，且第一橫向尺寸W1小於第二橫向尺寸W2。例如，W1與W2之差異可為1至10μm。
第2圖係根據某些實施例之延著第1圖線I-I所繪之半導體晶片上的凸塊結構的剖面圖。半導體晶片100包括第一基底10；金屬墊16，設於第一基底10上；鈍化層18，位於金屬墊16上。第一凸塊結構28A藉由鈍化層18中的開口電性連接至金屬墊16，第二凸塊結構28D設於鈍化層18上且並未電性連接金屬墊16。在某些實施例中，第一基底10包括半導體基底11；積體電路裝置12，設於半導體基底11之中及/或之上；互連結構14，設於裝置12及半導體基底11上。
第一基底10使用於半導體積體電路的製程中，而積體電路可形成於第一基底10之中及/或之上。半導體基底11被定義為代表任何包括半導體材料的結構，此半導體材料包括，但不限定於，主體矽、半導體晶圓、絕緣層上覆矽(SOI)基底或矽化鍺基底。亦可使用其它包括第三族、第四族及第五族元素半導體材料。
形成於半導體基底11之中及/或之上的積體電路裝置12包括電晶體(亦即金氧半場效電晶體(MOSFET)、互補金氧半場效電晶體(CMOS)，雙極性接面電晶體(BJT)、高電壓電晶體、高頻率電晶體、P通道及/或N通道場效電晶體(PFETs/NFETs)等)、電阻、二極體、電容、電感、熔絲及其它適合的裝置。微電子元件互連並形成積體電路裝置，例如邏輯裝置、記憶體 裝置(亦即靜態隨機存取記憶體或SRAM)、射頻(RF)裝置、輸入/輸出(I/O)裝置、系統晶片(SoC)裝置、上述之組合及其它適合的裝置。
互連結構14包括位於積體電路裝置12上的層間介電層(未顯示)及金屬層(未顯示)。層間介電層包括低介電常數介電材料、未摻雜矽玻璃(USG)、氮化矽、氮氧化矽或其它常使用之材料。低介電常數介電材料的介電常數(k值)可小於約3.9，或小於2.8。金屬層可為銅(Cu)、鋁(Al)、AlCu、銅合金或其它導電材料。
金屬墊16係形成於互連結構14的層間介電層頂層的金屬層。在一實施例中，金屬墊16形成於半導體晶片100的第一區110中。在某些實施例中，金屬墊16形成於第一區110及第二區120上。例如，金屬墊16適合的材料包括，但不限於，Cu、Al、AlCu、銅合金或其它導電材料。金屬墊16提供電性連接。後續製程步驟中，第一凸塊結構28A形成於金屬墊16上並提供外部連接。
鈍化層18形成於互連結構14上且覆蓋金屬墊16的某些部份，而金屬墊16在第一區110中的某些部份藉由鈍化層18中的開口19露出(第3A圖及第3B圖)。在某些實施例中，鈍化層18包括介電層、聚合物層或上述之組合。鈍化層18可為單層或多層。在第2圖中，鈍化層18的單層僅用於說明之目的。因此，其它實施例可包括任何數量之鈍化層。鈍化層18可具有單一開口或多個開口19於金屬墊16上。第2圖中，具有兩個開口19的鈍化層18僅用於說明之目的。因此，其它實施例可包括任 何數量之開口19於金屬墊16上的鈍化層18中。
凸塊結構28A及28D形成於經圖案化且具有開口19的鈍化層18形成之後。在某些實施例中，第一凸塊結構28A形成於第一區110中的金屬墊16的露出部份上，第二凸塊結構28D形成於第二區120中的鈍化層18上。在至少一實施例中，凸塊結構28A及28D為柱狀凸塊。此柱狀凸塊以導電材料形成。在某些實施例中，柱狀凸塊包括凸塊下金屬(UBM)層、金屬柱及至少一個蓋層。金屬柱可包括Cu、銅合金、金(Au)、金合金或其它相似材料。蓋層可包Ni、焊錫、Au、Pd或任何其它貴金屬。
在第一區110上，第一凸塊結構28A具有第一凸塊高度HA，此第一凸塊高度HA係為第一凸塊結構28A之底部28AB至第一凸塊結構28A之頂部28AT之距離。在第二區120上，第二凸塊結構28D具有第二凸塊高度HD，此第二凸塊高度HD係為第二凸塊結構28D之底部28DB至第二凸塊結構28D之頂部28DT之距離。第二凸塊結構28D設於具有厚度T18的鈍化層18上。在某些實施例中，厚度T18大於約3μm。例如厚度T18為約1μm至約20μm。
根據某些實施例，為了減少或消除兩個凸塊結構頂部之間的間隙，第二凸塊高度HD被控制並使第一凸塊結構28A的頂部28AT與第二凸塊結構28D的頂部28DT實質上齊平。例如，頂部28AT與頂部28DT之間的間隙被控制在約0至約5μm的範圍、約0至約3μm的範圍或約0至約1μm的範圍。在某些實施例中，第一凸塊高度HA大於第二凸塊高度HD。例如第一凸塊高度HA與第二凸塊高度HD之差異為約1nm至約20nm。因為 頂部28AT與頂部28DT之間的間隙被減小，使得在晶片100結合至其它基底的封裝結構中控制間距(standoff)變得可行。作為範例的封裝結構包括具有凸塊結構的封裝基底上的晶片、具有凸塊結構的晶圓上的晶片或具有凸塊結構的其它晶片上的晶片。藉由控制晶片100中的凸塊，晶片100與其它基底之間的間距的差異可以被減少，使間距變得更均勻，並增進封裝結構中底部填充材料塗佈的品質。在某些實施例中，提供共平面凸塊結構的機制可使用於在晶片中的不同區有不同的關鍵尺寸的凸塊結構之製造中。
第3A至3D圖係根據某些實施例之製造凸塊結構的各階段的剖面圖。除非特別指明，此實施例之標號代表第1、2圖中的實施例的相似元件。
參見第3圖，提供具有積體電路裝置12(參見第2圖)的第一基底10，此第一基底10例如為包括多個晶片區的晶圓等級型態，此積體電路裝置12形成於半導體基底11之中或之上。互連結構14形成於半導體基底11上，金屬墊16形成於互連結構14上。在一實施例中，各晶片區包括第一區110及第二區120，金屬墊16形成於第一區110中的互連結構14上。鈍化層18形成於互連結構14及金屬墊16的覆蓋部份上。在某些實施例中，形成鈍化層18的步驟包括依序形成介電層18A及第一聚合物層18B於第一基底10上，接著形成開口19A於18A與18B的堆疊中，並露出部份金屬墊16。在某些實施例中，介電層18A包括由任何適合之方法形成的未摻雜矽玻璃(USG)、氮化矽、氧化矽、氮氧化矽或非開口材料，此適合之方法包括CVD、PVD或 其它相似之方法。介電層18A可為單層或多層。在某些實施例中，第一聚合物層18B為環氧化合物(epoxy)、聚醯亞胺(polyimide)、苯環丁烯(benzocyclobutene，BCB)、聚苯並噁唑(polybenzoxazole，PBO)或其它相似材料。也可使用其它相反軟的介電材料，例如有機介電材料。在一實施例中，開口19穿過介電層18A與第一聚合物層18B並露出金屬墊16的中間部分。
參見第3B圖，形成鈍化層18的步驟更包括形成第二聚合物層18C於第3A圖中得到的結構上。在某些實施例中，第二聚合物層18C為環氧化合物(epoxy)、聚醯亞胺(polyimide)、苯環丁烯(benzocyclobutene，BCB)、聚苯並噁唑(polybenzoxazole，PBO)或其它相似材料。也可使用其它相反軟的介電材料，例如有機介電材料。接著，另一開口19B與開口19C形成於第二聚合物層18C中。開口19B形成於第一區110的第二聚合物層18C中以露出金屬墊16的連接部份16P。在一實施例中，留在金屬墊16上的第二聚合物層18C形成至少一個聚合物緩衝物18D，此聚合物緩衝物18D隔離兩個鄰近的開口19B。開口19C形成於第二區120的第二聚合物層18C中以露出第一聚合物層18B的接著(landing)部分18P。
參見第3C圖，凸塊下金屬層20形成於第3B圖所示之結構上。凸塊下金屬層20覆蓋第二聚合物層18C、金屬墊16的連接部份16P及第一聚合物層18B的接著(landing)部分18P。在至少一實施例中，凸塊下金屬層包括擴散阻擋層(未顯示)，此擴散阻擋層可為鈦、鉭、氮化鈦、氮化鉭或相似的材料。在 某些實施例中，凸塊下金屬層20更包括晶種層(未顯示)形成於擴散阻擋層上。此晶種層可為銅、包括銀、鉻、鎳、鈦、金及上述之組合的銅合金。
接著，第一金屬堆疊M1形成於凸塊下金屬層20上並位於連接部分16P上方。在一實施例中，包括第一金屬柱22A、第一金屬蓋層24A及第一焊接蓋層26A的第一金屬堆疊M1形成於凸塊下金屬層20上並直接位於第一區110中的連接區16P上方。舉例來說，第一金屬堆疊M1可藉由光罩、微影步驟、圖案化步驟及乾/溼蝕刻步驟形成。在至少一實施例中，第一金屬柱22A包括一膜層，此膜層包含實質上純的銅元素、含有無法避免的雜質的銅及含有少量元素，例如為鉭、銦、錫、鋅、錳、鉻、鈦、鍺、鍶、鉑、鎂、鋁、鈷或鋯，的銅合金。在至少一實施例中，第一金屬柱22A具有小於約20μm的厚度T22A。在另一實施例中，厚度T22A為約1至約20μm，此厚度可更大或更小。
第一金屬蓋層24A形成於第一金屬柱22A上。第一金屬蓋層24A可作為阻擋層，防止第一金屬柱22A中的銅擴散進入用來連接第一基底10與外部元件的接合材料，例如焊接合金。防止銅的擴散可增加此電子封裝結構的可靠度與接合強度。在某些實施例中，第一金屬蓋層24A為金屬層，包括Ni、Sn、SnPb、Au、Ag、Pd、In、Pt、NiPdAu、NiAu、其它相似材料或合金。第一金屬蓋層24A可為多層結構或單層結構。在一實施例中，第一金屬蓋層24A具有小於約5μm的厚度T24A。在另一實施例中，厚度T24A為約0.5至約3μm。
第一焊接蓋層26A形成於第一金屬蓋層24A上。在某些實施例中，第一焊接蓋層26A由不含有鉛(lead-free)的焊接材料以電鍍方式形成，例如Sn、SnAg、Sn-Pb、SnAgCu(其中Cu之重量百分比小於或等於0.5%)、SnAgZn、SnZn、SnBi-In、Sn-In、Sn-Au、SnPb、SnCu、SnZnIn、SnAgSb及其它相似且適合之材料。在至少一實施例中，第一焊接蓋層26A具有可控制的體積。在一實施例中，第一焊接蓋層26A具有小於約10μm的可控制的厚度T26A。在另一實施例中，厚度T26A小於或等於約7μm。在至少一實施例中，厚度T26A被控制在約2μm至約7μm之間。
參見第3D圖，第二金屬堆疊M2形成於凸塊下金屬層20上且直接位於第二區120中的接著部分18P上方。在一實施例中，第二金屬堆疊M2包括第二金屬柱22D、第二金屬蓋層24D及第二焊接蓋層26D。舉例來說，第二金屬堆疊M2可藉由光罩、微影步驟、圖案化步驟及乾/溼蝕刻步驟形成。在至少一實施例中，第二金屬柱22D包括一膜層，此膜層包含實質上純的銅元素、含有無法避免的雜質的銅及含有少量元素，例如為鉭、銦、錫、鋅、錳、鉻、鈦、鍺、鍶、鉑、鎂、鋁、鈷或鋯，的銅合金。在一實施例中，第二金屬柱22D具有厚度T22D，此厚度T22D小於第一金屬柱22A具有厚度T22A。舉例來說，厚度T22D小於約5μm，此厚度可更大或更小。在某些實施例中，厚度T22A對厚度T22D的比值為約1至約4。
第二金屬蓋層24D形成於第二金屬柱22D上。在某些實施例中，第二金屬蓋層24D為金屬層，包括Ni、Sn、SnPb、 Au、Ag、Pd、In、Pt、NiPdAu、NiAu、其它相似材料或合金。第二金屬蓋層24D可為多層結構或單層結構。在一實施例中，第二金屬蓋層24D具有厚度T24D，此厚度T24D與第一金屬蓋層24A的厚度T24A實質上相同。在一實施例中，厚度T24D小於約5μm。例如，厚度T24D介於約0.5μm至約3μm之間。
第二焊接蓋層26D形成於第二金屬蓋層24D上。在某些實施例中，第二焊接蓋層26D由不含有鉛(lead-free)的焊接材料以電鍍方式形成，例如Sn、SnAg、Sn-Pb、SnAgCu(其中Cu之重量百分比小於或等於0.3%)、SnAgZn、SnZn、SnBi-In、Sn-In、Sn-Au、SnPb、SnCu、SnZnIn、SnAgSb及其它相似且適合之材料。在一實施例中，第二焊接蓋層26D具有厚度T26D，此厚度T26D大於第一焊接蓋層26A的厚度T26A。在某些實施例中，厚度T26D小於約10μm。在另一實施例中，厚度T26D小於或等於約7μm。在至少一其它實施例中，厚度T26D被控制在約2μm至約7μm之間。
形成第一金屬堆疊M1及第二金屬堆疊M2後，凸塊下金屬層20的露出部分被移除。在某些實施例中，位於第一金屬柱22A下的凸塊下金屬層20的殘留部分被稱作第一凸塊下金屬層20A，位於第二金屬柱22D下的凸塊下金屬層20的殘留部分被稱作第二凸塊下金屬層20D。因此，第一凸塊結構28A係包括第一凸塊下金屬層20A、第一金屬柱22A、第一金屬蓋層24A及第一焊接蓋層26A的堆疊。第二凸塊結構28D係包括第二凸塊下金屬層20D、第二金屬柱22D、第二金屬蓋層24D及第二焊接蓋層26D的堆疊。在一實施例中，藉由控制第二金屬柱22D 的厚度T22D與第二焊接蓋層26D的厚度T26D，第一焊接蓋層26A之頂面26AT與第二焊接蓋層26D之頂面26DT實質上齊平。例如，頂面26AT與頂面26DT之間的間隙被控制在約0至約5μm的範圍、約0至約3μm的範圍或約0至約1μm的範圍。如第3D圖所示，第一凸塊結構28A具有第一凸塊高度H1，此第一凸塊高度H1係為第一凸塊下金屬層20A之底面20AB至第一焊接蓋層26A之頂面26AT之距離。第二凸塊結構28D具有第二凸塊高度H2，此第二凸塊高度H2係為第二凸塊下金屬層20D之底面20DB至第二焊接蓋層26D之頂面26DT之距離。根據一實施例，由於第二凸塊結構28D位於層18A及層18B上，第一凸塊高度H1大於第二凸塊高度H2。例如，第一凸塊高度H1與第二凸塊高度H2之差異為約1nm至約20nm。藉由控制在不同區110與120中的金屬柱22A及22D的厚度，第一凸塊結構28A的頂部與第二凸塊結構28D的頂部實質上齊平。在某些實施例中，第一金屬柱22A的頂面22AT與第二金屬蓋層24D的頂面24DT實質上齊平。
在某些實施例中，第一基底10包括多個晶片區，此多個晶片區被切割並分離形成個別的晶片100A。第4圖係根據某些實施例之具有晶片100A結合至第二基底200的封裝結構300A的剖面圖。此第二基底200可為半導體晶圓、部份半導體晶圓、半導體晶片、封裝基底或電路板。在某些實施例中，第二基底200包括矽、砷化鎵、絕緣層上覆矽、玻璃、陶瓷、塑膠、有機材料、膠膜或其它支撐結構。在某些實施例中，第二基底200亦包括被動裝置，例如電阻、電容、電感及其它相似裝置；或主動裝置，例如電晶體。在某些實施例中，第二基底 200包括如第4圖所示之導孔202。根據某些實施例，導孔202可為銅、銅合金或其它導電材料。在一實施例中，第二基底200係作為中介層以將至少一個積體電路晶片與另一個晶片、晶圓或基底互連。在某些實施例中，第二基底200包括多個第一接觸墊204於第一側200S1上；第一介電層206於第一側200S1且覆蓋部份的接觸墊204；多個連接器208A及208B落於第一接觸墊204的露出部份上。根據某些實施例，連接器208A及208B可為具有相同材料及相同橫向尺寸的之金屬堆疊。在一實施例中，連接器208A或208B包括銅或銅合金的金屬柱。在某些實施例中，連接器208A或208B亦包括至少一金屬蓋層於金屬柱上，此金屬蓋層可為Ni、Au或焊錫。在某些實施例中，第二基底200亦包括多個第二接觸墊210於第二側200S2上，此第二側200S2與第一側200S1相反；第二介電層212於第二側200S2且覆蓋部份的第二接觸墊210；多個連接器214設於第二接觸墊210的露出部份上。在某些實施例中，連接器214為焊接球並形成第二基底與其下基底(未顯示)之間的連接。
第4圖中的封裝結構300A顯示藉由將第一基底10上的凸塊結構28A及28D連接至第二基底200上的連接器208A及208B，可將晶片100結合至第二基底200。藉由焊材再流動步驟，第一焊接區302形成於第一凸塊結構28A與第一連接器208A之間，第二焊接區304形成於第二凸塊結構28D與第二連接器208B之間。第一焊接區302的厚度T302可以根據第一焊接蓋層26A的體積及第一連接器208A上的焊接材料的體積而改變，第二焊接區304的厚度T304可以根據第二焊接蓋層26D的體 積及第二連接器208D上的焊接材料的體積而改變。在一實施例中，第二焊接區304的厚度T304大於第一焊接區302的厚度T302。第一基底10及第二基底200之間的距離係稱為”間距”(standoff)。在某些實施例中，在晶片100及第二基底200之間的空間填充底部填充材料以防止龜裂發生在焊接區中。藉由控制晶片100A中的凸塊結構28A及28D的高度，可以減少晶片100A及基底200間的間距(standoff)變化並使得間距(standoff)變得更均勻、底部填充材料形成步驟變得可控制且可再現。上述做為範例的晶片封裝結構包括位於具有凸塊結構的基底上的晶片。然而，在某些實施例中，凸塊結構可應用於包括位於不具有凸塊結構的基底上的晶片封裝結構。
第5A圖係根據某些實施例之半導體晶片100B上的凸塊結構的剖面圖，第5B圖係根據某些實施例之具有半導體晶片100B結合至第二基底200的結構的封裝結構300B的剖面圖。除非特別指明，此實施例之標號代表第1-4圖中的實施例的相似元件。
參照第5A圖，藉由控制晶片100B上不同區110及120中的金屬柱22A及22D的厚度，第一凸塊結構28A的頂部與第二凸塊結構28D的頂部實質上齊平。因此，第一焊接蓋層26A的頂面26AT與第二焊接蓋層26D的頂面26DT實質上齊平。由於第一凸塊結構28A位於金屬墊16上且第二凸塊結構28D位於層18A及18B上，第一凸塊高度H1大於第二凸塊高度H2。在某些實施例中，凸塊結構28A及28D的層的厚度滿足以下條件。T22A大於T22D、T24A與T24D實質上相同、T26A與T26D實質上相同。例 如，T22A與T22D的差異為約1至約20μm。在某些實施例中，第一金屬柱22A的頂面22AT與第二金屬柱22D的頂面22DT實質上齊平。參見第5B圖，封裝結構300B顯示藉由將第一基底10上的凸塊結構28A及28D個別與第二基底200上的第一連接器208A及208B連結，晶片100B可結合至第二基底200。在一實施例中，第二焊接區304的厚度T304與第一焊接區302的厚度T302實質上相同。
第6A圖係根據某些實施例之半導體晶片100C上的凸塊結構的剖面圖，第6B圖係根據某些實施例之具有半導體晶片100C結合至第二基底200的結構的封裝結構300C的剖面圖。除非特別指明，此實施例之標號代表第1-4圖中的實施例的相似元件。
參照第6A圖，藉由控制晶片100C上不同區110及120中的焊接蓋層26A及26D的厚度，第一凸塊結構28A的頂部與第二凸塊結構28D的頂部實質上齊平。因此，第一焊接蓋層26A的頂面26AT與第二焊接蓋層26D的頂面26DT實質上齊平。在某些實施例中，凸塊結構28A及28D的凸塊高度及層的厚度滿足以下條件。H1大於H2、T22A與T22D實質上相同、T24A與T24D實質上相同、T26A大於T26D。例如，T26A對T26D的比值為約1.5至約3。在另一實施例中，T26A與T26D的差異為約1至約10μm。在某些實施例中，第一金屬柱22A的頂面22AT低於第二金屬柱22D的頂面22DT，第一金屬蓋層24A的頂面24AT低於第二金屬蓋層24D的頂面24DT。參見第6B圖，封裝結構300C顯示藉由將第一基底10上的凸塊結構28A及28D個別與第二基底200上的 連接器208A及208B連結，晶片100C可結合至第二基底200。在一實施例中，第一焊接區302的厚度T302大於第二焊接區304的厚度T304。例如，T302對T304的比值為約1.5至約3。
第7A至7C圖係根據某些實施例之製造凸塊結構的各階段的剖面圖。除非特別指明，此實施例之標號代表第3A至3D圖中的實施例的相似元件。
參見第7A圖，鈍化層18的形成步驟包括形成介電層18A，接著形成開口於介電層18A中並露出部分金屬墊16。接著，形成第一聚合物層18B於介電層18A及金屬墊16的露出部分上，接著，形成至少兩個開口19d於第一聚合物層18B中。第二開口19d形成於第一區110中以露出部分金屬墊16。在一實施例中，殘留於金屬墊16上的第一聚合物層18B形成至少一個聚合物緩衝物18D1，此聚合物緩衝物18D1隔離兩個鄰近的開口19d。
參見第7B圖，第二聚合物層18C形成於第7A圖所示之結構上。接著，另外的開口19e及19c形成於第一區110及第二區120的第二聚合物層18C中，在某些實施例中，至少兩個開口19e個別形成於兩個開口19d中以露出第一區110中的金屬墊16的至少兩個連接部分16P。在一實施例中，如第7B圖所示，第二聚合物層18C包括殘留於聚合物緩衝物18D1上的18D2部分，18D2隔離兩個鄰近的開口19e。在某些實施例中，至少一個開口19c形成於第一區110中以露出第一聚合物層18B的接著部分18P。
接著，如第7C圖所示，凸塊結構28A及28D個別形 成於連接部分16P及接著部分18P上。第一凸塊結構28A形成於連接部分16P上，第二凸塊結構28D形成於第二聚合物層18C的接著部分18P上。在一實施例中，第一凸塊結構28A包括第一凸塊下金屬層20A、第一金屬柱22A、第一金屬蓋層24A及第一焊接蓋層26A。在一實施例中，第二凸塊結構28D包括第二凸塊下金屬層20D、第二金屬柱22D、第二金屬蓋層24D及第二焊接蓋層26D。藉由控制不同區110及120中金屬柱22A及22D的厚度，第一凸塊結構28A之頂面與第二凸塊結構28D之頂面實質上齊平。由於第一凸塊結構28A位於金屬墊16上且第二凸塊結構28D位於層18A及18B上，第一凸塊高度H1大於第二凸塊高度H2。在某些實施例中，凸塊結構28A及28D的層的厚度滿足以下條件。T22A大於T22D、T24A與T24D實質上相同、T26A小於T26D。例如，T22A與T22D的差異為約1至約20μm。在某些實施例中，第一金屬柱22A的頂面22AT與第二金屬蓋層24D的頂面24DT實質上齊平。
在某些實施例中，第一基底10包括多個晶片區，此多個晶片區被切割並分離形成個別的晶片100D。第8圖係根據某些實施例之具有晶片100D結合至第二基底200的封裝結構300D的剖面圖。除非特別指明，此實施例之標號代表第4圖中的實施例的相似元件。封裝結構300D顯示藉由將第一基底10上的凸塊結構28A及28D個別與第二基底200上的連接器208A及208B連結，晶片100D可結合至第二基底200。在一實施例中，第二焊接區304的厚度T304大於第一焊接區302的厚度T302。
第9A圖係根據某些實施例之半導體晶片100E上的 凸塊結構的剖面圖，第9B圖係根據某些實施例之具有半導體晶片100E結合至第二基底200的結構的封裝結構300E的剖面圖。除非特別指明，此實施例之標號代表第7-8圖中的實施例的相似元件。
參照第9A圖，第一凸塊結構28A的頂部與第二凸塊結構28D的頂部實質上齊平。在一實施例中，第一焊接蓋層26A的頂面26AT與第二焊接蓋層26D的頂面26DT實質上齊平。在某些實施例中，凸塊結構28A及28D的凸塊高度及層的厚度滿足以下條件。H1大於H2、T22A大於T22D、T24A與T24D實質上相同、T26A與T26D實質上相同。例如，T22A與T22D的差異為約1至約20μm。在某些實施例中，第一金屬柱22A的頂面22AT與第二金屬柱22D的頂面22DT實質上齊平。參見第9B圖，其顯示於封裝結構300E中，藉由將第一基底10上的凸塊結構28A及28D個別與第二基底200上的連接器208A及208B連結，晶片100E可結合至第二基底200。在一實施例中，第二焊接區304的厚度T304與第一焊接區302的厚度T302實質上相同。
第10A圖係根據某些實施例之半導體晶片100F上的凸塊結構的剖面圖，第10B圖係根據某些實施例之具有半導體晶片100F結合至第二基底200的結構的封裝結構300F的剖面圖。除非特別指明，此實施例之標號代表第7-8圖中的實施例的相似元件。
參照第10A圖，第一凸塊結構28A的頂部與第二凸塊結構28D的頂部實質上齊平。在一實施例中，第一焊接蓋層26A的頂面26AT與第二焊接蓋層26D的頂面26DT實質上齊平。 在某些實施例中，凸塊結構28A及28D的凸塊高度及層的厚度滿足以下條件。H1大於H2、T22A與T22D實質上相同、T24A與T24D實質上相同、T26A大於T26D。例如，T26A對T26D的比值為約1.5至約3。在另一實施例中，T26A與T26D的差異為約1至約10μm。在某些實施例中，第一金屬柱22A的頂面22AT低於第二金屬柱22D的頂面22DT，第一金屬蓋層24A的頂面24AT低於第二金屬蓋層24D的頂面24DT。參見第10B圖，其顯示封裝結構300F中，藉由將第一基底10上的凸塊結構28A及28D個別與第二基底200上的連接器208A及208B連結，晶片100F可結合至第二基底200。在一實施例中，第一焊接區302的厚度T302大於第二焊接區304的厚度T304。例如，T302對T304的比值為約1.5至約3。
第11A至11B圖係根據某些實施例之製造凸塊結構的各階段的剖面圖。除非特別指明，此實施例之標號代表第3A至3D圖中的實施例的相似元件。
參見第11A圖，鈍化層18的形成步驟包括形成介電層18A及第一聚合物層18B，接著形成穿過層18A及18B的開口19a並露出金屬墊16的連接部分16P。接著，如第11B圖所示，第一凸塊結構28A形成於連接部分16P上，第二凸塊結構28D形成於第一聚合物層18B中預定的18P部分上。藉由控制不同區110及120中金屬柱22A及22D的厚度，第一凸塊結構28A之頂面與第二凸塊結構28D之頂面實質上齊平。在某些實施例中，凸塊結構28A及28D的凸塊高度及層的厚度滿足以下條件。H1大於H2、T22A大於T22D、T24A與T24D實質上相同、T26A小於T26D。在某些實施例中，第一金屬柱22A的頂面22AT與第二金屬蓋層 24D的頂面24DT實質上齊平。
在某些實施例中，第一基底10包括多個晶片區，此多個晶片區被切割並分離形成個別的晶片100G。第12圖係根據某些實施例之具有晶片100G結合至第二基底200的封裝結構300G的剖面圖。除非特別指明，此實施例之標號代表第4圖中的實施例的相似元件。在封裝結構300G中，藉由將第一基底10上的凸塊結構28A及28D個別與第二基底200上的連接器208A及208B連結，晶片100G可結合至第二基底200。在一實施例中，第二焊接區304的厚度T304大於第一焊接區302的厚度T302。
第13A圖係根據某些實施例之半導體晶片100H上的凸塊結構的剖面圖，第13B圖係根據某些實施例之具有半導體晶片100H結合至第二基底200的結構的封裝結構300H的剖面圖。除非特別指明，此實施例之標號代表第11-12圖中的實施例的相似元件。
參照第13A圖，第一凸塊結構28A的頂部與第二凸塊結構28D的頂部實質上齊平。在一實施例中，第一焊接蓋層26A的頂面26AT與第二焊接蓋層26D的頂面26DT實質上齊平。在某些實施例中，凸塊結構28A及28D的凸塊高度及層的厚度滿足以下條件。H1大於H2、T22A大於T22D、T24A與T24D實質上相同、T26A與T26D實質上相同。例如，T22A對T22D的差異為約1至約20μm。在某些實施例中，第一金屬柱22A的頂面22AT與第二金屬柱22D的頂面22DT實質上齊平。參見第13B圖，封裝結構300H顯示藉由將第一基底10上的凸塊結構28A及28D個別與第二基底200上的連接器208A及208B連結，晶片100E可結合至 第二基底200。在一實施例中，第二焊接區304的厚度T304與第一焊接區302的厚度T302實質上相同。
第14A圖係根據某些實施例之半導體晶片100I上的凸塊結構的剖面圖，第13B圖係根據某些實施例之具有半導體晶片100I結合至第二基底200的結構的封裝結構300I的剖面圖。除非特別指明，此實施例之標號代表第11-12圖中的實施例的相似元件。
參照第14A圖，第一凸塊結構28A的頂部與第二凸塊結構28D的頂部實質上齊平。在一實施例中，第一焊接蓋層26A的頂面26AT與第二焊接蓋層26D的頂面26DT實質上齊平。在某些實施例中，凸塊結構28A及28D的凸塊高度及層的厚度滿足以下條件。H1大於H2、T22A與T22D實質上相同、T24A與T24D實質上相同、T26A大於T26D。例如，T26A對T26D的比值為約1.5至約3。在另一實施例中，T26A對T26D的差異為約1至約10μm。在某些實施例中，第一金屬柱22A的頂面22AT低於第二金屬柱22D的頂面22DT，第一金屬蓋層24A的頂面24AT低於第二金屬蓋層24D的頂面24DT。參見第14B圖，封裝結構300I顯示藉由將第一基底10上的凸塊結構28A及28D個別與第二基底200上的連接器208A及208B連結，晶片100I可結合至第二基底200。在一實施例中，第一焊接區302的厚度T302大於第二焊接區304的厚度T304。例如，T302對T304的比值為約1.5至約3。
雖然本發明的實施例及其優點已揭露如上，但應該瞭解的是，任何所屬技術領域中具有通常知識者，在不脫離本發明之精神和範圍內，當可作更動、替代與潤飾。此外，本 發明之保護範圍並未侷限於說明書內所述特定實施例中的製程、機器、製造、物質組成、裝置、方法及步驟，任何所屬技術領域中具有通常知識者可從本發明揭示內容中理解現行或未來所發展出的製程、機器、製造、物質組成、裝置、方法及步驟，只要可以在此處所述實施例中實施大抵相同功能或獲得大抵相同結果皆可根據本發明使用。因此，本發明之保護範圍包括上述製程、機器、製造、物質組成、裝置、方法及步驟。另外，每一申請專利範圍構成個別的實施例，且本發明之保護範圍也包括各個申請專利範圍及實施例的組合。
10‧‧‧第一基底
18A‧‧‧介電層
18B‧‧‧第一聚合物層
18C‧‧‧第二聚合物層
20A‧‧‧第一凸塊下金屬層
20AT‧‧‧第一凸塊下金屬層20A之頂面
20AB‧‧‧第一凸塊下金屬層20A之底面
20D‧‧‧第二凸塊下金屬層
20DB‧‧‧第二凸塊下金屬層20D之底面
22AT‧‧‧第一金屬柱22A的頂面
22D‧‧‧第二金屬柱
24D‧‧‧第二金屬蓋層
24DT‧‧‧第二金屬蓋層24D的頂面
26D‧‧‧第二焊接蓋層
26DT‧‧‧第二焊接蓋層26D之頂面
28A‧‧‧第一凸塊結構
28D‧‧‧第二凸塊結構
110‧‧‧第一區
120‧‧‧第二區
M2‧‧‧第二金屬堆疊
H1‧‧‧第一凸塊高度
H2‧‧‧第二凸塊高度
T22D、T24D、T26D‧‧‧厚度

Claims (10)

  1. 一種封裝結構，包括：一第一基底，具有一第一區及一第二區，並包括一金屬墊，位於該第一區中的該第一基底上；一第一金屬柱，位於該金屬墊上；一鈍化層，位於該第二區中的該第一基底上；及一第二金屬柱，位於該第二區中的該鈍化層上；以及一第二基底，包括一第一連接器及一第二連接器；其中該第一基底結合至該第二基底，其中一第一焊接區形成於該第一金屬柱與該第一連接器之間，一第二焊接區形成於該第二金屬柱與該第二連接器之間；以及其中該第一金屬柱之厚度大於該第二金屬柱之厚度。
  2. 如申請專利範圍第1項所述之封裝結構，其中該第二焊接區的厚度大於或實質相同於該第一焊接區的厚度。
  3. 如申請專利範圍第1項所述之封裝結構，其中該鈍化層位於該第一區中的該第一基底上並包括至少一開口，露出該金屬墊的一部分且該第一金屬柱位於該金屬墊的露出部份的上方。
  4. 如申請專利範圍第3項所述之封裝結構，其中該鈍化層包括至少兩個開口，露出該金屬墊的兩個部份，且該兩個開口藉由該金屬墊上的部份鈍化層隔離。
  5. 如申請專利範圍第1項所述之封裝結構，更包括一第一金屬蓋層，設於該第一金屬柱與該第一焊接區之間；及一第二金屬蓋層，設於該第二金屬柱與該第二焊接區之間。
  6. 如申請專利範圍第1項所述之封裝結構，更包括一導孔， 穿過該第二基底並電性連接該第一連接器。
  7. 一種封裝結構，包括：一第一基底，具有一第一區及一第二區，並包括一金屬墊，位於該第一區中的該第一基底上；一第一金屬柱，位於該金屬墊上並電性連接該金屬墊；一鈍化層，位於該第二區中的該第一基底上；及一第二金屬柱，位於該第二區中的該鈍化層上；以及一第二基底，具有相反一第一側及一第二側，並包括一第一連接器及一第二連接器於該第一側上；其中該第一基底結合至該第二基底的第一側，其中一第一焊接區形成於該第一金屬柱與該第一連接器之間，一第二焊接區形成於該第二金屬柱與該第二連接器之間；以及其中該第一焊接區之厚度大於該第二焊接區之厚度。
  8. 如申請專利範圍第7項所述之封裝結構，其中該第一金屬柱的厚度與該第二金屬柱的厚度實質相同。
  9. 如申請專利範圍第7項所述之封裝結構，其中該鈍化層位於該第一區中的該第一基底上並包括至少一開口，露出該金屬墊的一部分，且該第一金屬柱位於該該金屬墊的露出部份的上方。
  10. 如申請專利範圍第9項所述之封裝結構，其中該鈍化層包括至少兩個開口，露出該金屬墊的至少兩個部份，且該至少兩個開口藉由該金屬墊上的部份鈍化層隔離。
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