TW202109807A - 電子裝置 - Google Patents

電子裝置 Download PDF

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Publication number
TW202109807A
TW202109807A TW109128615A TW109128615A TW202109807A TW 202109807 A TW202109807 A TW 202109807A TW 109128615 A TW109128615 A TW 109128615A TW 109128615 A TW109128615 A TW 109128615A TW 202109807 A TW202109807 A TW 202109807A
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Taiwan
Prior art keywords
conductive
solder
conductive pillar
side wall
electronic device
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TW109128615A
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English (en)
Inventor
朱強瑞
蕭景文
劉浩君
鄭明達
吳永華
張道生
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台灣積體電路製造股份有限公司
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Publication of TW202109807A publication Critical patent/TW202109807A/zh

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    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
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Abstract

提供了電子裝置、半導體封裝及其形成方法。本發明實施例的一種電子裝置包括基底、導電接墊、導電柱以及焊料區。所述基底具有表面。所述導電接墊設置在所述基底的所述表面上。所述導電柱設置在所述導電接墊上並電連接到所述導電接墊，其中所述導電柱的頂表面相對於所述基底的所述表面傾斜。所述焊料區設置在所述導電柱的所述頂表面上。

Description

電子裝置
本發明實施例是有關於一種電子裝置、半導體封裝及其形成方法。
近年來，由於各種電子元件（例如，電晶體、二極體、電阻器、電容器等）的集成密度持續提高，半導體行業已經歷快速成長。大多數情況下，集成密度的此種提高來自最小特徵大小（minimum feature size）的連續減小，這使得更多元件能夠集成到給定區域中。
與先前的封裝相比，這些較小的電子元件需要佔據較少面積的較小的封裝。半導體封裝的類型的實例包括四方扁平封裝（quad flat pack，QFP）、引腳格陣列（pin grid array，PGA）、球格陣列（ball grid array，BGA）、倒裝晶片（flip chip，FC）、三維積體電路（three-dimensional integrated circuit，3DIC）、晶圓級封裝（wafer level package，WLP）以及疊層封裝（package on package，PoP）裝置。一些3DIC是通過將晶片放置在半導體晶圓級上的晶片之上製備而成。3DIC提供提高的集成密度及其他優點，例如更快的速度及更高的頻寬，這是因為堆疊的晶片之間的內連線的長度減小。然而，存在許多與3DIC相關的挑戰。
本發明實施例的一種電子裝置包括基底、導電接墊、導電柱以及焊料區。所述基底具有表面。所述導電接墊設置在所述基底的所述表面上。所述導電柱設置在所述導電接墊上並電連接到所述導電接墊，其中所述導電柱的頂表面相對於所述基底的所述表面傾斜。所述焊料區設置在所述導電柱的所述頂表面上。
本發明實施例的一種半導體封裝包括第一電子裝置、第二電子裝置以及多個焊料區。所述第一電子裝置包括多個導電柱，且所述導電柱分別包括傾斜的頂表面。所述第二電子裝置包括多個導電接墊。所述焊料區設置在所述導電柱與所述導電接墊之間以結合所述第一電子裝置及所述第二電子裝置，其中所述焊料區中相鄰的焊料區彼此分離。
本發明實施例的一種形成半導體封裝的方法。提供第一電子裝置，其中所述第一電子裝置包括多個導電柱及多個焊料區，所述多個導電柱具有傾斜的頂表面，所述多個焊料區位於所述傾斜的頂表面上。提供第二電子裝置，其中所述第二電子裝置包括多個導電接墊。通過所述焊料區將所述第一電子裝置結合到所述第二電子裝置上，其中所述焊料區在結合之後彼此分離。
以下公開內容提供用於實施所提供主題的不同特徵的許多不同的實施例或實例。以下闡述元件及排列的具體實例以簡化本公開。當然，這些僅為實例而非旨在進行限制。舉例來說，在以下說明中，在第二特徵之上或第二特徵上形成第一特徵可包括其中第一特徵與第二特徵被形成為直接接觸的實施例，且也可包括其中第一特徵與第二特徵之間可形成附加特徵從而使得第一特徵與第二特徵可不直接接觸的實施例。另外，本公開可在各種實例中重複參考編號和/或字母。此種重複使用是為了簡明及清晰起見，且自身並不表示所討論的各種實施例和/或配置之間的關係。
此外，為易於說明，本文中可能使用例如“在、、、之下（beneath）”、“在、、、下方（below）”、“下部的（lower）”、“在、、、之上（above）”、“上部的（upper）”等空間相對性用語來闡述圖中所示一個元件或特徵與另一（其他）元件或特徵的關係。除了圖中所繪示的取向以外，所述空間相對性用語還旨在囊括裝置在使用或操作中的不同取向。設備可以其他方式取向（旋轉90度或處於其他取向），且本文所用的空間相對性描述語可同樣相應地作出解釋。
另外，為易於說明，本文中可能使用例如“第一”、“第二”、“第三”、“第四”等用語來闡述圖中所示類似或不同的元件或特徵，且所述用語可根據說明的存在或上下文的順序互換地使用。
也可包括其他特徵及製程。舉例來說，可包括測試結構以說明對三維（three dimensional，3D）封裝或3DIC裝置進行驗證測試。所述測試結構可例如包括在重佈線層中或在基底上形成的測試接墊（test pad），以便能夠對3D封裝或3DIC進行測試、對探針和/或探針卡（probe card）進行使用等。可對中間結構以及最終結構執行驗證測試。另外，可將本文中所公開的結構及方法與包括對已知良好晶粒進行中間驗證的測試方法結合使用，以提高良率並降低成本。
圖1A到1E示出根據一些實施例的形成電子裝置的方法的剖視圖。
參照圖1A，提供具有多個導電接墊110的基底102。在一些實施例中，基底102可以是半導體基底。半導體基底包含元素半導體（例如，矽或鍺）和/或化合物半導體（例如，矽鍺、碳化矽、砷化鎵、砷化銦、氮化鎵或磷化銦）。在一些實施例中，基底102包含含矽材料。舉例來說，基底102是絕緣體上矽（silicon-on-insulator，SOI）基底或矽基底。在各種實施例中，基底102可採用平面基底、具有多個鰭的基底、奈米線的形式、或所屬領域中的普通技術人員已知的其他形式。根據設計的要求而定，基底102可以是P型基底或N型基底且可在其中具有摻雜區。可針對N型裝置或P型裝置配置摻雜區。在一些實施例中，基底102中可根據製程要求而具有基底穿孔。
基底102包括界定至少一個主動區域的隔離結構，且在所述主動區域上/中設置有至少一個裝置104。裝置104包括一個或多個功能裝置。在一些實施例中，所述功能裝置包括主動元件、被動元件或其組合。在一些實施例中，所述功能裝置可包括積體電路裝置。所述功能裝置例如為電晶體、電容器、電阻器、二極體、光電二極體、熔絲裝置和/或其他類似裝置。在一些實施例中，裝置104包括閘極介電層、閘極電極、源極區/汲極區、間隔件等。
在一些實施例中，在基底102的一側（例如，前側）之上設置有內連結構106。具體來說，內連結構106設置在裝置104之上且電連接到裝置104。在一些實施例中，內連結構106包括至少一個絕緣層以及多個金屬特徵。金屬特徵設置在絕緣層中且彼此電連接。在一些實施例中，絕緣層包括位於基底102上的層間介電（inter-layer dielectric，ILD）層、以及位於所述層間介電層之上的至少一個金屬間介電（inter-metal dielectric，IMD）層。在一些實施例中，絕緣層包含氧化矽、氮氧化矽、氮化矽、苯並環丁烯（benzocyclobutene，BCB）聚合物、聚醯亞胺（polyimide，PI）、聚苯並惡唑（polybenzoxazole，PBO）或其組合，且由例如旋轉塗布、化學氣相沉積（chemical vapor deposition，CVD）等合適的製程形成。絕緣層可以是單層或多層結構。在一些實施例中，金屬特徵包括金屬通孔及金屬線。金屬通孔形成在兩條金屬線之間並與所述兩條金屬線接觸。金屬特徵可包含鎢（W）、銅（Cu）、銅合金、鋁（Al）、鋁合金或其組合。在一些實施例中，阻擋層可設置在每個金屬特徵與絕緣層之間，以防止金屬特徵的材料遷移到位於下方的裝置104。阻擋層可包含鉭（Ta）、氮化鉭（TaN）、鈦（Ti）、氮化鈦（TiN）、鈷鎢（CoW）或其組合。在一些實施例中，內連結構106是由雙鑲嵌製程形成的。在替代實施例中，內連結構106是由多個單鑲嵌製程形成的。在又一些替代實施例中，內連結構106是由電鍍製程形成的。
在一些實施例中，導電接墊110形成在基底102之上。在一些實施例中，導電接墊110形成在內連結構106的絕緣層之上。此外，導電接墊110可電連接到由內連結構106的絕緣層暴露出的頂部金屬特徵。導電接墊110可包含鎢（W）、銅（Cu）、銅合金、鋁（Al）、鋁合金、鈦（Ti）、鈦合金、鉭（Ta）、鉭合金或其組合。舉例來說，導電接墊110是鋁接墊。在一些實施例中，導電接墊110可通過電鍍製程、化學氣相沉積（CVD）製程、原子層沉積（atomic layer deposition，ALD）製程、物理氣相沉積（physical vapor deposition，PVD）製程或其他合適的製程形成。
在一些實施例中，在基底102之上形成第一鈍化層112。第一鈍化層112部分覆蓋並部分暴露出導電接墊110。舉例來說，第一鈍化層112的材料形成在導電接墊110之上，且然後被圖案化以形成多個第一開口112a，以分別暴露出導電接墊110的頂表面。在一些實施例中，第一鈍化層112包含氧化矽、氮氧化矽、氮化矽、其組合等。在一些替代實施例中，第一鈍化層112包含聚合物材料，例如聚苯並惡唑（PBO）、聚醯亞胺、苯並環丁烯（BCB）、其組合等。
在一些實施例中，在第一鈍化層112之上形成第二鈍化層114。第二鈍化層114覆蓋第一鈍化層112的頂表面、第一開口112a的側壁及導電接墊110的頂表面。此外，第二鈍化層114分別部分暴露出導電接墊110的頂表面。舉例來說，第二鈍化層114的材料形成在第一鈍化層112及導電接墊110之上，且然後被圖案化以形成第二開口114a，以分別暴露出導電接墊110的頂表面。第二開口114a的直徑小於第一開口112a的直徑，並且第二開口114a設置在第一開口112a中。第二鈍化層114的材料可不同於第一鈍化層112的材料。在一些實施例中，第二鈍化層114包含聚合物材料，例如聚苯並惡唑（PBO）、聚醯亞胺、苯並環丁烯（BCB）、其組合等。
參照圖1B，在導電接墊110及鈍化層112之上形成凸塊下金屬（under bump metallurgy，UBM）層116。在一些實施例中，UBM層116毯覆並共形地形成在鈍化層114及導電接墊110之上。舉例來說，在鈍化層114的頂表面、開口114a的側壁及導電接墊110的被暴露出的頂表面上形成UBM層116。UBM層116可包括擴散阻擋層及晶種層。擴散阻擋層可由氮化鉭、氮化鈦、鉭、鈦等形成。在一些實施例中，擴散阻擋層可通過物理氣相沉積（PVD）製程、濺射製程等形成。晶種層可包含銅（Cu）或銅合金，所述銅合金包含銀、鉻、鎳、錫、金及其組合。舉例來說，UBM層116包括由Ti形成的擴散阻擋層及由Cu形成的晶種層。然而，本公開不限於此。
然後，在UBM層116之上形成圖案化罩幕M，並對其進行圖案化以形成多個開口OP。在一些實施例中，開口OP相應地設置在開口114a之上。在一些實施例中，開口OP的直徑大於或等於開口114a的直徑。在一些實施例中，開口OP的大小在約5 μm到約100 μm之間。在一些實施例中，圖案化罩幕M可以是圖案化光阻罩幕、圖案化硬罩幕等。
參照圖1C，在圖案化罩幕M的開口OP中形成多個導電柱（或杆）120。在一些實施例中，導電柱120部分填充圖案化罩幕M的開口OP以接觸UBM層116。舉例來說，導電柱120的最大高度H1（如圖1D所示）小於開口OP的深度（例如，圖案化罩幕M的高度H）。在一些實施例中，導電柱120形成有傾斜的頂表面122。導電柱120可通過電鍍製程、無電鍍製程等形成。導電柱120可包含鎢（W）、銅（Cu）、銅合金、鋁（Al）、鋁合金、鈦（Ti）、鈦合金、鉭（Ta）、鉭合金等或其組合。
在實施例中，通過電鍍製程形成導電柱120，並且通過控制製程參數中的至少一者來產生傾斜的頂表面122，所述製程參數例如是電鍍液的組成、電鍍液的濃度及電鍍速率。在一些實施例中，電鍍液由CuSO4 、H2 SO4 及HCl形成。在一些實施例中，CuSO4 的濃度為185 g/L到215 g/L，H2 SO4 的濃度為85 g/L到115 g/L，且鹽酸的濃度為41 ppm到69 ppm。在一些實施例中，電鍍液也被稱為原生補充溶液（virgin make-up solution，VMS）。在一些實施例中，電鍍液還包括用於方案控制（protocol control）的添加劑。添加劑可以是硫酸、五水合硫酸銅、甲磺酸或其組合，且其濃度可在0.1%到0.6%的範圍內。舉例來說，硫酸的濃度為0.4%到0.6%，且甲磺酸的濃度為0.1%到0.3%。在一些實施例中，電鍍速率在約0.5 μm/min到約4 μm/min之間。然而，本公開不限於此。
參照圖1D，移除圖案化罩幕M以暴露出UBM層116的一部分。在一些實施例中，通過剝離製程移除圖案化罩幕M。剝離製程可包括O2 等離子體灰化製程、濕法蝕刻製程或在例如硫酸（H2 SO4 ）溶液等化學溶液中的濕法浸漬（wet dip）。在移除圖案化罩幕M之後，UBM層116的一些部分被導電柱120覆蓋，而UBM層116的其他部分被暴露出。然後，移除UBM層116的被暴露出的部分。在一些實施例中，可通過濕法蝕刻製程（例如，在具有2%的氫氟（HF）酸的磷酸（H3 PO4 ）及過氧化氫（H2 O2 ）的化學溶液中的濕法浸漬，其被稱為DPP）來移除被暴露出的UBM層116。
如圖1D所示，導電柱120的一部分設置在第二鈍化層114中，且導電柱120的一部分從第二鈍化層114突出。導電柱120形成在基底102的表面102s上。導電柱120包括第一側壁124a及與第一側壁124a相對的第二側壁124b，並且第二側壁124b的高度H2小於第一側壁124a的高度H1。在一些實施例中，舉例來說，第二側壁124b的高度H2對第一側壁124a的高度H1的比小於0.9。導電柱120的高度H1（例如，最大高度）可大於30 μm。在一些實施例中，高度H1可大於40 μm。在一些替代實施例中，高度H1可在40 μm與50 μm或40 μm與70 μm的範圍內。然而，本公開不限於此。換句話說，高度H1可能更大或更小。在一些實施例中，導電柱120設置在UBM層116上，並且導電柱120的第一側壁124a及第二側壁124b實質上與UBM層116的相對側壁齊平。傾斜的頂表面122形成在第一側壁124a與第二側壁124b之間，並且相對於基底102的表面102s傾斜。舉例來說，傾斜的頂表面122連續形成在第一側壁124a與第二側壁124b之間。傾斜的頂表面122分別實體連接到第一側壁124a及第二側壁124b。在一些實施例中，在傾斜的頂表面122與水平線HL之間形成夾角θ，且夾角θ在1度到15度的範圍內。舉例來說，當夾角θ小於1度時，可能不會形成傾斜的頂表面，而當夾角θ大於15度時，由於導電柱的短邊中的充分金屬間化合物，應力將會較高。在一些實施例中，水平線HL實質上平行於基底102的表面102s（或第二鈍化層114的表面114s），並且垂直於導電柱120的高度方向。舉例來說，水平線HL垂直於第一側壁124a和/或第二側壁124b。
在一些實施例中，如圖1D所示，第一側壁124a（例如，具有最大高度的側壁）設置在導電柱120的相同側。類似地，第二側壁124b（例如，具有最小高度的側壁）設置在導電柱120的另一相同側。舉例來說，第一側壁124a位於導電柱120的右側，且第二側壁124b位於導電柱120的左側。
圖2A及圖2B分別示出圖1D的示意性俯視圖。舉例來說，圖1D示出沿圖2A的線I-I’截取及沿圖2B的線II-II’截取的導電柱的剖視圖。在一些實施例中，如圖2A所示，導電柱120可排列成陣列，即，導電柱120沿行方向DR 排列成多行R1、R2，且沿列方向Dc 排列成多列C1、C2。在一些實施例中，不同行中的導電柱120沿著列方向Dc 彼此對齊，並且不同列中的導電柱120沿著行方向DR 彼此對齊。舉例來說，第一行R1中的導電柱120沿著行方向DR 分別與鄰近第一行R1的第二行R2中的導電柱120對齊。在一些實施例中，如圖1D及圖2A所示，舉例來說，導電柱120之間的距離d（例如，水平距離）在20 μm到50 μm的範圍內。然而，本公開不限於此。在一些替代實施例中，如圖2B所示，導電柱120可佈置得更密集。在此類實施例中，沿著列方向Dc ，奇數行中的導電柱120彼此對齊，且偶數行中的導電柱120彼此對齊，並且奇數行中的導電柱120與偶數行中的導電柱120交替設置。舉例來說，沿著行方向DR ，第一行R1中的導電柱120分別與第三行R3中的導電柱120對齊，第二行R2中的導電柱120分別與第四行R4中的導電柱120對齊，並且第一行R1中的導電柱120與第二行R2中的導電柱120交替設置。
參照圖1E，將多個焊料區130設置在導電柱120的傾斜的頂表面122上。在一些實施例中，在形成焊料區130之後，形成電子裝置100。在一些實施例中，焊料區130由錫（Sn）、SnAg、SnPb、SnAgCu、SnAgZn、SnZn、SnBiIn、SnIn、SnAu、SnPb、SnCu、SnZnIn、SnAgSb等或其組合製成。在一些實施例中，焊料區130通過電鍍製程、物理氣相沉積（PVD）製程、化學氣相沉積（CVD）製程等形成。
焊料區130用於將電子裝置100結合到外部特徵。焊料區130及導電柱120被稱為形成在導電接墊110之上的凸塊結構。在一些實施例中，舉例來說，焊料區130具有圓形（或球形）頂表面132。在一些實施例中，焊料區130具有從頂表面132的頂點到導電柱120的頂表面122測量的平均高度。舉例來說，平均高度在20 μm與30 μm的範圍中。如圖1E所示，焊料區130形成在導電柱120上，而不潤濕導電柱120的第一側壁124a及第二側壁124b。舉例來說，焊料區130的邊緣實質上與導電柱120的第一側壁124a及第二側壁124b齊平。然而，本公開不限於此。
在一些替代實施例中，在導電柱120與焊料區130之間形成覆蓋層（圖中未示出）。覆蓋層可充當阻擋層，以防止導電柱120中的金屬（例如，銅）擴散到焊料區130中。防止金屬擴散增加了封裝的可靠性及結合強度。覆蓋層可包含鎳、錫、錫鉛（SnPb）、金（Au）、銀、鈀（Pd）、銦（In）、鎳-鈀-金（NiPdAu）、鎳-金（NiAu）、其他類似材料或合金。
在一些實施例中，電子裝置100是其中包括例如電晶體等主動裝置的裝置晶粒（例如，積體電路晶粒）。然而，本公開不限於此。在一些替代實施例中，電子裝置100可以是其中不具有主動裝置的中介層（interposer）、封裝基底、印刷電路板、高密度內連線等。
圖3A及圖3B示出根據一些實施例的形成半導體封裝的方法的剖視圖。
參照圖3A，提供第一電子裝置E1及第二電子裝置E2。第一電子裝置E1實質上與圖1E的電子裝置100相同或類似。在一些實施例中，第二電子裝置E2可以是封裝基底、裝置晶粒、中介層等。在一些實施例中，第二電子裝置E2可包括基底202、內連結構206及多個導電接墊210。在一些實施例中，半導體基底202包含元素半導體（例如，矽或鍺）和/或化合物半導體（例如，矽鍺、碳化矽、砷化鎵、砷化銦、氮化鎵或磷化銦）。在一些實施例中，半導體基底202包含含矽材料。舉例來說，半導體基底202是絕緣體上矽（SOI）基底或矽基底。在各種實施例中，半導體基底202可採用平面基底、具有多個鰭的基底、奈米線的形式或所屬領域中的普通技術人員已知的其他形式。根據設計的要求而定，半導體基底202可以是P型基底或N型基底且可在其中具有摻雜區。可針對N型裝置或P型裝置配置摻雜區。在一些實施例中，半導體基底202中可根據製程要求而具有基底穿孔。
在一些實施例中，內連結構206設置在半導體基底202的一側（例如，前側）之上。在一些實施例中，內連結構206包括至少一個絕緣層以及多個金屬特徵。金屬特徵設置在絕緣層中且彼此電連接。在一些實施例中，絕緣層包括位於半導體基底202上的層間介電（ILD）層以及位於所述層間介電層之上的至少一個金屬間介電（IMD）層。在一些實施例中，絕緣層包含氧化矽、氮氧化矽、氮化矽、苯並環丁烯（BCB）聚合物、聚醯亞胺（PI）、聚苯並惡唑（PBO）或其組合，且由例如旋轉塗布、化學氣相沉積（CVD）等合適的製程形成。絕緣層可以是單層或多層結構。在一些實施例中，金屬特徵包括金屬通孔及金屬線。金屬通孔形成在兩條金屬線之間並與所述兩條金屬線接觸。金屬特徵可包含鎢（W）、銅（Cu）、銅合金、鋁（Al）、鋁合金或其組合。在一些實施例中，阻擋層可設置在每個金屬特徵與絕緣層之間，以防止金屬特徵的材料遷移到位於下方的裝置204。阻擋層可包含鉭（Ta）、氮化鉭（TaN）、鈦（Ti）、氮化鈦（TiN）、鈷鎢（CoW）或其組合。在一些實施例中，內連結構206是由雙鑲嵌製程形成的。在替代實施例中，內連結構206是由多個單鑲嵌製程形成的。在又一些替代實施例中，內連結構206是由電鍍製程形成的。
導電接墊210形成在半導體基底202之上。在一些實施例中，導電接墊210形成在內連結構206的絕緣層之上。此外，導電接墊210可電連接到由內連結構206的絕緣層暴露出的頂部金屬特徵。導電接墊210可包含鎢（W）、銅（Cu）、銅合金、鋁（Al）、鋁合金、鈦（Ti）、鈦合金、鉭（Ta）、鉭合金等或其組合。舉例來說，導電接墊210是鋁接墊。在一些實施例中，導電接墊210可通過電鍍製程或其他合適的製程形成。
在一些實施例中，多個焊料區230分別設置在導電接墊210上。在一些實施例中，焊料區230由錫（Sn）、SnAg、SnPb、SnAgCu、SnAgZn、SnZn、SnBiIn、SnIn、SnAu、SnPb、SnCu、SnZnIn、SnAgSb等或其組合製成。在一些實施例中，焊料區230通過例如電鍍製程、物理氣相沉積（PVD）製程、化學氣相沉積（CVD）製程等沉積製程形成。
參照圖3B，將第一電子裝置E1與第二電子裝置E2結合以形成半導體封裝PK。在一些實施例中，可通過倒裝晶片結合來結合第一電子裝置E1與第二電子裝置E2。舉例來說，第一電子裝置E1的焊料區130與第二電子裝置E2的焊料區230分別對齊，且然後執行回焊製程，以便將第一電子裝置E1的焊料區130與第二電子裝置E2的焊料區230結合在一起。在一些實施例中，在第一電子裝置E1的焊料區130與第二電子裝置E2的焊料區230之間形成焊點（圖中未示出）。此外，由於相互擴散，在焊料區130與導電柱120之間的介面處和/或焊料區230與導電接墊210之間的介面處可形成金屬間化合物（inter-metallic compound，IMC）（圖中未示出）。在一些實施例中，在焊料區130和/或焊料區230的熔點溫度下執行回焊製程。在一些實施例中，回焊製程在約100攝氏度到約300攝氏度的範圍內的溫度下執行。當溫度在上述範圍內時，結合品質及結合良率提高。然而，本公開不限於此。
如圖3B所示，在結合步驟期間，焊料區130可被導電柱120擠壓到一邊以形成焊料區134a、134b。在一些實施例中，導電柱120的側壁124a、124b的一些部分分別被焊料區134a、134b覆蓋，此也被稱為側壁潤濕。在一些實施例中，導電柱120的側壁124a、124b具有不同的高度H1、H2，且因此焊料區130易於被朝向具有較小高度的側壁124b擠壓。也就是說，大部分焊料區130可實質上沿著相同的方向D被擠壓。方向D是從側壁124a（例如，長側壁）到側壁124b（例如，短側壁）的方向。如圖3B所示，對於每個導電柱120，大部分焊料區130被擠壓到導電柱120的側壁124b上。換句話說，側壁124a上的焊料區134a的量小於側壁124b上的焊料區134b的量。在一些實施例中，側壁124a上的焊料區134a的寬度W1（例如，從焊料區134a的外表面到側壁124a測量的最大水平寬度）小於側壁124b上的焊料區134b的寬度W2（例如，從焊料區134b的外表面到側壁124b測量的最大水平寬度）。在一些實施例中，不同導電柱120上的焊料區134a的寬度W1可實質上相同或不同，並且不同導電柱120上的焊料區134b的寬度W2可實質上相同或不同。在一些實施例中，寬度W1與寬度W2的總和小於相鄰導電柱120之間的距離d。因此，在兩個相鄰的導電柱120之間，一個導電柱120的側壁124a上的焊料區134a不容易與另一導電柱120的側壁124b上的焊料區134b橋接。因此，相鄰導電柱120上的焊料區130彼此分離。
在一些實施例中，舉例來說，焊料區134a與第一電子裝置E1的表面（例如，第二鈍化層114的表面114s）之間的距離d1大於焊料區134b與第一電子裝置E1的表面（例如，第二鈍化層114的表面114s）之間的距離d2。然而，本公開不限於此。在一些替代實施例中，距離d1可實質上相同於或小於距離d2。此外，在一些實施例中，導電柱120的側壁124a、124b上的焊料區134a、134b被示為焊料區130的一些部分。然而，本公開不限於此。在一些替代實施例中，導電柱120的側壁124a、124b上的焊料區134a、134b可由焊料區130及焊料區230兩者形成。
圖4示出根據一些實施例的半導體封裝的剖視圖。圖4的半導體封裝PK1類似於圖3B的半導體封裝PK，且以下描述主要區別。參照圖4，在一些實施例中，大部分焊料區130可被擠壓到導電柱120的側壁124b上。也就是說，大部分焊料區130可實質上沿著相同的方向D被擠壓。在一些實施例中，在導電柱120的側壁124a上實質上沒有焊料，換句話說，在導電柱120的側壁124a上不會發生焊料潤濕。此外，焊料區134b的寬度W2小於相鄰導電柱120之間的距離d。也就是說，導電柱120上的焊料區134b不與和其相鄰的另一導電柱120接觸。因此，可防止相鄰導電柱上的焊料區之間的焊料橋接。
圖5示出根據一些實施例的半導體封裝的剖視圖。圖5的半導體封裝PK2類似於圖3B的半導體封裝PK，且以下描述主要區別。參照圖5，在一些實施例中，導電柱120的頂表面122具有傾斜部分122b及平坦部分122a。在一些實施例中，平坦部分122a實體連接到第一側壁124a，並且平坦部分122a實質上平行於水平線HL。水平線HL實質上平行於基底102的表面102s（或第二鈍化層114的表面114s），並且垂直於導電柱120的高度方向。舉例來說，水平線HL垂直於第一側壁124a和/或第二側壁124b。平坦部分122a實體連接到第二側壁124b，並且在傾斜的頂表面122與水平線HL之間形成夾角θ。舉例來說，夾角θ可在1度到15度的範圍內。在一些實施例中，傾斜部分122b對頂表面122（例如，傾斜部分122b的寬度對頂表面122的寬度）的比在50%到100%的範圍內。在一些實施例中，平坦部分122a的寬度可在0 μm到30 μm的範圍內。在一些實施例中，導電柱120的頂表面122具有傾斜部分122b，且因此焊料區130易於被朝向具有較小高度的側壁124b擠壓。也就是說，大部分焊料區130可實質上沿著相同的方向D被擠壓。因此，在兩個相鄰的導電柱120之間，一個導電柱120的側壁124a上的焊料區134a不容易與另一導電柱120的側壁124b上的焊料區134b橋接。因此，可防止相鄰導電柱上的焊料區之間的焊料橋接。
在一些實施例中，由於電子裝置的導電柱具有傾斜的頂表面，因此導電柱上的焊料易於被擠壓到具有較小高度的側壁上。因此，防止了相鄰導電柱上的焊料區之間的焊料橋接。因此，在一些實施例中，通過由焊料區將電子裝置與另一電子裝置結合而形成的半導體封裝可具有更好的良率及改善的性能。
根據一些實施例，一種電子裝置包括基底、導電接墊、導電柱以及焊料區。所述基底具有表面。所述導電接墊設置在所述基底的所述表面上。所述導電柱設置在所述導電接墊上並電連接到所述導電接墊，其中所述導電柱的頂表面相對於所述基底的所述表面傾斜。所述焊料區設置在所述導電柱的所述頂表面上。
根據一些實施例，在所述導電柱的所述頂表面與所述基底的所述表面之間形成的夾角在1度至15度的範圍內。
根據一些實施例，所述導電柱的所述頂表面形成在所述導電柱的第一側壁與和所述第一側壁相對的第二側壁之間，並且所述第二側壁的高度小於所述第一側壁的高度。
根據一些實施例，所述第二側壁的所述高度對所述第一側壁的所述高度的比小於0.9。
根據一些實施例，所述導電柱的所述頂表面實體連接到所述第一側壁。
根據一些實施例，所述導電柱的所述頂表面包括實體連接到所述第一側壁的平坦部分以及實體連接到所述平坦部分及所述第二側壁的傾斜部分。
根據一些實施例，所述焊料區具有圓形頂表面。
根據一些實施例，一種半導體封裝包括第一電子裝置、第二電子裝置以及多個焊料區。所述第一電子裝置包括多個導電柱，且所述導電柱分別包括傾斜的頂表面。所述第二電子裝置包括多個導電接墊。所述焊料區設置在所述導電柱與所述導電接墊之間以結合所述第一電子裝置及所述第二電子裝置，其中所述焊料區中相鄰的焊料區彼此分離。
根據一些實施例，所述焊料區分別延伸到所述導電柱的側壁上。
根據一些實施例，在所述傾斜的頂表面與水平線之間形成的夾角在1度到15度的範圍內。
根據一些實施例，所述導電柱分別包括第一側壁及第二側壁，所述第二側壁與所述第一側壁相對且高度小於所述第一側壁，並且所述傾斜的頂表面形成在所述第一側壁與所述第二側壁之間。
根據一些實施例，所述第一側壁設置在所述導電柱的相同側，並且所述第二側壁設置在所述導電柱的另一相同側。
根據一些實施例，所述焊料區的延伸到所述導電柱的所述第二側壁上的一部分的寬度大於所述焊料區的延伸到所述導電柱的所述第一側壁上的一部分的寬度。
根據一些實施例，所述導電柱包括第一導電柱及第二導電柱，所述焊料區包括位於所述第一導電柱上的第一焊料區及位於所述第二導電柱上的第二焊料區，延伸到所述第一導電柱的第一側壁上的所述第一焊料區具有第一寬度，延伸到所述第一導電柱的第二側壁上的所述第二焊料區具有第二寬度，並且所述第一寬度與所述第二寬度的總和小於所述第一側壁與所述第二側壁之間的距離。
根據一些實施例，提供了一種形成半導體封裝的方法。提供第一電子裝置，其中所述第一電子裝置包括多個導電柱及多個焊料區，所述多個導電柱具有傾斜的頂表面，所述多個焊料區位於所述傾斜的頂表面上。提供第二電子裝置，其中所述第二電子裝置包括多個導電接墊。通過所述焊料區將所述第一電子裝置結合到所述第二電子裝置上，其中所述焊料區在結合之後彼此分離。
根據一些實施例，所述傾斜的頂表面分別形成在所述導電柱的第一側壁與和所述第一側壁相對的第二側壁之間，並且所述第二側壁的高度小於所述第一側壁的高度。
根據一些實施例，所述焊料區的邊緣在結合之前實質上與所述導電柱的所述第一側壁及所述第二側壁齊平。
根據一些實施例，所述焊料區在結合之後至少分別延伸到所述導電柱的所述第二側壁上。
根據一些實施例，在結合之後，所述焊料區的延伸到所述第一側壁上的一部分具有第一寬度，所述焊料區的延伸到所述第二側壁上的一部分具有第二寬度，並且所述第一寬度小於所述第二寬度。
根據一些實施例，所述導電柱包括第一導電柱及第二導電柱，所述焊料區包括位於所述第一導電柱上的第一焊料區及位於所述第二導電柱上的第二焊料區，在結合之後，延伸到所述第一導電柱的第一側壁上的所述第一焊料區具有第一寬度，延伸到所述第二導電柱的第二側壁上的所述第二焊料區具有第二寬度，並且所述第一寬度與所述第二寬度的總和小於所述第一側壁與所述第二側壁之間的距離。
以上概述了若干實施例的特徵，以使所屬領域中的技術人員可更好地理解本公開的各個方面。所屬領域中的技術人員應理解，其可容易地使用本公開作為設計或修改其他製程及結構的基礎來施行與本文中所介紹的實施例相同的目的和/或實現與本文中所介紹的實施例相同的優點。所屬領域中的技術人員還應認識到，這些等效構造並不背離本公開的精神及範圍，而且他們可在不背離本公開的精神及範圍的條件下對其作出各種改變、替代及變更。
100:電子裝置 102:基底 102s:表面 104:裝置 106:內連結構 110:導電接墊 112:鈍化層 112a:開口 114:鈍化層 114a:開口 114s:表面 116:凸塊下金屬（UBM）層 120:導電柱 122:頂表面 122a:平坦部分 122b:傾斜部分 124a:側壁 124b:側壁 130:焊料區 132:頂表面 134a、134b:焊料區 202:基底 206:內連結構 210:導電接墊 230:焊料區 d、d1、d2:距離 C1、C2:列 D:方向 Dc:列方向 DR:行方向 E1:電子裝置 E2:電子裝置 H:高度 H1:高度 H2:高度 HL:水平線 I-I’、II-II’:線 M:圖案化罩幕 OP:開口 PK、PK1、PK2:半導體封裝 R1、R2、R3、R4:行 W1、W2:寬度 θ:夾角
結合附圖閱讀以下詳細說明，會最好地理解本公開的各個方面。應注意，根據本行業中的標準慣例，各種特徵並非按比例繪製。事實上，為論述清晰起見，可任意增大或減小各種特徵的尺寸。 圖1A到1E示出根據一些實施例的形成電子裝置的方法的剖視圖。 圖2A及圖2B分別示出圖1D的示意性俯視圖。 圖3A及3B示出根據一些實施例的形成半導體封裝的方法的剖視圖。 圖4示出根據一些實施例的半導體封裝的剖視圖。 圖5示出根據一些實施例的半導體封裝的剖視圖。
102:基底
104:裝置
106:內連結構
110:導電接墊
112:鈍化層
114:鈍化層
116:凸塊下金屬(UBM)層
120:導電柱
122:頂表面
124a:側壁
124b:側壁
130:焊料區
134a、134b:焊料區
202:基底
206:內連結構
210:導電接墊
230:焊料區
d、d1、d2:距離
D:方向
E1:電子裝置
E2:電子裝置
HL:水平線
PK:半導體封裝
W1、W2:寬度
θ:夾角

Claims (1)

  1. 一種電子裝置，包括： 基底，具有表面； 導電接墊，位於所述基底的所述表面上； 導電柱，設置在所述導電接墊上並電連接到所述導電接墊，其中所述導電柱的頂表面相對於所述基底的所述表面傾斜；以及 焊料區，設置在所述導電柱的所述頂表面上。
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