TWI429047B - 積體電路結構 - Google Patents

積體電路結構 Download PDF

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Publication number
TWI429047B
TWI429047B TW099129825A TW99129825A TWI429047B TW I429047 B TWI429047 B TW I429047B TW 099129825 A TW099129825 A TW 099129825A TW 99129825 A TW99129825 A TW 99129825A TW I429047 B TWI429047 B TW I429047B
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Taiwan
Prior art keywords
layer
copper
semiconductor substrate
integrated circuit
metal
Prior art date
Application number
TW099129825A
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English (en)
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TW201121022A (en
Inventor
Hon Lin Huang
Ching Wen Hsiao
Kuo Ching Hsu
Chen Shien Chen
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Taiwan Semiconductor Mfg
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Application filed by Taiwan Semiconductor Mfg filed Critical Taiwan Semiconductor Mfg
Publication of TW201121022A publication Critical patent/TW201121022A/zh
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Publication of TWI429047B publication Critical patent/TWI429047B/zh

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Description

積體電路結構
本發明係有關於一種積體電路結構，特別是有關於一種積體電路結構內的內連線(interconnect)結構。
由於各個電子部件(即，電晶體、二極體、電阻、電容等等)的集積度(integration density)持續不斷的改進，使積體電路製造、半導體業持續的快速成長發展。主要來說，集積度的改進來自於最小特徵尺寸(minimum feature size)不斷縮小而容許更多的部件整合至既有的晶片面積內。
這些集積度的改進實質上是朝二維(two-dimensional,2D)方面的，因為積體部件所佔的體積實際上位於半導體晶圓的表面。儘管微影(lithography)技術的精進為2D積體電路製作帶來相當大的助益，二維空間所能擁有的密度還是有其物理限制。這些限制之一在於製作這些部件所需的最小尺寸。再者，當更多的裝置放入一晶片中，需具有更複雜的電路設計。
另一限制來自於當裝置數量增加時，其間的內連線(interconnection)的數量及長度大幅增加。而當內連線的數量及長度增加時，電路的時間延遲(RC delay)以及電量耗損均會增加。
在解決上述限制的方法之中，通常使用三維積體電路(three-dimensional integrated circuit,3DIC)及疊置晶片。而基底通孔電極(through-substrate-via,TSV)通常用於3DIC及疊置晶片中以連接晶片。在此情形中，基底通孔電極時常用以將晶片上的積體電路連接至晶片的背側。另外，基底通孔電極也提供短接地路徑，使積體電路透過晶片背側(其可覆蓋一接地金屬層)而接地。
本發明一實施例中，一種積體電路構包括：一半導體基底；一基底通孔電極穿過半導體基底；以及一含銅立柱，位於半導體基底上方且電性連接至基底通孔電極。
本發明另一實施例中，一種積體電路構包括：一半導體基底；一基底通孔電極自半導體基底的一前表面延伸至一背表面；一內連線結構，位於半導體基底的前表面，其中內連線結構含銅；以及一含銅立柱，位於半導體基底的前表面上且電性連接至基底通孔電極及內連線結構。
本發明又一實施例中，一種積體電路構包括：一半導體基底；一基底通孔電極自半導體基底的一前表面延伸至一背表面；一含銅立柱，位於半導體基底上方且電性連接至基底通孔電極；以及一導電阻障層，位於含銅立柱上，其中導電阻障層、該含銅立柱及基底通孔電極彼此電性連接。
以下說明本發明實施例之製作與使用。然而，可輕易了解本發明實施例提供許多合適的發明概念而可實施於廣泛的各種特定背景。所揭示的特定實施例僅僅用於說明以特定方法製作及使用本發明，並非用以侷限本發明的範圍。
以下根據一實施例說明一種新的內連線結構及其製造方法並配合圖式說明製造上述實施例的各個階段。全文中各個不同實施例及圖式中，相同的標號係用於表是相同的部件。
請參照第1圖，提供一晶圓2，其包括一基底10。晶圓2具有一前側(面向上)及一背側。基底10為一半導體基底，例如一塊材(bulk)矽基底，然其可包括其他半導體材料，例如第三族、第四族及/或第五族元素。半導體裝置14，例如電晶體，可形成於基底10的前表面/側10a(表面10a在第1圖中為面向上)。內連線結構12係形成於基底上且可連接至半導體裝置14，內連線結構12包括形成於內的金屬線及介層窗(via)(未繪示)。金屬線及介層窗可由銅或銅合金所構成，且可利用習知鑲嵌製程而形成。內連線結構12包括一般熟習的內層介電(inter-layer dielectric,ILD)層及金屬層間(inter-metal dielectric,IMD)層。
基底通孔電極(through-substrate via,TSV)20自基底10的前表面10a延伸於基底10內。在一第一實施例中，基底通孔電極20是使用先鑽孔(via-first)法來製做，且於形成內連線結構12之前完成。因此，基底通孔電極20僅延伸至內層介電(ILD)層(其用於覆蓋主動(active)裝置)而未延伸於內連線結構12的金屬層間(IMD)層內。在另一實施例中，基底通孔電極20係使用後鑽孔(via-last)法來製做，且於形成內連線結構12之後完成。因此，基底通孔電極20貫穿基底10及內連線結構12。隔離層22形成於基底通孔電極20的側壁及底部上且使基底通孔電極20與基底10電性隔離。隔離層22可由一般常用的介電材料所構成，例如氮化矽、氧化矽(如，四乙基矽酸鹽(tetra-ethyl-ortho-silicate,TEOS)氧化物)等等。
鈍化保護層24及26形成於內連線結構12上。在習知技術中，鈍化保護層24及26通常分別稱作鈍化保護層-1及鈍化保護層-2且可由以下材料所構成：氧化矽、氮化矽、未摻雜矽玻璃(un-doped silicate glass,USG)、聚亞醯胺(polyimide)及/或上述材料所組成的多層材料。金屬接墊28形成於鈍化保護層24。金屬接墊28可由鋁所構成，因而也可稱作鋁接墊28，然其也可由其他材料所構成，例如銅、銀、金、鎳、鎢、上述金屬的合金及/或上述金屬所組成的多層材料。金屬接墊28可透過下方的內連線結構12而電性連接至半導體裝置14。開口32形成於鈍化保護層26內，而金屬接墊28經由開口32而露出。
請參照第2圖，形成介電緩衝層30，其可由聚亞醯胺所構成。圖案化介電緩衝層30，以在開口32內形成另一開口，使金屬接墊28經由開口32以及介電緩衝層30內的開口而露出。
請參照第3圖，形成一凸塊底部金屬層(under-bump metallurgy,UBM)34。凸塊底部金屬層34的可用材料包括一擴散阻障層、一晶種(seed)層或其組合。擴散阻障層可包括Ti、TiN、Ta、TaN或其組合。晶種層可包括銅或銅合金。然而，也可包括其他材料，例如，鎳、鈀、銀、金、鋁、上述金屬的組合、及上述金屬所組成的多層材料。在一實施例中，凸塊底部金屬層34利用濺鍍(sputtering)來製做。在其他實施例中，也可利用電鍍(electro plating)來製做。
第4圖係繪示出罩幕層38的製做。在一實施例中，罩幕層38為乾膜，其包括有機材料，例如增層絕緣膜(Ajinimoto buildup film,ABF)。另外，罩幕層38也可由光阻所構成。接著圖案化罩幕層38，以形成開口40，其中金屬接墊28位於開口40下方。
請參照第5圖，開口40內選擇性填入一金屬材料，以在開口40內形成金屬立柱44。在一實施例中，填入的材料包括銅或銅合金，因而金屬立柱44也稱作含銅立柱44，然而也可使用其他金屬，例如鋁、銀、金及其組合。含銅立柱44的厚度可小於60微米(μm)或在30微米至50微米的範圍之間。含銅立柱的邊緣可為垂直的，換句話說，垂直於半導體基底10的上表面。接著，形成導電阻障層46，其可由含鎳層、含銅層、或含錫層所構成。接著形成焊料(solder)層48，其可包括無鉛焊料或共晶(eutectic)焊料。焊料層48的厚度小於15微米。含銅立柱44、導電阻障層46及焊料層48的製造方法包括電化學電鍍(electro-chemical plating,ECP)、無電電鍍(electroless plating)或其他習知沉積方法，諸如濺鍍、印刷及化學氣相沉積(chemical vapor deposition,CVD)。焊料層48的上表面可低於罩幕層38的上表面，使含銅立柱44、導電阻障層46及焊料層48的邊緣垂直對準，且焊料層48的邊緣不會延伸超過含銅立柱44的邊緣。
接著，請參照第6圖，去除罩幕層38。如此一來，位於罩幕層38下方部分的凸塊底部金屬層34會因此露出。請參照第7圖，透過閃蝕(flash etching)去除露出的凸塊底部金屬層34部分。接著進行回流製程(re-flow)，使焊料層48形成圓化的上表面，如第8A圖所示。在一實施例中，如第8C圖所示，一介金屬化合物(intermetallic compound,IMC)層49形成於含銅立柱44與回流後的焊料層48之間，其中導電阻障層46可能會局部或完全耗盡。
第8A圖所示的導電阻障層46及焊料層48可以一金屬表面處理層(metal finish)取代之。請參照第8B圖，在形成罩幕層38之後，形成含銅立柱44。在去除罩幕層38之後，形成金屬表面處理層60。金屬表面處理層60的製造方法包括電化學電鍍(ECP)、無電電鍍等等。在一實施例中，金屬表面處理層60包括由浸漬(immersion)法所形成的錫。在其他實施例中，金屬表面處理層60包括化鎳浸金(electroless nickel immersion gold,ENIG)。又其他實施例中，金屬表面處理層60包括鎳鈀。又其他實施例中，金屬表面處理層60包括化鎳鈀浸金(electroless nickel electroless palladium immersion gold,ENEPIG)。
請參照第9圖，晶圓2經由黏著層52而組裝於承載晶圓50上。承載晶圓50可為一玻璃晶圓。可看到含銅立柱44、導電阻障層46可能會局部或完全耗盡。
第8A圖所示的導電阻障層46、焊料層48及焊料層48的加總厚度僅約在25微米至60微米之間的範圍。此加總厚度是在黏著層52可達到的厚度範圍以內。因此黏著層52可完全填入承載晶圓50與晶圓2之間的間隙而不會產生空孔。如此一來，在後續的背側研磨製程與內連線製造中，黏著層52可提供晶圓2內的結構最大的保護。
在後續製程步驟中，進行基底10的背側10b研磨，並製做背側內連線結構。舉例來說，背側研磨與內連線結構的製做揭示於2008年12月11日所提申的美國共同申請案中(申請號第12/332,934號；發明名稱：Backside Connection to TSVs Having Redistribution Lines、申請號第12/347,742號；發明名稱：Bond Pad Connection to Redistribution Lines Having Tapered Profiles)，其併入此處作為參考。此處不再贅述。在形成背側內連線結構之後，且可能在將晶圓2接合至另一晶圓之後，承載晶圓50可自晶圓2處卸離，接著去除黏著層52。
第10至19B圖繪示出另一實施例，其中形成了後鈍化保護層內連線(post-passivation interconnect,PPI)。請參照第10圖，其繪示出內連線結構12內的金屬線及介層窗。內連線結構可包括頂層介層窗61，其經由介電層而露出。頂層介層窗61可形成於一鈍化保護層內，其可實質相同於第9圖所示的鈍化保護層24及26。接著，請參照第11圖，形成一晶種層62，其可由實質相同於第3圖所示的凸塊底部金屬層34的材料所構成。
請參照第12圖，形成一罩幕層64，例如乾膜或光阻。請參照第13圖，形成後鈍化保護層內連線66及68。後鈍化保護層內連線66可包括一金屬接墊，而後鈍化保護層內連線68可包括一金屬線，用以配送信號。後鈍化保護層內連線66連接至金屬表面處理層60。再者，後鈍化保護層內連線66可由銅所構成，然其可由其他材料所構成或加入這些材料，例如鋁、銀、鎢等等。製造的方法包括電鍍或無電電鍍。
請參照第14圖，去除罩幕層64，接著去除露出的凸塊底部金屬層34(即，晶種層62)。由於凸塊底部金屬層34由實質相同於後鈍化保護層內連線66及68的材料所構成，凸塊底部金屬層34將併入於後鈍化保護層內連線66及68內，因而之後不再繪示出剩餘的凸塊底部金屬層34。
在後續的製程步驟中，如第15至19B圖所示，形成含銅立柱44、導電阻障層46及焊料層48。以下簡單說明其製程，而細節部分則實質相同於第3至8A圖的製程。除非有其他不同之處，否則第15至19B圖中相同於第3至8A圖的部件係使用相同的標號。請參照第15圖，形成介電緩衝層30，其可由聚亞醯胺所構成。在介電緩衝層30內形成開口32併露出後鈍化保護層內連線66。請參照第16圖，形成凸塊底部金屬層34。請參照第17圖，形成罩幕層38。接著形成含銅立柱44、導電阻障層46及焊料層48，如第18圖所示。第19圖繪示出去除罩幕層38及露出部分的凸塊底部金屬層34。第19B圖繪示出另一實施例，其以金屬表面處理層60取代了導電阻障層46及焊料層48。
上述實施例擁有許多的優點。透過形成含銅立柱來取代焊料凸塊，可使含銅立柱的厚度獲得良好的控制且可低於用於將晶圓接合至承載晶圓的黏著層可行的厚度。如此一來，晶圓的內部結構可獲得較佳的保護。再者，含銅立柱與上方的焊料層及金屬表面處理層並未明顯向側邊延伸，因此可將相鄰的含銅立柱之間距輕易控制在低於150微米。相較之下，在現行的積體電路結構中，由於使用焊料凸塊，因此凸塊間距必須大於150微米以避免相鄰的焊料凸塊之間發生短路。
雖然本發明已以較佳實施例揭露如上，然其並非用以限定本發明，任何所屬技術領域中具有通常知識者，在不脫離本發明之精神和範圍內，當可作各種更動、替代與潤飾。然而，很清楚的是在不脫離本發明之精神和範圍內，當可作出各種更動、結構、製程及改變，如請求保護範圍所述。再者，本發明之保護範圍並未侷限於說明書內所述特定實施例中的製程、機器、製造、物質組成、裝置、方法及步驟，任何所屬技術領域中具有通常知識者可從本發明揭示內容中理解現行或未來所發展出的製程、機器、製造、物質組成、裝置、方法及步驟，只要可以在此處所述實施例中實施大體相同功能或獲得大體相同結果皆可使用於本發明中。因此，本發明之保護範圍包括上述製程、機器、製造、物質組成、裝置、方法及步驟。另外，每一申請專利範圍構成個別的實施例，且本發明之保護範圍也包括各個申請專利範圍及實施例的組合。
2．．．晶圓
10．．．基底
10a．．．前表面/側
10b．．．背側
12．．．內連線結構
14．．．半導體裝置
20．．．基底通孔電極
22．．．隔離層
24、26．．．鈍化保護層
28．．．金屬接墊
30．．．介電緩衝層
32、40．．．開口
34．．．凸塊底部金屬層
38、64．．．罩幕層
44．．．金屬立柱/含銅立柱
46．．．導電阻障層
48．．．焊料層
49．．．介金屬化合物層
50．．．承載晶圓
52．．．黏著層
60．．．金屬表面處理層
61．．．頂層介層窗
62．．．晶種層
66、68．．．後鈍化保護層內連線
第1至9圖係繪示出根據一實施例之製造前側內連線結構的各個階段剖面示意圖。
第10至19B圖係繪示出根據另一實施例之製造前側內連線結構的各個階段剖面示意圖，其中形成了後鈍化保護層內連線。
2．．．晶圓
10．．．基底
12．．．內連線結構
14．．．半導體裝置
20．．．基底通孔電極
22．．．隔離層
24、26．．．鈍化保護層
28．．．金屬接墊
30．．．介電緩衝層
34．．．凸塊底部金屬層
44．．．金屬立柱/含銅立柱
46．．．導電阻障層
48．．．焊料層

Claims (10)

  1. 一種積體電路結構，包括：一半導體基底；一基底通孔電極穿過該半導體基底；以及一含銅立柱，位於該半導體基底上方且電性連接至該基底通孔電極。
  2. 如申請專利範圍第1項所述之積體電路結構，更包括：一導電阻障層，位於該含銅立柱上；以及一焊料層，位於該導電阻障層上。
  3. 如申請專利範圍第1項所述之積體電路結構，更包括一金屬層，位於該含銅立柱上，其中該金屬層包括一第一部位於該含銅立柱正上方以及一第二部位於該含銅立柱的一側壁上。
  4. 如申請專利範圍第1項所述之積體電路結構，更包括：一凸塊底部金屬層，形成於該含銅立柱與該半導體基底之間；一金屬接墊，位於該凸塊底部金屬層下方並與其連接；以及一介電緩衝層，位於該金屬接墊上，其中該金屬接墊透過該介電緩衝層內的一導電特徵部件而連接至該凸塊底部金屬層。
  5. 一種積體電路結構，包括：一半導體基底；一基底通孔電極自該半導體基底的一前表面延伸至該半導體基底內；一內連線結構，位於該半導體基底的該前表面，其中該內連線結構含銅；以及一含銅立柱，位於該半導體基底的該前表面上且電性連接至該基底通孔電極及該內連線結構。
  6. 如申請專利範圍第5項所述之積體電路結構，更包括：一含鋁接墊，位於該半導體基底上且電性連接至基底通孔電極；一凸塊底部金屬層，位於該含鋁接墊上且與其電性連接；以及一聚亞醯胺層，位於含鋁接墊上且位於一部分的該凸塊底部金屬層下方，其中該凸塊底部金屬層與包括一延伸部延伸於該聚亞醯胺層內且與該含鋁接墊接觸。
  7. 如申請專利範圍第5項所述之積體電路結構，更包括：一導電阻障層，位於該含銅立柱上；以及一焊料層，位於該導電阻障層上。
  8. 如申請專利範圍第5項所述之積體電路結構，更包括一金屬表面處理層，位於該含銅立柱上，其中該金屬表面處理層包括一第一部位於該含銅立柱正上方以及一第二部位於該含銅立柱的一側壁上，其中該金屬表面處理層包括一金屬，其擇自於由錫、鎳、鈀、金以及其組合所構成之群族。
  9. 一種積體電路結構，包括：一半導體基底；一基底通孔電極自該半導體基底的一前表面延伸至一背表面；一含銅立柱，位於該半導體基底上方且電性連接至該基底通孔電極；以及一導電阻障層，位於該含銅立柱上，其中該導電阻障層、該含銅立柱及該基底通孔電極彼此電性連接。
  10. 如申請專利範圍第9項所述之積體電路結構，更包括：一內連線結構，位於該半導體基底上且電性連接至該基底通孔電極，其中該內連線結構含銅；以及一介電緩衝層，具有一第一部與該內連線結構切齊以及一第二部位於該內連線結構上。
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US20140227831A1 (en) 2014-08-14
TW201121022A (en) 2011-06-16
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US9349699B2 (en) 2016-05-24
US20110049706A1 (en) 2011-03-03

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