CN102013421A - 集成电路结构 - Google Patents

集成电路结构 Download PDF

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Publication number
CN102013421A
CN102013421A CN2010102735324A CN201010273532A CN102013421A CN 102013421 A CN102013421 A CN 102013421A CN 2010102735324 A CN2010102735324 A CN 2010102735324A CN 201010273532 A CN201010273532 A CN 201010273532A CN 102013421 A CN102013421 A CN 102013421A
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cupric
column
semiconductor
layer
integrated circuit
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CN102013421B (zh
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黄宏麟
萧景文
许国经
陈承先
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Abstract

本发明揭示一种集成电路结构，包括：一半导体基底；一基底通孔电极穿过半导体基底；以及一含铜立柱(post)，位于半导体基底上方且电性连接至基底通孔电极。通过形成含铜立柱来取代焊料凸块，可使含铜立柱的厚度获得良好的控制且可低于用于将晶片接合至承载晶片的粘着层可行的厚度。如此一来，晶片的内部结构可获得较佳的保护。

Description

集成电路结构
技术领域
本发明涉及一种集成电路结构，特别涉及一种集成电路结构内的内连线(interconnect)结构。
背景技术
由于各个电子部件(即，晶体管、二极管、电阻、电容等等)的集积度(integration density)持续不断的改进，使集成电路制造、半导体业持续的快速成长发展。主要来说，集积度的改进来自于最小特征尺寸(minimum feature size)不断缩小而容许更多的部件整合至既有的芯片面积内。
这些集积度的改进实质上是朝二维(two-dimensional，2D)方面的，因为集成部件所占的体积实际上位于半导体晶片的表面。尽管光刻(lithography)技术的精进为2D集成电路制作带来相当大的助益，二维空间所能拥有的密度还是有其物理限制。这些限制之一在于制作这些部件所需的最小尺寸。再者，当更多的装置放入一芯片中，需具有更复杂的电路设计。
另一限制来自于当装置数量增加时，其间的内连线(interconnection)的数量及长度大幅增加。而当内连线的数量及长度增加时，电路的时间延迟(RC delay)以及电量耗损均会增加。
在解决上述限制的方法之中，通常使用三维集成电路(three-dimensional integrated circuit，3DIC)及叠置芯片。而基底通孔电极(through-substrate-via，TSV)通常用于3DIC及叠置芯片中以连接芯片。在此情形中，基底通孔电极时常用以将芯片上的集成电路连接至芯片的背侧。另外，基底通孔电极也提供短接地路径，使集成电路通过芯片背侧(其可覆盖一接地金属层)而接地。
发明内容
本发明的目的在于克服现有技术中的上述缺陷。
本发明一实施例中，一种集成电路构包括：一半导体基底；一基底通孔电极穿过半导体基底；以及一含铜立柱，位于半导体基底上方且电性连接至基底通孔电极。
本发明另一实施例中，一种集成电路构包括：一半导体基底；一基底通孔电极自半导体基底的一前表面延伸至一背表面；一内连线结构，位于半导体基底的前表面，其中内连线结构含铜；以及一含铜立柱，位于半导体基底的前表面上且电性连接至基底通孔电极及内连线结构。
本发明又一实施例中，一种集成电路构包括：一半导体基底；一基底通孔电极自半导体基底的一前表面延伸至一背表面；一含铜立柱，位于半导体基底上方且电性连接至基底通孔电极；以及一导电阻挡层，位于含铜立柱上，其中导电阻挡层、该含铜立柱及基底通孔电极彼此电性连接。
通过形成含铜立柱来取代焊料凸块，可使含铜立柱的厚度获得良好的控制且可低于用于将晶片接合至承载晶片的粘着层可行的厚度。如此一来，晶片的内部结构可获得较佳的保护。
附图说明
图1至图9示出根据一实施例的制造前侧内连线结构的各个阶段剖面示意图。
图10至图19B示出根据另一实施例的制造前侧内连线结构的各个阶段剖面示意图，其中形成了后钝化保护层内连线。
其中，附图标记说明如下：
2～晶片；
10～基底；
10a～前表面/侧；
10b～背侧；
12～内连线结构；
14～半导体装置；
20～基底通孔电极；
22～隔离层；
24、26～钝化保护层；
28～金属接垫；
30～介电缓冲层；
32、40～开口；
34～凸块底部金属层；
38、64～掩模层；
44～金属立柱/含铜立柱；
46～导电阻挡层；
48～焊料层；
49～介金属化合物层；
50～承载晶片；
52～粘着层；
60～金属表面处理层；
61～顶层介层窗；
62～籽晶层；
66、68～后钝化保护层内连线。
具体实施方式
以下说明本发明实施例的制作与使用。然而，可轻易了解本发明实施例提供许多合适的发明概念而可实施于广泛的各种特定背景。所揭示的特定实施例仅仅用于说明以特定方法制作及使用本发明，并非用以局限本发明的范围。
以下根据一实施例说明一种新的内连线结构及其制造方法并配合附图说明制造上述实施例的各个阶段。全文中各个不同实施例及附图中，相同的标号用于表示相同的部件。
请参照图1，提供一晶片2，其包括一基底10。晶片2具有一前侧(面向上)及一背侧。基底10为一半导体基底，例如一块材(bulk)硅基底，然其可包括其他半导体材料，例如第三族、第四族及/或第五族元素。半导体装置14，例如晶体管，可形成于基底10的前表面/侧10a(表面10a在图1中为面向上)。内连线结构12形成于基底上且可连接至半导体装置14，内连线结构12包括形成于内的金属线及介层窗(via)(未示出)。金属线及介层窗可由铜或铜合金所构成，且可利用公知镶嵌工艺而形成。内连线结构12包括一般熟习的内层介电(inter-layer dielectric，ILD)层及金属层间(inter-metal dielectric，IMD)层。
基底通孔电极(through-substrate via，TSV)20自基底10的前表面10a延伸于基底10内。在一第一实施例中，基底通孔电极20是使用先钻孔(via-first)法来制做，且于形成内连线结构12之前完成。因此，基底通孔电极20仅延伸至内层介电(ILD)层(其用于覆盖有源(active)装置)而未延伸于内连线结构12的金属层间(IMD)层内。在另一实施例中，基底通孔电极20使用后钻孔(via-last)法来制做，且于形成内连线结构12之后完成。因此，基底通孔电极20贯穿基底10及内连线结构12。隔离层22形成于基底通孔电极20的侧壁及底部上且使基底通孔电极20与基底10电性隔离。隔离层22可由一般常用的介电材料所构成，例如氮化硅、氧化硅(如，四乙基硅酸盐(tetra-ethyl-ortho-silicate，TEOS)氧化物)等等。
钝化保护层24及26形成于内连线结构12上。在公知技术中，钝化保护层24及26通常分别称作钝化保护层-1及钝化保护层-2且可由以下材料所构成：氧化硅、氮化硅、未掺杂硅玻璃(un-doped silicate glass，USG)、聚酰亚胺(polyimide)及/或上述材料所组成的多层材料。金属接垫28形成于钝化保护层24。金属接垫28可由铝所构成，因而也可称作铝接垫28，然其也可由其他材料所构成，例如铜、银、金、镍、钨、上述金属的合金及/或上述金属所组成的多层材料。金属接垫28可通过下方的内连线结构12而电性连接至半导体装置14。开口32形成于钝化保护层26内，而金属接垫28经由开口32而露出。
请参照图2，形成介电缓冲层30，其可由聚酰亚胺所构成。图案化介电缓冲层30，以在开口32内形成另一开口，使金属接垫28经由开口32以及介电缓冲层30内的开口而露出。
请参照图3，形成一凸块底部金属层(under-bump metallurgy，UBM)34。凸块底部金属层34的可用材料包括一扩散阻挡层、一籽晶(seed)层或其组合。扩散阻挡层可包括Ti、TiN、Ta、TaN或其组合。籽晶层可包括铜或铜合金。然而，也可包括其他材料，例如，镍、钯、银、金、铝、上述金属的组合、及上述金属所组成的多层材料。在一实施例中，凸块底部金属层34利用溅镀(sputtering)来制做。在其他实施例中，也可利用电镀(electro plating)来制做。
图4示出掩模层38的制做。在一实施例中，掩模层38为干膜，其包括有机材料，例如增层绝缘膜(Ajinimoto buildup film，ABF)。另外，掩模层38也可由光致抗蚀剂所构成。接着图案化掩模层38，以形成开口40，其中金属接垫28位于开口40下方。
请参照图5，开口40内选择性填入一金属材料，以在开口40内形成金属立柱44。在一实施例中，填入的材料包括铜或铜合金，因而金属立柱44也称作含铜立柱44，然而也可使用其他金属，例如铝、银、金及其组合。含铜立柱44的厚度可小于60微米(μm)或在30微米至50微米的范围之间。含铜立柱的边缘可为垂直的，换句话说，垂直于半导体基底10的上表面。接着，形成导电阻挡层46，其可由含镍层、含铜层、或含锡层所构成。接着形成焊料(solder)层48，其可包括无铅焊料或共晶(eutectic)焊料。焊料层48的厚度小于15微米。含铜立柱44、导电阻挡层46及焊料层48的制造方法包括电化学电镀(electro-chemical plating，ECP)、无电电镀(electroless plating)或其他公知沉积方法，诸如溅镀、印刷及化学气相沉积(chemical vapor deposition，CVD)。焊料层48的上表面可低于掩模层38的上表面，使含铜立柱44、导电阻挡层46及焊料层48的边缘垂直对准，且焊料层48的边缘不会延伸超过含铜立柱44的边缘。
接着，请参照图6，去除掩模层38。如此一来，位于掩模层38下方部分的凸块底部金属层34会因此露出。请参照图7，通过闪蚀(flash etching)去除露出的凸块底部金属层34部分。接着进行回流工艺(re-flow)，使焊料层48形成圆化的上表面，如图8A所示。在一实施例中，如图8C所示，一介金属化合物(intermetallic compound，IMC)层49形成于含铜立柱44与回流后的焊料层48之间，其中导电阻挡层46可能会局部或完全耗尽。
图8A所示的导电阻挡层46及焊料层48可以一金属表面处理层(metal finish)取代之。请参照图8B，在形成掩模层38之后，形成含铜立柱44。在去除掩模层38之后，形成金属表面处理层60。金属表面处理层60的制造方法包括电化学电镀(ECP)、无电电镀等等。在一实施例中，金属表面处理层60包括由浸渍(immersion)法所形成的锡。在其他实施例中，金属表面处理层60包括化镍浸金(electroless nickel immersion gold，ENIG)。又其他实施例中，金属表面处理层60包括镍钯。又其他实施例中，金属表面处理层60包括化镍钯浸金(electroless nickel electroless palladium immersion gold，ENEPIG)。
请参照图9，晶片2经由粘着层52而组装于承载晶片50上。承载晶片50可为一玻璃晶片。可看到含铜立柱44、导电阻挡层46可能会局部或完全耗尽。
图8A所示的导电阻挡层46、焊料层48及焊料层48的加总厚度仅约在25微米至60微米之间的范围。此加总厚度是在粘着层52可达到的厚度范围以内。因此粘着层52可完全填入承载晶片50与晶片2之间的间隙而不会产生空孔。如此一来，在后续的背侧研磨工艺与内连线制造中，粘着层52可提供晶片2内的结构最大的保护。
在后续工艺步骤中，进行基底10的背侧10b研磨，并制做背侧内连线结构。举例来说，背侧研磨与内连线结构的制做揭示于2008年12月11日所提申的美国共同申请案中(申请号第12/332,934号；发明名称：Backside Connection to TSVs Having Redistribution Lines、申请号第12/347,742号；发明名称：Bond Pad Connection to Redistribution Lines Having Tapered Profiles)，其并入此处作为参考。此处不再赘述。在形成背侧内连线结构之后，且可能在将晶片2接合至另一晶片之后，承载晶片50可自晶片2处卸离，接着去除粘着层52。
图10至图19B示出另一实施例，其中形成了后钝化保护层内连线(post-passivation interconnect，PPI)。请参照图10，其示出内连线结构12内的金属线及介层窗。内连线结构可包括顶层介层窗61，其经由介电层而露出。顶层介层窗61可形成于一钝化保护层内，其可实质相同于图9所示的钝化保护层24及26。接着，请参照图11，形成一籽晶层62，其可由实质相同于图3所示的凸块底部金属层34的材料所构成。
请参照图12，形成一掩模层64，例如干膜或光致抗蚀剂。请参照图13，形成后钝化保护层内连线66及68。后钝化保护层内连线66可包括一金属接垫，而后钝化保护层内连线68可包括一金属线，用以配送信号。后钝化保护层内连线66连接至金属表面处理层60。再者，后钝化保护层内连线66可由铜所构成，然其可由其他材料所构成或加入这些材料，例如铝、银、钨等等。制造的方法包括电镀或无电电镀。
请参照图14，去除掩模层64，接着去除露出的凸块底部金属层34(即，籽晶层62)。由于凸块底部金属层34由实质相同于后钝化保护层内连线66及68的材料所构成，凸块底部金属层34将并入于后钝化保护层内连线66及68内，因而之后不再示出剩余的凸块底部金属层34。
在后续的工艺步骤中，如图15至图19B所示，形成含铜立柱44、导电阻挡层46及焊料层48。以下简单说明其工艺，而细节部分则实质相同于图3至图8A的工艺。除非有其他不同之处，否则图15至图19B中相同于图3至图8A的部件使用相同的标号。请参照图15，形成介电缓冲层30，其可由聚酰亚胺所构成。在介电缓冲层30内形成开口32并露出后钝化保护层内连线66。请参照图16，形成凸块底部金属层34。请参照图17，形成掩模层38。接着形成含铜立柱44、导电阻挡层46及焊料层48，如图18所示。图19示出去除掩模层38及露出部分的凸块底部金属层34。图19B示出另一实施例，其以金属表面处理层60取代了导电阻挡层46及焊料层48。
上述实施例拥有许多的优点。通过形成含铜立柱来取代焊料凸块，可使含铜立柱的厚度获得良好的控制且可低于用于将晶片接合至承载晶片的粘着层可行的厚度。如此一来，晶片的内部结构可获得较佳的保护。再者，含铜立柱与上方的焊料层及金属表面处理层并未明显向侧边延伸，因此可将相邻的含铜立柱之间距轻易控制在低于150微米。相较之下，在现行的集成电路结构中，由于使用焊料凸块，因此凸块间距必须大于150微米以避免相邻的焊料凸块之间发生短路。
虽然本发明已以优选实施例公开如上，然其并非用以限定本发明，任何所属技术领域中的普通技术人员，在不脱离本发明的精神和范围内，当可作各种更动、替代与润饰。然而，很清楚的是在不脱离本发明的精神和范围内，当可作出各种更动、结构、工艺及改变，如请求保护范围所述。再者，本发明的保护范围并未局限于说明书内所述特定实施例中的工艺、机器、制造、物质组成、装置、方法及步骤，任何所属技术领域中的普通技术人员可从本发明揭示内容中理解现行或未来所发展出的工艺、机器、制造、物质组成、装置、方法及步骤，只要可以在此处所述实施例中实施大体相同功能或获得大体相同结果皆可使用于本发明中。因此，本发明的保护范围包括上述工艺、机器、制造、物质组成、装置、方法及步骤。另外，每一权利要求构成个别的实施例，且本发明的保护范围也包括各个权利要求及实施例的组合。

Claims (10)

1.一种集成电路结构，包括：
一半导体基底；
一基底通孔电极穿过该半导体基底；以及
一含铜立柱，位于该半导体基底上方且电性连接至该基底通孔电极。
2.如权利要求1所述的集成电路结构，还包括：
一导电阻挡层，位于该含铜立柱上；以及
一焊料层，位于该导电阻挡层上。
3.如权利要求1所述的集成电路结构，还包括一金属层，位于该含铜立柱上，其中该金属层包括一第一部位于该含铜立柱正上方以及一第二部位于该含铜立柱的一侧壁上。
4.如权利要求1所述的集成电路结构，还包括：
一凸块底部金属层，形成于该含铜立柱与该半导体基底之间；
一金属接垫，位于该凸块底部金属层下方并与其连接；以及
一介电缓冲层，位于该金属接垫上，其中该金属接垫通过该介电缓冲层内的一导电特征部件而连接至该凸块底部金属层。
5.一种集成电路结构，包括：
一半导体基底；
一基底通孔电极自该半导体基底的一前表面延伸至该半导体基底内；
一内连线结构，位于该半导体基底的该前表面，其中该内连线结构含铜；以及
一含铜立柱，位于该半导体基底的该前表面上且电性连接至该基底通孔电极及该内连线结构。
6.如权利要求5所述的集成电路结构，还包括：
一含铝接垫，位于该半导体基底上且电性连接至基底通孔电极；
一凸块底部金属层，位于该含铝接垫上且与其电性连接；以及
一聚酰亚胺层，位于含铝接垫上且位于一部分的该凸块底部金属层下方，其中该凸块底部金属层与包括一延伸部延伸于该聚酰亚胺层内且与该含铝接垫接触。
7.如权利要求5所述的集成电路结构，还包括：一导电阻挡层，位于该含铜立柱上；以及
一焊料层，位于该导电阻挡层上。
8.如权利要求5所述的集成电路结构，还包括一金属表面处理层，位于该含铜立柱上，其中该金属表面处理层包括一第一部位于该含铜立柱正上方以及一第二部位于该含铜立柱的一侧壁上，其中该金属表面处理层包括一金属，其择自于由锡、镍、钯、金以及其组合所构成的群族。
9.一种集成电路结构，包括：
一半导体基底；
一基底通孔电极自该半导体基底的一前表面延伸至一背表面；
一含铜立柱，位于该半导体基底上方且电性连接至该基底通孔电极；以及
一导电阻挡层，位于该含铜立柱上，其中该导电阻挡层、该含铜立柱及该基底通孔电极彼此电性连接。
10.如权利要求9所述的集成电路结构，还包括：
一内连线结构，位于该半导体基底上且电性连接至该基底通孔电极，其中该内连线结构含铜；以及
一介电缓冲层，具有一第一部与该内连线结构切齐以及一第二部位于该内连线结构上。
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