TWI520243B - 半導體裝置及其製造方法 - Google Patents

半導體裝置及其製造方法 Download PDF

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Publication number
TWI520243B
TWI520243B TW102121292A TW102121292A TWI520243B TW I520243 B TWI520243 B TW I520243B TW 102121292 A TW102121292 A TW 102121292A TW 102121292 A TW102121292 A TW 102121292A TW I520243 B TWI520243 B TW I520243B
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Taiwan
Prior art keywords
layer
metal
patterning process
bump
semiconductor device
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TW102121292A
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English (en)
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TW201403724A (zh
Inventor
周孟緯
郭宏瑞
何明哲
劉重希
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台灣積體電路製造股份有限公司
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    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
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    • H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
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Description

半導體裝置及其製造方法
本發明係有關於一種半導體裝置及其製造方法。
因為各種電子元件(例如電晶體、二極體、電阻器、電容器等)的積集密度不斷地改善，半導體工業已經歷快速的發展。大多數的情況下，積集密度的改善是因為不斷地使電子元件之最小特徵尺寸縮小，這容許更多的元件整合在有限的範圍。近來隨著更小的電子裝置之需求的成長，更小且更創新的半導體晶粒封裝技術是必須的。
隨著半導體工藝發展，發展出晶圓級尺寸封裝(wafer-level chip scale package)結構，其作為能有效地更進一步縮小半導體裝置之實際尺寸的方案。在晶圓級尺寸封裝結構中，電晶體等主動裝置形成於晶圓級尺寸封裝結構的基板之上表面上。在基板的上方形成不同的金屬化(metallization)層，金屬化層包括互連(interconnect)結構。在頂金屬化層之上形成金屬墊，金屬墊電性連接至互連結構。在金屬墊之上可形成保護(passivation)層與第一聚合物層。保護層與第一聚合物層中的開口暴露出金屬墊。
在第一聚合物層上形成第一晶種(seed)層。在第一晶種層之上可形成後保護互連(post-passivation interconnect, PPI)金屬線及墊，其可藉由使用合適的製造技術形成，例如在第一晶種層上形成並圖案化第一光阻層、在第一光阻層中的開口內鍍上PPI金屬線及墊，接著移除第一光阻層。此外，藉由使用合適的蝕刻製程，將原本被第一光阻層遮蓋的部分第一晶種層移除。
可在PPI線及墊上方形成第二聚合物層。藉由使用合適的製造技術，例如圖案化，形成第二開口，第二開口係為了凸塊下金屬層(under bump metallization,UBM)而形成。在第二聚合物層上方形成第二晶種層。UBM結構伸入第二聚合物層中的第二開口，其中UBM結構電性連接至PPI金屬線與墊。UBM結構之製造步驟包括在第二晶種層上方形成第二光阻層、圖案化第二光阻層、在第二晶種層上形成UBM結構、移除第二光阻層、以及移除原本被第二光阻層遮蓋的部分第二晶種層。
一種半導體裝置的製造方法，包括：形成一保護(passivation)層於一基板上，其中一金屬墊埋入(embedded)保護層中；沉積一第一介電層於保護層上；施加一第一圖案化製程於第一介電層，以形成一第一開口；形成一第一晶種(seed)層於第一開口上；填入一導電材料至第一開口，以形成一金屬線，其中該金屬線之一頂表面與該第一介電層之一頂表面齊平；沉積一第二介電層於第一介電層上；施加一第二圖案化製程於第二介電層，以形成一第二開口；形成一凸塊下金屬層(under bump metallization,UBM)結構於第二開口上；以及固定 一互連凸塊於凸塊下金屬層結構上，其中第一圖案化製程與第二圖案化製程至少其一為雷射剝蝕製程。
一種半導體裝置的製造方法，包括：形成一保護層於一基板上，其中一金屬墊埋入保護層中且透過保護層的一開口暴露出；沉積一第一聚合物層於保護層上；施加一第一圖案化製程於第一聚合物層，以形成一第一溝槽；形成一第一晶種層於第一聚合物層上；透過一第二圖案化製程移除第一晶種層的無溝槽部份；填入一導電材料至第一溝槽；沉積一第二聚合物層於第一聚合物層上；施加一第三圖案化製程於第二聚合物層，以形成一凸塊下金屬層開口；形成一凸塊下金屬層結構於第二聚合物層中；以及固定一互連凸塊於凸塊下金屬層結構上，其中第一圖案化製程與第二圖案化製程至少其一為雷射剝蝕製程。
一種半導體裝置，包括：一金屬墊，位於一基板上方；一保護層，位於基板上方，其中金屬墊埋入保護層且透過保護層的一開口暴露出；一第一介電層，形成於保護層上方；一後保護互連結構，形成於第一介電層中，其中後保護互連結構包括：一晶種層，以保角的方式形成於一第一溝槽中，其中第一溝槽係由施加一第一圖案化製程於第一介電層而形成；以及一金屬線，形成於晶種層上方，其中金屬線電性連接至金屬墊，其中該金屬線之一頂表面與該第一介電層之一頂表面齊平；一第二介電層，形成於第一介電層上方，其中第二介電層包括藉由一第二圖案化製程形成的一第二溝槽；一凸塊下金屬層結構，形成於第二溝槽上方；以及一互連凸塊，形成於 凸塊下金屬層結構上方，其中第一圖案化製程與第二圖案化製程至少其一為雷射剝蝕製程。
100‧‧‧半導體裝置
101‧‧‧第二金屬線
102‧‧‧頂金屬化層
104‧‧‧保護層
106‧‧‧頂金屬墊
108‧‧‧第一聚合物層
110‧‧‧保護互連結構
112‧‧‧第二聚合物層
114、402‧‧‧晶種層
116‧‧‧金屬線
122‧‧‧互連結構
124‧‧‧導電層
126‧‧‧互連凸塊
131‧‧‧第一金屬線
132‧‧‧底金屬化層
142‧‧‧層間介電層
152‧‧‧基板
302、802‧‧‧開口
第1圖根據一實施例繪示出具有晶片級封裝元件的半導體裝置之剖面示意圖。
第2圖係根據一實施例繪示出在半導體裝置上形成第一聚合物層的半導體裝置之剖面示意圖。
第3圖根據一實施例繪示出第2圖中的半導體裝置之第一聚合物層的表面經過第一圖案化製程後的剖面示意圖。
第4圖根據一實施例繪示出在第3圖中的半導體裝置之第一聚合物層之上形成晶種層後的剖面示意圖。
第5圖根據一實施例繪示出在第4圖中的半導體裝置之晶種層之表面上施加第二圖案化製程後的剖面示意圖。
第6圖根據一實施例繪示出在第圖中的半導體裝置之晶種層之上形成後保護金屬線後的剖面示意圖。
第7圖根據一實施例繪示出在第6圖中的半導體裝置之上形成第二聚合物層後的剖面示意圖。
第8圖根據一實施例繪示出在第7圖中的半導體裝置之第二聚合物層之表面上施加第三圖案化製程後的剖面示意圖。
第9圖根據一實施例繪示出在第8圖中的半導體裝置之第一聚合物層上形成UBM晶種層後的剖面示意圖。
第10圖根據一實施例繪示出在第9圖中的半導體裝置之UBM晶種層之表面上施加第四圖案化製程後的剖面示意圖。
第11圖根據一實施例繪示出在第10圖中的半導體裝置之UBM晶種層之上形成第二導電層後的剖面示意圖。
第12圖根據一實施例繪示出在第11圖中的半導體裝置之UBM結構上形成互連凸塊後的剖面示意圖。
以下說明本發明實施例之製作與使用。然而，可輕易了解本發明實施例提供許多合適的發明概念而可實施於廣泛的各種特定背景。所揭示的特定實施例僅僅用於說明以特定方法製作及使用本發明，並非用以侷限本發明的範圍。
以下將對應到本發明實施例作特定背景的詳細敘述，其為具有晶片級封裝元件的半導體裝置之製造步驟。然而，本發明之實施例也可應用於各種半導體裝置。以下，將配合附圖對不同實施例作出詳細說明。
第1圖根據一實施例繪示出具有晶片級封裝元件的半導體裝置之剖面示意圖。如第1圖所示，半導體裝置100包括基板152。基板152可由矽、鍺化矽、或碳化矽等所組成。另外，基板152可為矽覆絕緣體(silicon-on insulator,SOI)基板。SOI基板可包括在絕緣層(例如，埋入氧化物(buried oxide)等)上方形成一層半導體材料(例如，矽、鍺等)，絕緣層係形成於矽基板中。再者，其他可被使用的基板包括多層(multi-layered)基板、梯度(gradient)基板、混成定向(hybrid orientation)基板等。
基板152可更進一步包括各種電子電路(未顯示)。形成於基板152上的電子電路可為適合特定應用的任何 類型的電路。
根據一實施例，電子電路可包括各種n型金屬氧化物半導體(n-type metal-oxide semiconductor,NMOS)及/或p型金屬氧化物半導體(p-type metal-oxide semiconductor,PMOS)，例如電晶體、電容器、電阻器、二極體、光電二極體(photo-diode)、引線等。電子電路可互連以呈現一或多種功能。上述功能可包括記憶(memory)結構、處理(processing)結構、感測器、擴大器(amplifier)、電源分配器、輸入/輸出電路等。此領域中之技藝人士應理解到，以上提供之範例僅是為了詳述本發明之應用，並非用以限制本發明。
在基板152之上形成層間(interlayer)介電層142。層間介電層142可由低介電常數材料所形層，例如氧化矽。層間介電層142可由任何合適的習知方法形成，例如旋轉(spinning)、化學氣相沉積(chemical vapor deposition,CVD)、及電漿加強化學氣相沈積(plasma enhanced chemical vapor deposition,PECVD)。值得一提的是，此領域之技藝人士將理解到層間介電層142可更包括多個介電層。
在層間介電層142上方形成底金屬化(metallization)層132與頂金屬化層102。如第1圖所示，底金屬化層132包括第一金屬線131。同樣地，頂金屬化層102包括第二金屬線101。金屬線131與102係由例如銅或銅合金等的金屬材料所形成。金屬化層132與102可由任何合適技術(例如沉積、鑲嵌(damascene)等)所形成。一般而言，上述一或多個層間金屬介電層與其相關的金屬化層係被用來使基板152中 的電子電路互連，以形成功能性電路，並進而提供外部電性連接。
值得一提的是，儘管第1圖顯示底金屬化層132與頂金屬化層102，此領域技藝人士將理解到一或多個層間金屬介電層(未顯示)與其相關的金屬化層(未顯示)形成於底金屬化層132與頂金屬化層102之間。確切地說，底金屬化層132與頂金屬化層102之間的多個層可由介電材料(例如，極(extremely)低介電常數材料)及導電材料(例如，銅)交替形成。
在頂金屬化層102之上形成保護(passivation)層104。根據一實施例，保護層係由無機材料所形成，例如未摻雜的矽玻璃、氮化矽、氧化矽等。此外，保護層104可由低介電常數材料所形成，例如氧化物摻雜碳等。再者，可使用極低介電常數(extremely low-k,ELK)材料以形成保護層104，ELK材料可包括多孔二氧化矽摻雜碳。
保護層104可透過任何合適技術而形成，例如CVD。如第1圖所示，可在保護層104中形成開口。開口係用以容納頂金屬墊106。
如第1圖所示，頂金屬墊106埋入(embedded)保護層104。切確地說頂金屬墊106在半導體裝置100的金屬線101與後保護互連(post-passivation interconncet)結構之間提供導電通道(channel)。可由金屬材料製作頂金屬墊106，例如，銅、銅合金、鋁、銀、金等金屬材料、上述之組合、及/或上述之多層膜。可藉由合適技術形成頂金屬墊106，例如CVD。此外，可藉由濺鍍(sputtering)、電鍍等形成頂金屬墊106。
在保護層104上形成第一介電層，例如，第一聚合物層108。第一聚合物層可由聚合物材料製作，例如，環氧樹酯(epoxy)、聚亞醯胺樹脂(polyimide)等。此外，第一聚合物層108可由合適的聚合物介電材料形成，例如聚苯噁唑(polybenzoxazole,PBO)。第一聚合物層108可由此技藝任何合適的習知方法製作，例如旋轉塗佈(spin coating)。
在第一聚合物層108中形成後保護互連結構110。如第1圖所示，後保護互連結構110可包括晶種層114及形成於晶種層114上方的金屬線116。後保護互連結構110以半導體裝置100的輸入/輸出端子(terminal)連接金屬墊106。更切確地說，後保護互連結構110提供半導體裝置100的金屬線(例如，金屬線101)與輸入/輸出端子(例如，互連凸塊(bump)126)之間的導電路徑。後保護互連結構110之操作原理在此技藝中係眾所皆知，因此在此不再詳述。
在第一聚合物層108之上形成第二介電層，例如，第二聚合物層112。第二聚合物層係由聚合物材料所製作，例如，環氧樹酯(epoxy)、聚亞醯胺樹脂(polyimide)等。此外，第二聚合物層112可由合適的聚合物介電材料形成，例如聚苯噁唑(polybenzoxazole,PBO)。第二聚合物層112可由此技藝任何合適的習知方法製作，例如旋轉塗佈(spin coating)。
凸塊126固定至凸塊下金屬層(under bump metallization,UBM)結構上。根據一實施例，凸塊126可為銅凸塊。銅凸塊之高度可為約45um。根據一實施例，可使用各種半導體封裝技術製作銅凸塊，例如，濺鍍、電鍍、及微影 (photolithography)。
根據另一實施例，凸塊126可為焊(solder)球。焊球126可由任何合適材料製作。根據一實施例，焊球126可由SAC405製作。SAC405包括：95.5% Sn、4.0% Ag、及0.5% Cu。
第2~12圖係根據一實施例繪示出製造第1圖顯示的半導體裝置100之後保護互連結構的中間階段之剖面示意圖。第2圖係根據一實施例繪示出在半導體裝置上形成第一聚合物層的半導體裝置之剖面示意圖。為了簡明起見，第2~12圖所繪示之製造步驟不包括頂金屬化層102下方的層與結構。
如第2圖所示，在頂金屬化層102上方形成保護層104。金屬墊106埋入保護層104中。此外，保護層104的開口暴露出金屬墊106。在保護層104上方沉積第一介電層，例如，第一聚合物層108。第一聚合物層108可由合適的聚合物介電材料形成，例如聚苯噁唑(polybenzoxazole,PBO)。第一聚合物層108之厚度可為約4um~10um。
第3圖根據一實施例繪示出第2圖中的半導體裝置之第一聚合物層的表面經過第一圖案化製程後的剖面示意圖。可藉由使用雷射剝蝕(ablation)製程執行第一圖案化製程。根據後保護互連結構110(在此未顯示，繪示在第1圖中)的形狀與位置而在第一聚合物層108之表面施加雷射束(未顯示)。如此一來，部份的第一聚合物層108被移除並形成開口302。根據一實施例，雷射束的波長為約308nm。雷射束的能量劑量為約500mJ/cm2~600mJ/cm2。
第4圖根據一實施例繪示出在第3圖中的半導體 裝置之第一聚合物層之上形成晶種層後的剖面示意圖。為了提供成核位置(nucleation site)給隨後的大量金屬沉積，薄晶種層402沉積於第一聚合物層108之上。薄晶種層402可包括導電材料，例如銅。可藉由使用合適的製造技術製造薄晶種層402，例如濺鍍、CVD等。
第5圖根據一實施例繪示出在第4圖中的半導體裝置之晶種層之表面上施加第二圖案化製程後的剖面示意圖。可藉由使用雷射剝蝕(ablation)製程執行第二圖案化製程。在晶種層402(顯示在第4圖中)的無溝槽(non-trench)部份之表面施加雷射束(未顯示)。如此一來，位於第一聚合物層108的無溝槽部份的一部份晶種層402被移除並形成晶種層114。根據一實施例，雷射束的波長為約308nm。雷射束的能量劑量為約1000mJ/cm2~1200mJ/cm2。
第6圖根據一實施例繪示出在第5圖中的半導體裝置之晶種層之上形成後保護金屬線後的剖面示意圖。如第6圖所示，填入導電材料至開口(第3圖中的開口302)以形成後保護互連結構110的金屬線116。金屬線116之頂表面與第一聚合物層108之頂表面齊平。導電材料可為銅，也可為任何合適的導電材料，例如銅合金、鋁、鎢、銀、及上述之組合。可藉由合適的技術形成後保護互連結構110的金屬線116，例如，無電(electro-less)電鍍製程。
第7圖根據一實施例繪示出在第6圖中的半導體裝置之上形成第二聚合物層後的剖面示意圖。在第一聚合物層108之上沉積第二介電層，例如，第二聚合物層112。第二聚 合物層112可由合適的聚合物介電材料形成，例如聚苯噁唑(polybenzoxazole,PBO)。第二聚合物層112之厚度可為約4um~10um。
第8圖根據一實施例繪示出在第7圖中的半導體裝置之第二聚合物層之表面上施加第三圖案化製程後的剖面示意圖。可藉由使用雷射剝蝕(ablation)製程執行第三圖案化製程。確切地說，根據UBM結構(在此未顯示，繪示在第1圖中)的形狀與位置而在第二聚合物層112之表面施加雷射束(未顯示)以形成開口802。根據一實施例，雷射束的波長為約308nm。雷射束的能量劑量為約500mJ/cm2~600mJ/cm2。
第9圖根據一實施例繪示出在第8圖中的半導體裝置之第一聚合物層上形成UBM晶種層後的剖面示意圖。在第二聚合物層112上沉積UBM晶種層902。UBM晶種層902可包括導電材料，例如銅。可藉由使用合適的製造技術製造UBM晶種層902，例如濺鍍、CVD等。
第10圖根據一實施例繪示出在第9圖中的半導體裝置之UBM晶種層之表面上施加第四圖案化製程後的剖面示意圖。可藉由使用雷射剝蝕(ablation)製程執行第四圖案化製程。根據第1圖的UBM結構之形狀與位置而在UBM晶種層902之表面施加雷射束(未顯示)。如此一來，部份的UBM晶種層902被移除。根據一實施例，雷射束的波長為約308nm。雷射束的能量劑量為約1000mJ/cm2~1200mJ/cm2。
第11圖根據一實施例繪示出在第10圖中的半導體裝置之UBM晶種層之上形成第二導電層後的剖面示意圖。 如第11圖所示，為了得到可靠的UBM結構，可在UBM晶種層122之上以保角(conformal)的方式沉積附加的導電材料以形成附加的導電層124。導電材料可為銅合金、鋁、鎢、銀、及上述之組合。導電層124可藉由合適的技術形成，例如無電電鍍。
第12圖根據一實施例繪示出在第11圖中的半導體裝置之UBM結構上形成互連凸塊後的剖面示意圖。互連凸塊126提供半導體裝置連接至外部電路(未顯示)的有效方法。根據一實施例，互連凸塊126可為焊球。焊球126可由任何合適的材料製作。根據一實施例，焊球126可包括SAC405。SAC405包括：95.5% Sn、4.0% Ag、及0.5% Cu。
根據第2~12圖，上述的製造方法的一優勢特徵係在於雷射剝蝕製程有益於減少晶圓級尺寸封裝(wafer-level chip scale package)的製造成本。例如，在傳統的製程中，為了形成後保護互連結構，製造過程中可有兩層光阻層的形成與移除。藉由使用上述第2~12圖的雷射剝蝕製程，省去了光阻層及其對應的製造步驟(例如，塗佈、曝光(exposure)、顯影(development)、及蝕刻)。如此一來，降低了晶圓級尺寸封裝的製造成本。
雖然本發明已以較佳實施例揭露如上，然其並非用以限定本發明，任何所屬技術領域中具有通常知識者，在不脫離本發明之精神和範圍內，當可作更動、替代與潤飾。舉例來說，任何所屬技術領域中具有通常知識者可輕易理解此處所述的許多特徵、功能、製程及材料可在本發明的範圍內作更動。
再者，本發明之保護範圍並未侷限於說明書內所述特定實施例中的製程、機器、製造、物質組成、裝置、方法及步驟，任何所屬技術領域中具有通常知識者可從本發明揭示內容中理解現行或未來所發展出的製程、機器、製造、物質組成、裝置、方法及步驟，只要可以在此處所述實施例中實施大體相同功能或獲得大體相同結果皆可使用於本發明中。因此，本發明之保護範圍包括上述製程、機器、製造、物質組成、裝置、方法及步驟。另外，每一申請專利範圍構成個別的實施例，且本發明之保護範圍也包括各個申請專利範圍及實施例的組合。
100‧‧‧半導體裝置
101‧‧‧第二金屬線
102‧‧‧頂金屬化層
104‧‧‧保護層
106‧‧‧頂金屬墊
108‧‧‧第一聚合物層
110‧‧‧保護互連結構
112‧‧‧第二聚合物層
114‧‧‧晶種層
116‧‧‧金屬線
122‧‧‧互連結構
124‧‧‧導電層
126‧‧‧互連凸塊
131‧‧‧第一金屬線
132‧‧‧底金屬化層
142‧‧‧層間介電層
152‧‧‧基板

Claims (10)

  1. 一種半導體裝置的製造方法，包括：形成一保護(passivation)層於一基板上，其中一金屬墊埋入(embedded)該保護層中；沉積一第一介電層於該保護層上；施加一第一圖案化製程於該第一介電層，以形成一第一開口；形成一第一晶種(seed)層於該第一開口上；填入一導電材料至該第一開口，以形成一金屬線，其中該金屬線之一頂表面與該第一介電層之一頂表面齊平；沉積一第二介電層於該第一介電層上；施加一第二圖案化製程於該第二介電層，以形成一第二開口；形成一凸塊下金屬層(under bump metallization,UBM)結構於該第二開口上；以及固定一互連凸塊於該凸塊下金屬層結構上，其中該第一圖案化製程與該第二圖案化製程至少其一為雷射剝蝕製程。
  2. 如申請專利範圍第1項所述之半導體裝置的製造方法，更包括：沉積一凸塊下金屬晶種層於該第二介電層上方；透過一第三圖案化製程移除一部分的該凸塊下金屬晶種層；以及以保角(conformal)的方式沉積一導電層，於該凸塊下金屬晶種層上方，其中 透過一第一無電(electro-less)電鍍製程沉積該導電層。
  3. 如申請專利範圍第1項所述之半導體裝置的製造方法，更包括：透過一第二無電電鍍製程填入該導電材料至該第一開口。
  4. 一種半導體裝置的製造方法，包括：形成一保護層於一基板上，其中一金屬墊埋入該保護層中且透過該保護層的一開口暴露出；沉積一第一聚合物層於該保護層上；施加一第一圖案化製程於該第一聚合物層，以形成一第一溝槽；形成一第一晶種層於該第一聚合物層上；透過一第二圖案化製程移除該第一晶種層的無溝槽部份；填入一導電材料至該第一溝槽；沉積一第二聚合物層於該第一聚合物層上；施加一第三圖案化製程於該第二聚合物層，以形成一凸塊下金屬層開口；形成一凸塊下金屬層結構於該第二聚合物層中；以及固定一互連凸塊於該凸塊下金屬層結構上，其中該第一圖案化製程與該第三圖案化製程至少其一為雷射剝蝕製程。
  5. 如申請專利範圍第4項所述之半導體裝置的製造方法，其中：該第一圖案化製程為一第一雷射剝蝕製程，其能量值為約500mJ/cm2~600mJ/cm2。
  6. 如申請專利範圍第4項所述之半導體裝置的製造方法，其中：該第二圖案化製程為一第二雷射剝蝕製程，其能量值為約1000mJ/cm2~1200mJ/cm2。
  7. 如申請專利範圍第4項所述之半導體裝置的製造方法，更包括：沉積一凸塊下金屬晶種層於該第二聚合物層上；透過一第四圖案化製程移除部份的該凸塊下金屬晶種層；以及以保角的方式沉積一導電層於該凸塊下金屬晶種層上，以形成凸塊下金屬層結構。
  8. 一種半導體裝置，包括：一金屬墊，位於一基板上方；一保護層，位於該基板上方，其中該金屬墊埋入該保護層且透過該保護層的一開口暴露出；一第一介電層，形成於該保護層上方；以及一後保護互連結構，形成於該第一介電層中，其中該後保護互連結構包括：一晶種層，以保角的方式形成於一第一溝槽中，其中該第一溝槽係由施加一第一圖案化製程於該第一介電層而形成；一金屬線，形成於該晶種層上方，其中該金屬線電性連接至該金屬墊，其中該金屬線之一頂表面與該第一介電層之一頂表面齊平； 一第二介電層，形成於該第一介電層上方，其中該第二介電層包括藉由一第二圖案化製程形成的一第二溝槽；一凸塊下金屬層結構，形成於該第二溝槽上方；以及一互連凸塊，形成於該凸塊下金屬層結構上方，其中該第一圖案化製程與該第二圖案化製程至少其一為雷射剝蝕製程。
  9. 如申請專利範圍第8項所述之半導體裝置，其中該凸塊下金屬結構層結構包括：一凸塊下金屬晶種層；以及一導電層，形成於該凸塊下金屬晶種層上方。
  10. 如申請專利範圍第8項所述之半導體裝置，更包括：多個金屬化層，形成於該基板與該金屬墊之間。
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CN103545249B (zh) 2016-09-07

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