TWI449140B - 積體電路裝置及封裝組件 - Google Patents

積體電路裝置及封裝組件 Download PDF

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Publication number
TWI449140B
TWI449140B TW99136673A TW99136673A TWI449140B TW I449140 B TWI449140 B TW I449140B TW 99136673 A TW99136673 A TW 99136673A TW 99136673 A TW99136673 A TW 99136673A TW I449140 B TWI449140 B TW I449140B
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Taiwan
Prior art keywords
layer
metal layer
bump
metal
sidewall
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TW99136673A
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English (en)
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TW201145482A (en
Inventor
Chien Ling Hwang
Hui Jung Tsai
Yi Wem Wu
Chung Shi Liu
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Taiwan Semiconductor Mfg
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Publication of TW201145482A publication Critical patent/TW201145482A/zh
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Publication of TWI449140B publication Critical patent/TWI449140B/zh

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    • H01L21/7688—Filling of holes, grooves or trenches, e.g. vias, with conductive material by deposition over sacrificial masking layer, e.g. lift-off
    • C—CHEMISTRY; METALLURGY
    • C23—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
    • C23C—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL
    • C23C14/00—Coating by vacuum evaporation, by sputtering or by ion implantation of the coating forming material
    • C23C14/22—Coating by vacuum evaporation, by sputtering or by ion implantation of the coating forming material characterised by the process of coating
    • C23C14/34—Sputtering
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Description

積體電路裝置及封裝組件
本發明係有關於積體電路製造，且特別是有關於一種積體電路中的銅柱凸塊結構。
現今積體電路係由數以百萬計之主動裝置(例如電晶體及電容)製成。這些裝置起初彼此互相隔離，但經由內連線相互連接而形成功能性電路。一般而言，內連線結構包含橫向內連線，例如金屬線(導線)，及垂直內連線，例如通孔(via)或接觸點。內連線數量的增加亦限制了現今積體電路的效能及密度。在內連線結構之頂端上，連接墊形成於晶片表面上並暴露於外，透過連接墊形成電性連接以連接一晶片至另一晶片或封裝基材。可使用導線連接或是覆晶連接來連接這些連接墊。
覆晶封裝使用凸塊來建立晶片之輸入/輸出墊與封裝體之基材或導線架之間的電性接觸。結構上，凸塊實際上包含凸塊本身及位於凸塊及輸入/輸出墊之間的凸塊下金屬(under bump metallurgy，UBM)。凸塊下金屬通常包含黏著層、阻障層及潤濕層(wetting layer)。凸塊本身基於其所使用之材料可分為錫鉛凸塊、金凸塊、銅柱凸塊及混用多種金屬的凸塊。近來，已發展出銅柱凸塊技術。電子元件藉由銅柱凸塊來取代焊料凸塊作連接，以使凸塊橋接的機率降至最低而達到較密集的節距(finer pitch)，減少電路的負載電容(capacitance load)，並使電子元件能在更高頻下運作。
銅柱凸塊覆晶組合具有以下優點：(1)較佳的熱/電子效能，(2)較高的電流承載容積，(3)對於電子遷移具有較佳的阻抗，因此可延長凸塊的壽命，(4)較少的成型空隙(molding gap)，亦即在銅柱凸塊之間具有較一致的間隙。此外，藉由銅柱的使用來控制焊料的散佈，不需無鉛珠狀物(lead-free teardrops)的設計，可使基材成本較低。現今製程中，使用具有開口之光阻層，並形成由金屬蓋所覆蓋的銅柱於光阻層之開口中。然而，形成金屬蓋通常導致光阻於剝除製程之前或之後形成缺陷。在使用無電電鍍/浸鍍(electroless/immersion)金屬沉積製程的方法中，既然浸鍍介質直接碰觸光阻層，可能會造成光阻脫落(leaching)，而造成光阻脫層(delamination)浸泡污染、及導致較差的頂部覆蓋率。在另一使用電鍍金屬製程的方法中，可觀察到在剝除光阻層後，仍有光阻殘餘物殘存在基材上。
此外，銅在製造過程中容易氧化，氧化的銅柱會導致電子元件對基材的黏著性變差，較差的黏著性因為漏電流較高，會造成嚴重的可靠度問題。氧化的銅柱也會導致底部填膠沿著底部填膠與銅柱之間的界面裂開，此裂縫會蔓延至底下的低介電常數介電層，或蔓延至用於接合銅柱至基材的焊錫。因此，需要側壁保護層來避免銅氧化，但是傳統處理銅柱側壁的方法需要較高的製造成本，並且會有界面脫層問題。目前使用化學浸錫製程(immersion tin process)在銅柱側壁上提供錫層，但是仍然有製造成本、錫與底部填膠之間的黏著力，以及焊錫潤濕至側壁上的問題產生，其對於新世代晶片的微細節距封裝技術是一種挑戰。
本發明係提供一種積體電路裝置，包括：一半導體基材；一凸塊下金屬層，形成於此半導體基材上；一導電柱體，形成於此凸塊下金屬層上，且具有一頂面及一側壁表面，其中此側壁表面具有一鄰近此頂面之第一部分及一鄰近此凸塊下金屬層之第二部分；一非金屬保護結構，形成於此導電柱體之此側壁表面之第二部分上；以及一金屬蓋層，形成於此頂面上並延伸至此導電柱體之此側壁表面之第一部分上。
本發明亦提供一種封裝組件，包括：一第一基材；一凸塊下金屬層，形成於此第一基材上；一銅柱，形成於此凸塊下金屬層上，且具有一頂部、一鄰近此頂部之第一側壁部分、及一鄰近此第一基材之第二側壁部分；一非金屬保護結構，覆蓋此銅柱之此第二側壁部分；一金屬蓋層，覆蓋此銅柱之此頂部及此第一側壁部分；一第二基材；以及一共焊層，形成於此第二基材及此金屬蓋層之間。
為讓本發明之上述和其他目的、特徵、和優點能更明顯易懂，下文特舉出較佳實施例，並配合所附圖式，作詳細說明如下：
本發明係提供用於銅柱凸塊技術之側壁間隔物及頂蓋的製程。側壁間隔物作為銅柱凸塊側壁之保護結構，係由一或多層的非金屬材料層形成，例如介電材料層、聚合物材料層或前述之組合。頂蓋，作為銅柱凸塊頂面上之阻障結構，用以防止銅擴散至接合材料中，接合材料包含至少一金屬層，例如無電鎳鈀浸金(electroless nickel electroless palladium immersion gold，ENEPIG)結構(由無電鍍鎳/無電鍍鈀/浸金層所組成之堆疊結構)、無電鎳鈀(electroless nickel electroless palladium，ENEP)結構(由無電鍍鎳/無電鍍鈀層所組成之堆疊結構)、無電鎳(electroless nickel，EN)結構(無電鍍鎳層)、無電鎳浸金(electroless nickel immersion gold，ENIG)結構(由無電鍍鎳/浸金層所組成之堆疊結構)或前述之組合，由無電電鍍或浸鍍金屬沉積製程所形成。在本說明書中，“銅柱凸塊”意指包含含銅或銅合金之導電柱體(立柱(post)或限位塊(standoff))之凸塊結構。銅柱凸塊可直接設在半導體晶片上之導電墊、用以作覆晶組合重分佈層上或作其他的應用。
以下將配合所舉例之圖示為參考，詳述本發明之各實施例。無論任何可能的地方，說明書及圖示中之相同標號代表相同或相似元件。在圖示中，實施例之形狀及厚度可作放大以使圖示清晰易懂。本說明書將依照本發明描述特定的元件形成，其可能為裝置的一部分或直接與裝置結合使用。可知的是，沒有特別顯示或描述這些元件可能存在的形式。再者，當提到某一層在另一層“之上”或“上方”，可代表兩層之間直接接觸或中間更插有其他元件或膜層。在本說明書中，所述之“一實施例”意指與該實施例有關之特定元件、結構或特徵，且可包含於至少一實施例中。因此，在本發明說明書之各處出現“在一實施例中”之措辭時，無需將其指向同一實施例。再者，在一或多個實施例中之特定元件、結構或特徵可以任何形式結合。值得注意的是，以下所示之圖示僅用以舉例說明，而未依原比例顯示。
第1-9圖顯示依照本發明一實施例之半導體裝置於積體電路製程中之各種階段之部分剖面圖。
參見第1圖，其顯示積體電路製造所使用之用於凸塊製造之半導體基材10，且積體電路可形成於基材10中及/或其上。半導體基材10可定義為任何包含半導體材料之結構，包含但不限於，塊材矽、半導體晶圓、絕緣層上覆(SOI)矽基材、矽鍺基材，或亦可使用其他包含第III族、第IV族及第V族之半導體材料。基材10可更包含多個隔離元件(未顯示)，例如淺溝槽隔離(STI)元件或矽局部氧化(LOCOS)元件。隔離元件可定義及隔離各種微機電元件(未顯示)。各種微機電元件，例如包含電晶體(例如金氧半場效電晶體(MOSFET)、互補式金氧半(CMOS)電晶體、p-通道及/或n-通道場效電晶體(PFETs/NFETs)等)、電阻、二極體、電容、電感、熔絲或其他合適元件，可形成於基材10中。可進行各種製程以形成各種微機電元件，包含沉積、蝕刻、佈植、光學微影、退火或其他合適製程。微機電元件彼此內連接以形成積體電路裝置，例如邏輯裝置、記憶體裝置(例如靜態隨機存取記憶體，SRAM)、射頻(RF)裝置、輸入/輸出(I/O)裝置、系統單晶片(SoC)裝置、前述之組合或其他合適型態之裝置。
半導體基材10更包含層間介電層及金屬化結構於積體電路上。金屬化結構中的層間介電層包含低介電常數介電材料、無摻雜玻璃(USG)、氮化矽、氮氧化矽或其他常用材料。低介電常數材料之介電常數(k值)可低於約3.9或低於約2.8。金屬化結構中金屬線可包含銅或銅合金。金屬化結構之形成細節係為本領域所屬通常知識者所公知。接墊區12為頂部金屬層，形成在最頂層的介電層中，為導電路徑的一部分，並視需要具有經平坦化製程(例如化學機械研磨)處理之暴露表面。用於接墊區之合適材料例如可包含，但不限於，銅、鋁、銅鋁合金(AlCu)、銅合金或其他合適導電材料。於接合製程中，以接墊區來連接晶片中積體電路至外部元件。
第1圖亦顯示保護層14形成於半導體基材10上，並暴露一部分的接墊區12，以進行隨後的銅柱凸塊製程。保護層14係由擇自於無摻雜矽玻璃(USG)、氮化矽、氮氧化矽或前述之組合的非有機材料形成。在某些實施例中，保護層14係由聚合物層形成，例如環氧樹脂、聚亞醯胺、苯環丁烯(benzocyclobutene，BCB)、聚苯噁唑(polybenzoxazole，PBO)或其類似物，或亦可使用其他較柔軟，通常為有機的介電材料。
第1圖更顯示形成包含第一凸塊下金屬層18及第二凸塊下金屬層20之凸塊下金屬層(UBM)16於基材10上。例如，凸塊下金屬層16形成於接墊區12之暴露部分上，並延伸覆蓋一部分的保護層14。第一凸塊下金屬層18，亦可視為擴散阻障層或黏著層，係由鈦、鉭、氮化鈦、氮化鉭或其類似物形成，其可由物理氣相沉積(PVD)或濺鍍製程形成。第一凸塊下金屬層18之厚度沉積至約500至2000之間，在某些實施例中，可為約1000。第二凸塊下金屬層20為經由物理氣相沉積或濺鍍所形成之銅種晶層，位於第一凸塊下金屬層18上。第二凸塊下金屬層20可由包含銀、鉻、鎳、錫、金或前述之組合的銅合金形成。第二凸塊下金屬層20之厚度可沉積至約500至10000之間，且在某些實施例中，可為約5000。在一實施例中，凸塊下金屬層16包含由鈦形成之第一凸塊下金屬層18及由銅形成之第二凸塊下金屬層20。
第1圖更顯示形成罩幕層22於凸塊下金屬層16上。罩幕層22係經圖案化以形成開口24於其中，暴露一部分的凸塊下金屬層16以形成銅柱凸塊。罩幕層22可為乾膜或光阻膜，其可由微影及/或蝕刻製程圖案化。
參見第2圖，其顯示在開口24中形成具有焊料潤濕性(solder wettability)的導電材料。在一實施例中，銅層26形成於開口中24中以接觸底下的凸塊下金屬層16。在本說明書中，所述之“銅層”可包含一膜層實質上包含純元素銅、含無可避免之雜質的銅、或含少量其他元素(例如鉭、銦、錫、鋅、錳、鉻、鈦、鍺、鍶、鉑、鎂、鋁或鋯)的銅合金。形成方法可包含濺鍍、印刷、電鍍、無電電鍍或化學氣相沉積(CVD)等方法。例如，進行電化學電鍍(ECP)以形成銅層26。在一實施例中，銅層厚度大於25 μm。在另一實施例中，銅層厚度約40-50 μm或約40-70 μm，或可更厚或更薄。
參見第3圖，進行移除罩幕層22之製程，因而暴露出銅層26之頂面26a及側壁表面26b。此後，自凸塊下金屬層16突出之銅層26稱為銅柱26。部分未由銅層26所覆蓋的第二凸塊下金屬層20在此步驟中亦暴露出來。在罩幕層22為乾膜之實施例中，可由鹼性溶液予以移除。如罩幕層22由光阻形成，可使用丙酮、N-甲基砒喀烷酮(n-methyl pyrrolidone，NMP)、二甲基亞碸(dimethyl sulfoxide,DMSO)、2-(2-氨基乙氧基)乙醇或其類似物予以移除。
接著參見第4圖，蝕刻第二凸塊下金屬層20之暴露部分以暴露其底下之第一凸塊下金屬層18未由銅柱26所覆蓋的部分18a。在一實施例中，由乾蝕刻或濕蝕刻移除一部份第二凸塊下金屬層20。例如，使用以氨為主的酸(ammonia-based acid)進行等向性濕蝕刻(由於所需時間很短，通常稱為快速蝕刻(flash etching))。因此，位於銅柱26底下之圖案化第二凸塊下金屬層20”係暴露出側壁表面20b。
參見第5圖，以例如毯覆式沉積形成保護層28於上述結構上。在某些實施例中，沉積保護層28以覆蓋銅柱26之頂面26a及側壁表面26b、圖案化第二凸塊下金屬層20”之側壁表面20b及第一凸塊下金屬層18之暴露部分18a。保護層28為非金屬材料層，例如介電材料層、聚合物材料層或前述之組合。保護層28可為單一材料層或多層結構，厚度可介於約500至10000之間。在一實施例中，保護層28可為由氮化矽、氧化矽、氮氧化矽、碳化矽、氧化矽及氮化矽交替膜層或前述之組合所形成之介電材料層，其可由包含熱氧化、低壓化學氣相沉積(LPCVD)、大氣壓化學氣相沉積(APCVD)或電漿增強式化學氣相沉積(PECVD)等技術形成。在一實施例中，保護層28為聚合物材料層，其係由例如環氧樹脂、聚亞醯胺、苯環丁烯(BCB)、聚苯噁唑(PBO)或其類似物形成，或亦可為其他較柔軟，通常為有機之介電材料形成。聚合物材料層性質柔軟，因而具有減少基材對應部分上的內部應力的功能。此外，聚合物層可輕易形成數十微米的厚度。
接著，參見第6圖，移除保護層28之某些區域，留下延著側壁表面26b及20b的部分，但移除銅柱頂面26a的部分，以形成側壁間隔物28a。在某些實施例中，側壁間隔物28a亦稱為側壁保護結構28a。側壁間隔物28a延伸至暴露部分18a之表面區域18a”。較佳是以微影及罩幕技術及乾蝕刻製程，例如反應性離子蝕刻(RIE)或其他電漿製程，形成側壁間隔物28a。
接著，在第7圖中，以側壁保護結構28a為罩幕，移除部分的第一凸塊下金屬層18，暴露出其底下的保護層14。以乾蝕刻製程，例如使用氯氣/三氯化硼(Cl2 /BCl3 )為蝕刻劑之標準反應性離子蝕刻製程，蝕刻第一凸塊下金屬層18。乾蝕刻製程移除大部分的暴露區域18a，除了鄰近於圖案化第二凸塊下金屬層20”之側壁表面20b並受側壁間隔物28a所覆蓋之表面區域18a”。既然表面區域18a自圖案化第二凸塊下金屬層20”之側壁表面20b延伸向外，圖案化第一凸塊下金屬層18”的面積大於圖案化第二凸塊下金屬層20”的面積。然而，在乾蝕刻製程中，某些側壁間隔物28b亦會自銅柱26之側壁表面26b之上部部分26b1 移除，造成側壁表面26b之上部部分26b1 在此步驟中被移除，僅有下部部分26 b2 受側壁間隔物28a覆蓋。暴露的上部部分26b1 之長度L約2至8 μm。
為了保護暴露的上部部分26b1 及覆蓋銅柱26之頂面26a，在銅柱26之頂面上進行形成頂蓋的製程。如第8圖所示，蓋層30形成於頂面26a上，並延伸覆蓋側壁表面26b之暴露的上部部分26b1 。蓋層30可作為阻障層以防止銅柱中的銅擴散至用以接合基材及外部元件之接合材料(例如焊料合金)中。防止銅的擴散增加了封裝體的可靠度及接合強度。蓋層30可包含鎳、錫、鉛錫合金(SnPb)、金、銀、鈀、銦、鎳鈀金(NiPdAu)、鎳金(NiAu)、以鎳為主之合金、以金為主之合金、以鈀為主之合金或其他類似材料，或由無電電鍍或浸鍍製程形成之合金。蓋層30之厚度約0.1至10 μm。在一實施例中，蓋層為三層結構，包含無電鍍鎳層、無電鍍鈀層及浸金層，其即為習知的無電鎳鈀浸金(ENEPIG)結構。在一實施例中，蓋層30可為雙層結構，包含無電鍍鎳層及無電鍍鈀層，稱為無電鎳鈀(ENEP)結構。在一實施例中，蓋層30為單層結構，包含無電鍍鎳層，即為習知的無電鎳(EN)結構。在一實施例中，蓋層30可為雙層結構，包含無電鍍鎳層及浸金層，即為習知的無電鎳浸金(ENIG)結構。
完成之凸塊結構32包含銅柱26、圖案化第二凸塊下金屬層20”、圖案化第一凸塊下金屬層18”、側壁間隔物28a及蓋層30。接著，切割基材10，並以設置於封裝基材或另一晶片上之焊球或銅凸塊將其封裝至另一晶片或封裝基材上。
第9圖顯示本發明實施例之覆晶組件之剖面圖。第8圖所示結構為上下翻轉，且底下接合至另一基材100。基材100可為封裝基材、基板(board)(例如印刷電路板)或其他基材。凸塊結構32透過各種導電連接點，例如接觸墊上及/或導線(conductive traces)之共焊層102，以形成共焊結構104，其連接基材10及100。共焊層102可為包含錫、鉛、銀、銅、鎳、鉍或前述之組合之共晶焊料(eutectic solder material)。在一實施例中，接合製程包含助焊(flux application)、晶片擺置(chip placement)、迴焊熔融之焊點(reflowing of melting solder joints)及/或清潔焊接殘餘物。積體電路基材10、焊接結構104及其他基材100可通稱為封裝組件200，或於本實施例中，稱為覆晶封裝組件。
本發明提供以非金屬材料所形成之側壁間隔物於銅柱側壁之下部部分，以防止銅柱側壁氧化並增加銅柱側壁與隨後所形成之底部填膠之間的黏著性。相較於接著需進行退火製程的傳統浸錫方法，非金屬側壁保護結構可調整基材應力，並預防焊料於迴焊製程中潤濕銅柱周圍之凸塊下金屬層，可應用至微細節距的凸塊結構。本發明亦提供由金屬形成之頂蓋於銅柱頂面及側壁上部上，以防止銅柱擴散至接合材料。既然頂蓋係是在側壁間隔物形成後，以無電電鍍或浸鍍製程形成，因此可減少像是光阻剝落或殘餘物等問題，且可良好地控制頂蓋沉積對齊銅柱之頂面及側壁上部。此外，使用無電鎳鈀浸金(ENEPIG)結構、無電鎳鈀(ENEP)結構、無電鎳(EN)結構或無電鎳浸金(ENIG)結構作為銅柱凸塊之頂蓋可減少凸塊崩塌的機率並增加封裝體之可靠度表現。
雖然本發明已以數個較佳實施例揭露如上，然其並非用以限定本發明，任何所屬技術領域中具有通常知識者，在不脫離本發明之精神和範圍內，當可作任意之更動與潤飾，因此本發明之保護範圍當視後附之申請專利範圍所界定者為準。
10‧‧‧基材
12‧‧‧接墊區
14‧‧‧保護層
16‧‧‧凸塊下金屬層
18、18”‧‧‧第一凸塊下金屬層
18a‧‧‧第一凸塊下金屬層之暴露部分
20、20”‧‧‧第二凸塊下金屬層
20b‧‧‧第二凸塊下金屬層側壁表面
26‧‧‧銅柱
26a‧‧‧銅柱頂面
26b‧‧‧銅柱側壁表面
26b1 ‧‧‧側壁表面上部
26b2 ‧‧‧側壁表面下部
28a‧‧‧側壁間隔物
30‧‧‧蓋層
32‧‧‧凸塊結構
100‧‧‧基材
102‧‧‧共焊層
104‧‧‧焊接結構
200‧‧‧封裝組件
第1~9圖顯示依照本發明一實施例之積體電路製程製造半導體裝置於各種階段之部分剖面圖。
10．．．基材
12．．．接墊區
14．．．保護層
18”．．．第一凸塊下金屬層
20”．．．第二凸塊下金屬層
20b．．．第二凸塊下金屬層側壁表面
26．．．銅柱
26a．．．側壁表面上部
26b2 ．．．側壁表面下部
28a．．．側壁間隔物
30．．．蓋層
32．．．凸塊結構

Claims (6)

  1. 一種積體電路裝置，包括：一半導體基材；一凸塊下金屬層，形成於該半導體基材上；一導電柱體，形成於該凸塊下金屬層上，且具有一頂面及一側壁表面，其中該側壁表面具有一鄰近該頂面之第一部分及一鄰近該凸塊下金屬層之第二部分；一非金屬保護結構，形成於該導電柱體之該側壁表面之第二部分上；以及一金屬蓋層，形成於該頂面上並延伸至該導電柱體之該側壁表面之第一部分上，其中該凸塊下金屬層包含：一第一凸塊下金屬層，形成於該半導體基材及導電柱體之間；及一第二凸塊下金屬層，形成於該第一凸塊下金屬層及該導電柱體之間；其中該第二凸塊下金屬層具有一側壁表面，且該第一凸塊下金屬層具有一表面區域自該第二凸塊下金屬層之該側壁表面向外延伸，其中該非金屬保護結構延伸覆蓋該第二凸塊下金屬層之該側壁表面及該第一凸塊下金屬層之該表面區域。
  2. 如申請專利範圍第1項所述之積體電路裝置，其中該非金屬保護結構包含一氮化矽層、一聚亞醯胺層或前述之組合。
  3. 如申請專利範圍第1項所述之積體電路裝置，其中 該金屬蓋層包含一無電鍍鎳層、一無電鍍鈀層、一浸金層或前述之組合。
  4. 一種封裝組件，包括：一第一基材；一凸塊下金屬層，形成於該第一基材上；一銅柱，形成於該凸塊下金屬層上，且具有一頂部、一鄰近該頂部之第一側壁部分、及一鄰近該第一基材之第二側壁部分；一非金屬保護結構，覆蓋該銅柱之該第二側壁部分；一金屬蓋層，覆蓋該銅柱之該頂部及該第一側壁部分；一第二基材；一共焊層，形成於該第二基材及該金屬蓋層之間；一第一凸塊下金屬層，形成於該第一基材及該銅柱之間；及一第二凸塊下金屬層，形成於該第一凸塊下金屬層及該銅柱之間；其中該第二凸塊下金屬層具有一側壁表面，且該第一凸塊下金屬層具有一表面區域自該第二凸塊下金屬層之該側壁表面向外延伸，其中該非金屬保護結構延伸覆蓋該第二凸塊下金屬層之該側壁表面及該第一凸塊下金屬層之該表面區域。
  5. 如申請專利範圍第4項所述之封裝組件，其中該非金屬保護結構包含一氮化矽層、一聚亞醯胺層或前述之組合。
  6. 如申請專利範圍第4項所述之封裝組件，其中該金屬蓋層包含：一無電鍍鎳層；一無電鍍鈀層形成於該無電鍍鎳層上；及一浸金層形成於該無電鍍鈀層上。
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