TWI413233B - 三維積體電路及其製造方法 - Google Patents

三維積體電路及其製造方法 Download PDF

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Publication number
TWI413233B
TWI413233B TW099144709A TW99144709A TWI413233B TW I413233 B TWI413233 B TW I413233B TW 099144709 A TW099144709 A TW 099144709A TW 99144709 A TW99144709 A TW 99144709A TW I413233 B TWI413233 B TW I413233B
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Taiwan
Prior art keywords
wafer
bump
metal
integrated circuit
metal bump
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TW099144709A
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English (en)
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TW201205769A (en
Inventor
Weng Jin Wu
Ying Ching Shih
Wen Chih Chiou
Shin Puu Jeng
Chen Hua Yu
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Taiwan Semiconductor Mfg
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Publication of TW201205769A publication Critical patent/TW201205769A/zh
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Publication of TWI413233B publication Critical patent/TWI413233B/zh

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    • H01L23/147—Semiconductor insulating substrates
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    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
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Description

三維積體電路及其製造方法
本發明係有關於一種積體電路，特別是有關於一種具有轉接板(interposer)的三維積體電路(three-dimensional integrated circuit,3DIC)及其製造方法。
由於各個電子部件(即，電晶體、二極體、電阻、電容等等)的集積度(integration density)持續的改進，使積體電路持續不斷的快速成長發展。主要來說，集積度的改進來自於最小特徵尺寸(minimum feature size)不斷縮小而容許更多的部件整合至既有的晶片面積內。
積體部件所佔的體積實際上位於半導體晶圓的表面。儘管微影(lithography)技術的精進為二維(2D)積體電路製作帶來相當大的助益，二維空間所能擁有的密度還是有其物理限制。這些限制之一在於製作這些部件所需的最小尺寸。再者，當更多的裝置放入一晶片中，需具有更複雜的電路設計。另一限制來自於當裝置數量增加時，其間的內連線(interconnection)的數量及長度大幅增加。而當內連線的數量及長度增加時，電路的時間延遲(RC delay)以及電量耗損均會增加。
因此，開始發展出三維積體電路(3DIC)，其中晶片的堆疊可透過用於堆疊晶片並將其連接至封裝基底的打線接合(wire bonding)、覆晶接合(flip-chip bonding) 及/或矽通孔電極(through-silicon via,TSV)。在傳統的晶片堆疊方法中，當二個晶片接合至另一晶片時便會產生問題，二個晶片可能需要不同的凸塊(bump)尺寸，其造成後續接合、焊料凸塊回流(reflowing)、底膠填充(underfill filling)及晶圓切割的困難度。
在本發明一實施例中，一種三維積體電路，包括：一第一晶片，具有一第一側及與其相對的一第二側，第一側具有一第一區及一第二區；一第一金屬凸塊，形成於第一晶片的第一側的第一區上，具有一第一平面尺寸；一第二晶片，透過第一金屬凸塊而接合至第一晶片的該第一側；一介電層，位於第一晶片的第一側上方，且包括直接位於第二晶片上的一第一部、環繞第二晶片的一第二部以及露出第一晶片的第一側的第二區的一開口；一第二金屬凸塊，形成於第一晶片的第一側的該第二區上且延伸進入介電層的開口內，具有一第二平面尺寸，第二平面尺寸大於第一平面尺寸；以及一電子部件，透過第二金屬凸塊而接合至第一晶片的第一側。
本發明另一實施例中，一種三維積體電路，包括：一第一晶片，包括一基底，其具有一第一側及與其相對的一第二側；一第一基底通孔電極及一第二基底通孔電極，形成於基底內；一第一凸塊下方金屬層及一第二凸塊下方金屬層，形成於基底的第一側上，且分別電性耦接至第一基底通孔電極及第二基底通孔電極；一介電 層，位於第一凸塊下方金屬層及第二凸塊下方金屬層上方，且具有露出至少一部分的第一凸塊下方金屬層的一第一開口以及露出至少一部分的第二凸塊下方金屬層的一第二開口，其中第一開口具有一第一平面尺寸且小於第二開口具有的一第二平面尺寸；一第一金屬凸塊，具有一第一高度且形成於露出的第一凸塊下方金屬層上並延伸進入介電層的第一開口內；一第二金屬凸塊，具有一第二高度且形成於露出的第二凸塊下方金屬層上並延伸進入介電層的第二開口內，其中第一高度低於第二高度；以及一第二晶片，透過第一金屬凸塊而接合至第一晶片。
本發明又一實施例中，一種三維積體電路製造方法，包括：提供一晶圓；在晶圓上方形成一第一凸塊下方金屬層及一第二凸塊下方金屬層；在第一凸塊下方金屬層上形成一第一金屬凸塊並與其電性耦接；將一第一晶片接合至第一金屬凸塊；形成一防焊塗佈層，以覆蓋第一晶片及晶圓；在防焊塗佈層內形成一開口，以露出至少一部分的第二凸塊下方金屬層；以及在開口內形成一第二金屬凸塊，且電性耦接至第二凸塊下方金屬層，其中第二金屬凸塊大於第一金屬凸塊。
以下說明本發明實施例之製作與使用。然而，可輕易了解本發明實施例提供許多合適的發明概念而可實施於廣泛的各種特定背景。所揭示的特定實施例僅僅用於 說明以特定方法製作及使用本發明，並非用以侷限本發明的範圍。
以下提供一種新的三維積體電路(3DIC)及其製造方法並說明一實施例之製造方法中各個階段。在各個圖式及實施例中，相同的部件係使用相同的標號。
請參照第1圖，提供一晶圓100，其內包括一基底10。基底10可由半導體材料所構成，例如矽、鍺化矽、碳化矽、砷化鍺或其它習用半導體材料。在一實施例中，晶圓100為一裝置晶圓，包括積體電路12，其可包括互補式金屬-氧化物-半導體(complementary metal-oxide-semiconductor,CMOS)電晶體、電阻、電感、及/或電容等等。在另一實施例中，晶圓100為一中介晶圓(interposer wafer)，其實質上不具有主動(active)裝置，例如電晶體。再者，中介晶圓100可具有或不具有被動裝置，例如電容、電阻及/或電感等等。因此，基底10可由介電材料所構成，例如氧化矽。
在基底10內形成基底通孔電極(through-substrate via,TSV)16，且可透過絕緣層(未繪示)而與基底10電性絕緣。基底通孔電極16自基底的一側貫穿至一相對側。在一實施例中，晶圓100為一裝置晶圓，且基底10具有一第一側10a及與第一側10a相對的一第二側10b。在積體電路製程中，第二側10b稱為基底10的前側，而第一側10a則稱為基底10的背側。在基底10的第二側10b上形成一內連結構18，其內包括金屬線及金屬介層窗(via)(未繪示)且電性耦接至積體電路12。金屬線 及金屬介層窗可由銅或銅合金所構成且可透過習知鑲嵌製程而形成。內連結構18可包括一習知內層介電(inter-layer dielectric,ILD)層及金屬層間介電(inter-metal dielectric,IMD)層，其可為具有低介電常數(例如，低於2.5，甚至低於2.0)的低介電常數介電層。在另一實施例中，晶圓100面向上的一側為裝置晶圓100的前側，而面向下的一側則為背側。金屬凸塊20形成於晶圓100的一表面，其可為焊料凸塊且電性耦接至積體電路12。
在基底10的第一側10a上的內連結構22。內連結構22包括一或多個介電層24以及位於介電層24內的金屬線24及金屬介層窗28。以下金屬線24及金屬介層窗28稱為重佈局線(redistribution line,RDL)。介電層24可由高分子材料、氮化矽、有機介電材料、或低介電常數材料等等所構成。重佈局線26及28可由銅或銅合金所構成，然而也可使用其他習用金屬材料，例如鋁及鎢等等。
形成凸塊下方金屬層(under-bump-metallurgy,UBM)30(包括30A及30B)且電性耦接至重佈局線26及28。凸塊下方金屬層(UBM)30可由鋁銅合金、鋁或銅等等所構成，且每一凸塊下方金屬層30也可包括位於含銅層上方的鎳層。形成介電層32以覆蓋凸塊下方金屬層30的邊緣部分，並透過凸塊下方金屬層開口34A及34B而露出凸塊下方金屬層30的中心部分。凸塊下方金屬層開口34A稱為大凸塊下方金屬層開口，而凸塊下方 金屬層開口34B稱為小凸塊下方金屬層開口，然而其可同時形成。在一實施例中，凸塊下方金屬層開口34A的平面尺寸(可為長度或寬度)L1大於凸塊下方金屬層開口34B的平面尺寸L2，而比率(L1/L2)的大於5或甚至大於10。承載板35可為一玻璃晶圓，且可接合至晶圓100的一側。
接下來，請參照第2圖，形成小金屬凸塊36，其中每一小金屬凸塊36的一部分位於小凸塊下方金屬層開口34B的其中一個內。小金屬凸塊36電性耦接至重佈局線26及28，且可電性耦接至基底通孔電極16。在一實施例中，小金屬凸塊36為焊料凸塊，例如共晶(eutectic)焊料凸塊。在另一實施例中，小金屬凸塊36為銅凸塊或其他金屬凸塊，其由金、銀、鎳、鎢、鋁及/或其合金所構成。當由銅所構成時，每一小金屬凸塊36可覆蓋一鎳層及/或位於鎳層上的一焊料上蓋層(未繪示)。
請參照第3圖，晶片38接合至小金屬凸塊36。晶片38可為一裝置晶片，其包括積體電路裝置形成於內，例如電晶體、電容、電感及電阻(未繪示)等等，且可為一邏輯晶片或一記憶體晶片。取決於小金屬凸塊36的結構，晶片38與小金屬凸塊36之間的接合可為焊料接合(solder bonding)或直接金屬對金屬(例如，銅對銅)接合。在將晶片38接合至小金屬凸塊36之後，在晶片38與晶圓100之間的間隙內形成底膠40，並接著進行固化。
請參照第4圖，在晶圓100及晶片38上塗覆一介電 層44。介電層44可為一防焊塗佈層(solder resist coating)，其可由光阻、高分子材料或類高分子材料所構成。另外，介電層44可由矽膠、旋塗玻璃(spin-on glass,SOG)或防焊材料等所構成。介電層44可包括直接位於晶片38上的一部分及環繞晶片38、小金屬凸塊36及底膠40的一部分。因此，介電層44保護小金屬凸塊36以及晶片38與晶圓100之間的接合。介電層44可利用旋轉塗佈(spin coating)、噴霧式塗佈(spray coating)或噴墨印刷(ink jet print)並接著進行固化步驟而形成。接著在介電層44內形成開口46，而露出凸塊下方金屬層30A，例如使用蝕刻。
接下來，請參照第5圖，在開口46內形成大金屬凸塊48且可與介電層44接觸。在一實施例中，大金屬凸塊48為焊料凸塊，其可由共晶焊料或無鉛焊料等所構成。在另一實施例中，大金屬凸塊48為銅凸塊且具有鎳層及/或焊料上蓋層形成於其上。
接下來，請參照第6圖，將電子部件50接合至大金屬凸塊48。在一實施例中，電子部件50為裝置晶片，其內包括積體電路，例如電晶體。在另一實施例中，電子部件50為封裝基板。在大金屬凸塊48為銅凸塊的實施例中，可進行回流(re-flow)製程，以結合電子部件50與大金屬凸塊48。在進行接合之後，電子部件50的底表面可高於介電層44的上表面。在電子部件50與晶圓100之間的間隙內以及大金屬凸塊48之間填入底膠52。可以理解的是雖然圖式中僅有一晶片38及一晶片(電子部件) 50，然而可具有多個晶片38及晶片50接合至晶圓100。此時可進行晶片切割(die saw)，以將晶圓100切割成多個晶片，每一晶片100’(請參照第7圖)包括晶圓100的一部分、其中一個晶片38以極其中一個晶片50。
在將電子部件50接合至晶圓100之後，大金屬凸塊48的平面尺寸(其為長度或寬度)L3大於小金屬凸塊的平面尺寸L4，而比率(L3/L4)的大於5或甚至大於15。再者，大金屬凸塊48的高度H大於介電層44的厚度。
請參照第7圖，將承載板35卸離(de-bonded)，並將電子部件56(可為裝置晶片或封裝基板)接合至晶圓100，其中電子部件56及晶片38位於晶圓100(或晶片100’)的相對側。如第8圖所示，當電子部件56為裝置晶片，可形成成形材料(molding compound)58，以覆蓋電子部件56。若尚未進行晶片切割，可接著進行晶片切割，以將晶圓100分割成多個晶片。
在上述實施例中，大金屬凸塊與小金屬凸塊係形成於同一三維積體電路(3DIC)內。由於小金屬凸塊受到介電材料保護，因此可形成大金屬凸塊，且可在形成及接合小金屬凸塊之後，將另一晶片接合至大金屬凸塊，且在接合大金屬凸塊期間不會損及小金屬凸塊。此增加了晶片堆疊的彈性。
雖然本發明已以較佳實施例揭露如上，然其並非用以限定本發明，任何所屬技術領域中具有通常知識者，在不脫離本發明之精神和範圍內，當可作更動、替代與潤飾。再者，本發明之保護範圍並未侷限於說明書內所 述特定實施例中的製程、機器、製造、物質組成、裝置、方法及步驟，任何所屬技術領域中具有通常知識者可從本發明揭示內容中理解現行或未來所發展出的製程、機器、製造、物質組成、裝置、方法及步驟，只要可以在此處所述實施例中實施大體相同功能或獲得大體相同結果皆可使用於本發明中。因此，本發明之保護範圍包括上述製程、機器、製造、物質組成、裝置、方法及步驟。另外，每一申請專利範圍構成個別的實施例，且本發明之保護範圍也包括各個申請專利範圍及實施例的組合。
10‧‧‧基底
10a‧‧‧第一側
10b‧‧‧第二側
12‧‧‧積體電路
16‧‧‧基底通孔電極
18、22‧‧‧內連結構
20‧‧‧金屬凸塊
24、32、44‧‧‧介電層
26‧‧‧金屬線/重佈局層
28‧‧‧金屬介層窗/重佈局層
30、30A、30B‧‧‧凸塊下方金屬層
34A、34B‧‧‧凸塊下方金屬層開口
35‧‧‧承載板
36‧‧‧小金屬凸塊
38、100’‧‧‧晶片
40、52‧‧‧底膠
46‧‧‧開口
48‧‧‧大金屬凸塊
50、56‧‧‧電子部件/晶片
58‧‧‧成形材料
100‧‧‧晶圓
H‧‧‧高度
L1、L2、L3、L4‧‧‧平面尺寸
T‧‧‧厚度
第1至8圖係繪示出根據一實施例之具有堆疊晶片的三維積體電路製造方法中各個階段的剖面示意圖，其中具有不同尺寸的金屬凸塊形成於同一晶片/晶圓上。
10‧‧‧基底
12‧‧‧積體電路
16‧‧‧基底通孔電極
18、22‧‧‧內連結構
20‧‧‧金屬凸塊
24、32、44‧‧‧介電層
30A、30B‧‧‧凸塊下方金屬層
36‧‧‧小金屬凸塊
38、100’‧‧‧晶片
40、52‧‧‧底膠
48‧‧‧大金屬凸塊
50、56‧‧‧電子部件/晶片
58‧‧‧成形材料

Claims (10)

  1. 一種三維積體電路，包括：一第一晶片，具有一第一側及與其相對的一第二側，該第一側具有一第一區及一第二區；一第一金屬凸塊，形成於該第一晶片的該第一側的該第一區上，具有一第一平面尺寸；一第二晶片，透過該第一金屬凸塊而接合至該第一晶片的該第一側；一介電層，位於該第一晶片的該第一側上方，且包括直接位於該第二晶片上的一第一部、環繞該第二晶片的一第二部以及露出該第一晶片的該第一側的該第二區的一開口；一第二金屬凸塊，形成於該第一晶片的該第一側的該第二區上且延伸進入該介電層的該開口內，具有一第二平面尺寸，該第二平面尺寸大於該第一平面尺寸；以及一第一電子部件，透過該第二金屬凸塊而接合至該第一晶片的該第一側。
  2. 如申請專利範圍第1項所述之三維積體電路，其中該介電層包括防焊材料、光阻、高分子材料及矽膠中的至少一種。
  3. 如申請專利範圍第1項所述之三維積體電路，其中該第二金屬凸塊的高度大於該第一金屬凸塊的高度。
  4. 如申請專利範圍第1項所述之三維積體電路，其中該第二平面尺寸與該第一平面尺寸的比率大於5。
  5. 如申請專利範圍第1項所述之三維積體電路，更包括一底膠材料，形成於該第一電子部件與該介電層之間的空間內。
  6. 如申請專利範圍第1項所述之三維積體電路，其中該第一晶片包括形成於該第一晶片內且電性耦接至該第一金屬凸塊的一第一基底通孔電極，以及形成於該第一晶片內且電性耦接至該第二金屬凸塊的一第二基底通孔電極。
  7. 如申請專利範圍第6項所述之三維積體電路，更包括一第二電子部件，接合至該第一晶片的該第二側，且透過該第二基底通孔電極而電性耦接至該第一電子部件。
  8. 如申請專利範圍第6項所述之三維積體電路，更包括：一第三晶片，透過該第二金屬凸塊而接合至該第一晶片；以及一電子部件，接合至該第一晶片的該第二側，且透過該第二基底通孔電極而電性耦接至該第三晶片。
  9. 一種三維積體電路製造方法，包括：提供一晶圓；在該晶圓上方形成一第一凸塊下方金屬層及一第二凸塊下方金屬層；在該第一凸塊下方金屬層上形成一第一金屬凸塊並與其電性耦接；將一第一晶片接合至該第一金屬凸塊； 形成一防焊塗佈層，以覆蓋該第一晶片及該晶圓；在該防焊塗佈層內形成一開口，以露出至少一部分的該第二凸塊下方金屬層；以及在該開口內形成一第二金屬凸塊，且電性耦接至該第二凸塊下方金屬層，其中該第二金屬凸塊大於該第一金屬凸塊。
  10. 如申請專利範圍第9項所述之三維積體電路製造方法，更包括：在該晶圓內形成複數個基底通孔電極；以及將一電子部件接合至該第二金屬凸塊，該電子部件擇自於由裝置晶片及封裝基板所組成的群族，該第二金屬凸塊的平面尺寸與該第一金屬凸塊的平面尺寸的比率大於5。
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US8669174B2 (en) 2014-03-11
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