TW201924009A - 半導體結構及其形成方法 - Google Patents

半導體結構及其形成方法 Download PDF

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TW201924009A
TW201924009A TW107115538A TW107115538A TW201924009A TW 201924009 A TW201924009 A TW 201924009A TW 107115538 A TW107115538 A TW 107115538A TW 107115538 A TW107115538 A TW 107115538A TW 201924009 A TW201924009 A TW 201924009A
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Taiwan
Prior art keywords
integrated circuit
conductive
layer
circuit die
opening
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TW107115538A
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English (en)
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TWI752225B (zh
Inventor
余振華
郭宏瑞
何明哲
李宗徽
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台灣積體電路製造股份有限公司
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Priority claimed from US15/907,717 external-priority patent/US11410918B2/en
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Publication of TW201924009A publication Critical patent/TW201924009A/zh
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Abstract

一種積體電路封裝及其形成方法。方法包括於載具上方形成第一重佈線層，第一重佈線層包括接觸墊以及焊墊。導電柱形成於接觸墊上方。積體電路晶粒之背側表面使用焊料接合貼附至焊墊。密封體沿著導電柱之側壁及積體電路晶粒之側壁形成，積體電路晶粒的前側表面實質上與密封體之最頂表面及導電柱之最頂表面齊平。第二重佈線層形成於積體電路晶粒之前側表面、密封體之最頂表面以及導電柱之最頂表面之上方。

Description

積體電路封裝及其形成方法
半導體元件用於多種電子應用中，諸如個人電腦、蜂巢式電話、數位攝影機以及其他電子裝備。通常藉由在半導體基底上依序沈積絕緣層或介電層、導電層以及半導電材料層以及使用微影技術圖案化各種材料層來製造半導體元件，以在其上形成電路組件以及構件。通常在單一半導體晶圓上製造幾十或幾百個積體電路。藉由沿著切割道切割積體電路而使個別晶粒單一化。隨後以多晶片模組形式或以其他類型的封裝形式單獨地封裝個別晶粒。
半導體行業由於各種電子組件（例如電晶體、二極體、電阻器、電容器等）之積體密度的持續改良而經歷快速增長。在大多數情況下，積體密度之改良來自於最小特徵尺寸之反覆減小（例如使半導體製程節點朝向次20奈米節點收縮），其允許更多組件整合於給定區域中。隨著最近對小型化、較高速度及較大頻寬以及較低功率消耗及延遲之需求增長，對半導體晶粒之更小且更具創造性封裝技術的需要也隨著增長。
隨著半導體技術進一步發展，堆疊半導體元件（例如三維積體電路（three dimensional integrated circuit，3DIC））已作為進一步縮小半導體元件之實體大小的有效替代物。在堆疊半導體元件中，諸如邏輯、記憶體、處理器電路以及其類似者之主動電路是被製造於不同半導體晶圓上。兩個或大於兩個半導體晶圓可安裝或堆疊於彼此之頂部上以進一步減小半導體元件之外觀尺寸。疊層封裝（package-on-package，POP）元件是一種類型之三維積體電路（3DIC），其中晶粒經封裝且隨後與另一或多個封裝晶粒一起封裝。晶片封裝（chip-on-package，COP）元件是另一類型之三維積體電路（3DIC），其中晶粒經封裝且隨後與另一或多個晶粒一起封裝。
以下揭露內容提供用於實施本發明之不同特徵的許多不同實施例或實例。下文描述組件及配置的特定實例以簡化本發明。當然，此等組件及配置僅為實例且不意欲為限制性的。舉例而言，在以下描述中，第一構件在第二構件上方或上的形成可包括第一構件以及第二構件直接接觸地形成的實施例，且亦可包括額外構件可在第一構件與第二構件之間形成使得第一構件與第二構件可不直接接觸的實施例。另外，本發明可在各種實例中重複圖式元件符號及/或字母。此重複是出於簡單性及清晰性之目的，且本身並不指示所論述之各種實施例及/或組態之間的關係。
此外，在本文中為了易於描述，可使用諸如「在...下方」、「下方」、「下部」、「在...上方」、「上部」以及其類似術語之空間相對術語來描述如在圖式中所展示的一個元件或構件與另一元件或構件的關係。除了諸圖中所描繪的定向以外，空間相對術語亦意欲涵蓋元件在使用或操作中的不同定向。設備可以其他方式定向（旋轉90度或處於其他定向），且本文中所使用的空間相對描述詞可同樣相應地進行解譯。
實施例將以關於特定情形之實施例來描述，即積體電路封裝，諸如整合扇出型（integrated fan-out，InFO）封裝件及包括整合扇出型封裝件之疊層封裝。然而，其他實施例亦可應用於其他電連接組件，包括但不限於在組合封裝、在處理基底、插入件（interposer）或其類似物中，或安裝輸入組件、板、晶粒或其他組件中，或用於連接任何類型的積體電路或電組件之封裝或安裝組合的疊層封裝組合件、晶粒對晶粒組合件、晶圓間組合件、晶粒對基底組合件。
本文所描述之各種實施例允許使用晶粒貼附方法形成積體電路封裝，其允許藉由減小或去除在晶粒與下方的層（諸如下方的重佈線層）之間的重疊偏移來減小或避免晶粒對準問題，且允許降低積體電路封裝之熱阻。本文所描述的各種實施例亦允許模塑通孔直接在下方的重佈線層上形成，且藉由修改在重佈線層形成期間所使用的晶種層來減小接觸電阻。本文所描述之各種實施例進一步允許減少製造步驟之數目及製造成本以形成積體電路封裝。
圖1至圖10是根據一些實施例在製造積體電路晶粒期間之各種處理步驟的截面圖。參看圖1，說明工件100之一部分具有藉由切割道103（亦稱作分割線或分割道）分離的晶粒區域101。如下文更詳細地描述，將沿著切割道103分割工件100以形成個別積體電路晶粒（諸如圖9中所說明之積體電路晶粒901）。在一些實施例中，工件100包括基底105、在基底105上之一或多個主動元件及/或被動元件107，以及在基底105及一或多個主動元件及/或被動元件107上方之內連線結構109。
在一些實施例中，基底105可由矽形成，但其亦可由其他III族、IV族及/或V族元素（諸如矽、鍺、鎵、砷以及其組合）形成。基底105亦可為絕緣層上矽（silicon-on-insulator，SOI）的形式。絕緣層上矽基底可包括形成於絕緣層（例如埋入式氧化物及/或類似物）上方的半導體材料（例如矽、鍺及/或類似物）層，而所述絕緣層形成於矽基底上。另外，可使用的其他基底包括多層基底（multi-layered substrate）、梯度基底（gradient substrate）、混合定向基底（hybrid orientation substrate）、其任何組合及/或其類似者。
在一些實施例中，一或多個主動元件及/或被動元件107可形成於在基底105上且可包括各種n型金屬氧化物半導體（n-type metal-oxide semiconductor，NMOS）元件及/或p型金屬氧化物半導體（p-type metal-oxide semiconductor，PMOS）元件，諸如電晶體、電容器、電阻器、二極體、光電二極體、熔斷器及/或其類似者。在一些實施例中，一或多個主動元件及/或被動元件107可使用任何可接受的方法形成。本領域的普通技術人員將瞭解上文之實例僅出於說明的目的提供且不意謂以任何方式限制本發明。其他電路亦可形成為適合於給定應用。
在一些實施例中，內連線結構109可形成於基底105以及一或多個主動元件及/或被動元件107上方。內連線結構109電互連一或多個主動元件及/或被動元件107以在工件100內形成功能電路。內連線結構109可包括一或多個介電層（圖中未示）以及在對應介電層內之一或多個金屬化層（圖中未示）。一或多個介電層可包括形成於基底及一或多個主動元件及/或被動元件上方的層間介電（inter-layer dielectric，ILD）/金屬間介電（inter-metal dielectric，IMD）層。層間介電/金屬間介電可藉由本領域中所知的任何適合的方法（諸如旋塗式塗覆方法（spin-on coating method）、化學氣相沈積（chemical vapor deposition，CVD）、電漿增強型化學氣相沈積（plasma enhanced CVD，PECVD）、其組合或其類似方法）而由例如低介電系數（low-K）介電材料（諸如磷矽酸鹽玻璃（phosphosilicate glass，PSG）、硼磷矽酸鹽玻璃（borophosphosilicate glass，BPSG）、FSG、SiOx Cy 、旋塗式玻璃（Spin-On-Glass）、旋塗式聚合物（Spin-On-Polymers）、矽碳材料（silicon carbon material）、其化合物、其複合物、其組合或其類似者）形成。在一些實施例中，一或多個金屬化層可包括使用（例如）金屬鑲嵌製程、雙金屬鑲嵌製程、其組合或其類似者形成於層間介電/金屬間介電中的各種導電特徵（諸如層間介電中之導電接觸點(conductive contacts)，以及金屬間介電中之導電線及通孔）。在一些實施例中，導電特徵可包括銅、銅合金、銀、金、鎢、鉭、鋁、其組合或其類似物。
在一些實施例中，接觸墊111形成於內連線結構109之上方。接觸墊111可經由內連線結構109之一或多個金屬化層電耦接至一或多個主動元件及/或被動元件107。在一些實施例中，接觸墊111可包括導電材料，諸如鋁、銅、鎢、銀、金、其組合或其類似物。在一些實施例中，導電材料可使用例如物理氣相沈積（physical vapor deposition，PVD）、原子層沈積（atomic layer deposition，ALD）、電化學電鍍、無電電鍍、其組合或其類似者形成於內連線結構109上方。隨後，導電材料經圖案化以形成接觸墊111。在一些實施例中，導電材料可使用適合的微影技術及蝕刻技術而圖案化。一般而言，微影技術涉及沈積光阻材料（圖中未示），光阻材料隨後經照射（曝光）並被顯影以移除光阻材料的一部分。剩餘光阻材料保護下方的材料（諸如接觸墊111之導電材料）以免於後續處理步驟（諸如蝕刻）。適合的蝕刻製程（諸如反應性離子蝕刻（reactive ion etch，RIE）或其他乾式蝕刻、等向性濕式蝕刻或非等向性濕式蝕刻或任何其他適合的蝕刻）或圖案化製程可施加於導電材料以移除導電材料被暴露的部分並且形成接觸墊111。隨後，可使用例如灰化製程以及隨後進行的濕式清潔製程來移除光阻材料。
進一步參看圖1，鈍化層113形成於內連線結構109以及接觸墊111上方。在一些實施例中，鈍化層113可包括諸如氮化矽、氧化矽、磷矽酸鹽玻璃（PSG）、硼矽酸鹽玻璃（borosilicate glass，BSG）、摻硼磷矽酸鹽玻璃（boron-doped phosphosilicate glass，BPSG）其組合或其類似者的一或多個非光可圖案化介電材料層，且可使用化學氣相沈積、物理氣相沈積、原子層沈積、旋塗式塗覆製程、其組合或其類似方法形成。在其他實施例中，鈍化層113可包括諸如聚苯并噁唑（polybenzoxazole，PBO）、聚醯亞胺（polyimide，PI）、苯并環丁烯（benzocyclobutene，BCB）、其組合或其類似者的一或多個光可圖案化絕緣材料層，且可使用旋塗式塗覆製程或其類似方法形成。可使用類似於光阻材料之微影方法來圖案化這些光可圖案化介電材料。
在一些實施例中，開口115形成於鈍化層113中以暴露接觸墊111之部分。在鈍化層113包括非光可圖案化介電材料的一些實施例中，鈍化層113可使用適合的微影方法以及蝕刻方法而圖案化。在一些實施例中，光阻材料（圖中未示）形成於鈍化層113上方。隨後照射（曝光）且顯影光阻材料以移除光阻材料之一部分。隨後，使用（例如）適合的蝕刻製程來移除鈍化層113被暴露的部分以形成開口115。
參看圖2，緩衝層201形成於鈍化層113以及接觸墊111上方。在一些實施例中，緩衝層201可包括諸如聚苯并噁唑（PBO）、聚醯亞胺（PI）、苯并環丁烯（BCB）、其組合或其類似者的一或多個光可圖案化絕緣材料層，且可使用旋塗式塗覆製程或其類似方法形成。在一些實施例中，緩衝層201經圖案化以形成緩衝層201中之開口203且暴露接觸墊111。在一些實施例中，可使用適當的微影技術形成開口203，以將緩衝層201曝光。在一些實施例中，在緩衝層201曝光之後，顯影及/或固化緩衝層201。
參看圖3，晶種層301全面性沈積於緩衝層201上方及開口203中。晶種層301可包括銅、鈦、鎳、金、錳、其組合或其類似物的一或多個層，且可藉由原子層沈積、物理氣相沈積、濺鍍、其組合或其類似方法形成。在一些實施例中，晶種層301包括形成於鈦層上的銅層。
參看圖4，其中具有開口403之圖案化罩幕401形成於晶種層301上方。在一些實施例中，圖案化罩幕401包括光阻材料或任何光可圖案化材料。在一些實施例中，圖案化罩幕401之材料經沈積、照射（曝光）以及顯影以移除材料之部分並且形成開口403，藉此形成圖案化罩幕401。在所說明的實施例中，所述開口403暴露形成於開口203中之接觸墊111上方的晶種層301之部分。如下文更詳細地論述，導電柱（諸如圖5中所說明之導電柱501）將形成於開口403中以提供電連接至接觸墊111。
參看圖5，導電柱501形成於由開口403以及開口203（參看圖4）形成的組合開口之中。在一些實施例中，用諸如銅、鎢、鋁、銀、金、其組合或其類似物之導電材料填充組合開口，使用電化學電鍍製程、無電電鍍製程、原子層沈積、物理氣相沈積、其組合或其類似方法以形成導電柱501。在一些實施例中，導電柱501部分地填充組合開口，且組合開口之剩餘部分用焊料材料填充以在導電柱501上方形成焊料層503。在一些實施例中，焊料材料可為諸如PbSn組合物的鉛類焊料，包括InSb、錫、銀及銅（「SAC」）組合物的無鉛焊料，以及具有普通熔點且在電應用中形成導電焊料連接之其他共晶材料（eutectic materials）。對於無鉛焊料，作為實例，可使用變化組合物的SAC焊料，諸如SAC 105（Sn 98.5%、Ag 1.0%、Cu 0.5%）、SAC 305以及SAC 405。無鉛焊料亦包括SnCu化合物而無需使用銀（Ag），以及SnAg化合物而無需使用銅（Cu）。在一些實施例中，焊料層503可使用蒸鍍、電化學電鍍製程、無電電鍍製程、印刷、焊料轉移、其組合或其類似者形成。
參看圖6，在形成導電柱501以及焊料層503之後，移除圖案化罩幕401（參看圖5）。在一些實施例中，圖案化罩幕401包括可使用例如灰化製程以及隨後進行的濕式清潔製程移除之光阻材料。隨後，使用例如適合的蝕刻製程移除晶種層301被暴露的部分。在一些實施例中，在移除晶種層301被暴露的部分之後，晶粒區域101中的每一個可電測試以識別良裸晶粒（known good die，KGD）以供進一步處理。在一些實施例中，電測試系統之探測卡可在電測試製程期間接觸焊料層503。在一些實施例中，在完成電測試製程之後，自對應導電柱501移除焊料層503。在一些實施例中，可使用適合的移除製程（諸如適合的蝕刻製程）來移除焊料層503。在所說明的實施例中，緊接地在完成電測試製程之後移除焊料層503。在其他實施例中，可在隨後的製造製程步驟（諸如在後續封裝步驟期間）中移除焊料層503。
參看圖7，在移除焊料層503之後，保護層701形成於導電柱501上方且包圍導電柱501。在一些實施例中，保護層701可包括諸如聚苯并噁唑（PBO）、聚醯亞胺（PI）、苯并環丁烯（BCB）、其組合或其類似者的一或多個光可圖案化絕緣材料層，且可使用旋塗式塗覆製程或其類似方法形成。
進一步參看圖7，在一些實施例中，適合背面研磨基底105（例如）以減少工件100之厚度以及隨後形成的積體電路晶粒之厚度。在此等實施例中，執行薄化製程，其中諸如背面研磨（back grinding，BG）膠帶之膠帶703可被施加至保護層701之頂部表面，且基底105之背側105b藉由研磨、蝕刻、化學機械研磨（CMP）製程、其組合或其類似者薄化。在一些實施例中，膠帶703保護工件100免受由研磨/蝕刻流體及/或殘渣所導致的污染。
參看圖8，在完成上述之薄化製程之後，晶種層801形成於基底105之背側105b上。在一些實施例中，晶種層801可使用與上文參看圖3所述之晶種層301類似的材料以及方法形成，且在本文中不重複描述。在一些實施例中，晶種層801可具有介於約0.06微米與約1.1微米之間的厚度。在一些實施例中，晶種層801可包括厚度介於約0.01微米與約0.1微米之間的鈦層以及厚度介於約0.05微米與約1微米之間的銅層
參看圖9，在形成晶種層801之後，移除膠帶703（參看圖8）並且使工件100單一化，以形成個別積體電路晶粒901。在一些實施例中，工件100可使用黏著劑905貼附至框架903以製備用於後續分割製程的工件100。在一些實施例中，框架903可為膜框架或任何適合的載具（carrier）以為後續操作（諸如分割）提供機械支撐。黏著劑905可為晶粒貼附膜、分割膜或任何適合的黏著劑、環氧樹脂、紫外線（ultraviolet，UV）膠（在暴露於紫外線輻射時失去其黏著特性）或其類似者，且可使用沈積製程、旋塗製程、印刷製程、疊層製程或其類似製程來形成。在一些實施例中，黏著劑905可具有多層結構且可包括釋放層（圖中未示）。釋放層可有助於在完成分割製程之後自框架903安全地移除個別積體電路晶粒901。在一些實施例中，釋放層可為紫外線類型，其中釋放層之黏著強度實質上在將釋放層暴露於紫外線輻射之後降低。在其他實施例中，釋放層可為熱類型(thermal type)，其中釋放層之黏著強度實質上在將釋放層暴露於適合的熱源之後降低。在一些實施例中，工件100可例如藉由切割、雷射燒蝕（laser ablation）、其組合或其類似者而單一化為個別積體電路晶粒901。
如9圖中所示，每一積體電路晶粒901包括單個鈍化層（諸如鈍化層113）、單個緩衝層（諸如緩衝層201）、兩個接觸墊（諸如接觸墊111）、兩個導電柱（諸如導電柱501）以及單個保護層（諸如保護層701）。本領域技術人員可知鈍化層、緩衝層、接觸墊、導電柱以及保護層之數目僅是為了說明而提供且不限制本發明之範疇。在其他實施例中，每一積體電路晶粒901可包括視積體電路晶粒901的設計要求而定的適當數目之鈍化層、緩衝層、接觸墊、導電柱以及保護層。
參看圖10，在將工件100單一化為積體電路晶粒901之後，將焊料膏1001施加至每一積體電路晶粒901之晶種層801。在一些實施例中，焊料膏1001可使用印刷製程、浸漬製程、其組合或其類似製程施加至晶種層801。在一些實施例中，焊料膏1001可包括焊料材料以及助熔劑（flux）。在其他實施例中，焊料膏1001可為無助熔劑的焊料膏。在一些實施例中，焊料膏1001之焊料材料可包括與上文參看圖5所描述之焊料層503類似的材料且在本文中不重複描述。在一些實施例中，焊料膏1001可具有介於約5微米與約100微米之間的厚度。
進一步參看圖9以及圖10，在所說明的實施例中，在使工件100單一化為積體電路晶粒901之後將焊料膏1001施加至積體電路晶粒901。在其他實施例中，可在使工件100單一化為積體電路晶粒901之前將焊料膏1001施加至工件100。在此等實施例中，在單一化製程期間，分割鋸（dicing saw）可能會受焊料膏1001污染。在一些實施例中，可對分割鋸執行適合的清理製程以自分割鋸移除污染物。如下文更詳細地描述，可使用焊料膏1001以在後續封裝步驟期間將積體電路晶粒901貼附至下方的重佈線層。
圖11至圖21是根據一些實施例在使用圖1至圖10中製造之積體電路晶粒來製造積體電路封裝期間之各種處理步驟的截面圖。首先參看圖11，在一些實施例中，釋放層1103形成於載具1101上方，且絕緣層1105形成於釋放層1103上方以開始形成積體電路封裝。在一些實施例中，載具1101可由石英、玻璃或其類似者形成，並為後續操作提供機械支撐。在一些實施例中，釋放層1103可包括光熱轉化（light to heat conversion，LTHC）材料、紫外線黏著劑、聚合物層或其類似者，且可使用旋塗式塗覆製程、印刷製程、疊層製程或其類似製程來形成。在釋放層1103由光熱轉化材料形成之一些實施例中，釋放層1103在暴露於光時部分地或完全地失去其黏著強度，且載具1101可很容易地自後續形成結構之背側移除。在一些實施例中，絕緣層1105可使用與上文參看圖2所描述之緩衝層201類似的材料以及方法形成且在本文中不重複描述。
進一步參看圖11，晶種層1107形成於絕緣層1105上方。在一些實施例中，晶種層1107可使用與上文參看圖3所描述之晶種層301類似的材料以及方法形成且在本文中不重複描述。在一些實施例中，晶種層1107可包括厚度介於約0.01微米與約0.1微米之間的鈦層以及厚度介於約0.06微米與約1.1微米之間的銅層。在一些實施例中，鈦層可省略，且晶種層1107可包括厚度介於約0.12微米與約0.7微米之間的銅層。在此等實施例中，藉由省略鈦層，可降低所得重佈線層之接觸電阻。
在一些實施例中，其中具有開口1111以及開口1113的圖案化罩幕1109形成於晶種層1107上方。在一些實施例中，圖案化罩幕1109可使用與上文參看圖4所描述之圖案化罩幕401類似的材料以及方法形成且在本文中不重複描述。在所說明的實施例中，圖案化罩幕401包括光阻材料且使用適合的微影方法而圖案化。如下文極詳細地描述，導電材料形成於開口1111以及開口1113中以形成重佈線層。在一些實施例中，形成於開口1111中之導電材料可形成接觸墊，其提供對後續形成導電通孔的電連接。在一些實施例中，形成於開口1113中之導電材料可形成焊墊，積體電路晶粒後續貼附至所述焊墊。在一些實施例中，開口1111之寬度W1 可小於開口1113之寬度W2 。在一些實施例中，寬度W1 可介於約120微米與約500微米之間。在一些實施例中，寬度W2 可介於約0.5毫米與約2毫米之間。在一些實施例中，比率W1 /W2 可介於約0.06與約1之間。
參看圖12，導電材料1201形成於開口1111以及開口1113中。在一些實施例中，導電材料1201可包括銅、鎢、鋁、銀、金、其組合或其類似者，且可使用電化學電鍍製程、無電電鍍製程、原子層沈積、物理氣相沈積、其組合或其類似者來形成。在一些實施例中，導電材料1201包括形成於開口1111內之第一部分1201a以及形成於開口1113內之第二部分1201b。在一些實施例中，導電材料1201之第一部分1201a可具有實質上與開口1111相同的寬度。在一些實施例中，導電材料1201之第二部分1201b可具有實質上與開口1113相同的寬度。
參看圖13，在形成導電材料1201之後，移除圖案化罩幕1109（參看圖12）。在一些實施例中，圖案化罩幕1109可使用與上文參看圖6所描述之圖案化罩幕401類似的方法移除且在本文中不重複描述。在一些實施例中，在移除圖案化罩幕1109之後，其中具有開口1303的圖案化罩幕1301形成於晶種層1107以及導電材料1201上方。在一些實施例中，圖案化罩幕1301可使用與上文參看圖4所描述之圖案化罩幕401類似的材料以及方法形成且在本文中不重複描述。在所說明的實施例中，圖案化罩幕1301包括乾式光可圖案化膜，其層合在晶種層1107以及導電材料1201上方且其使用適合的微影方法而圖案化。在一些實施例中，圖案化罩幕1301保護導電材料1201之第二部分1201b且經由對應開口1303暴露導電材料1201之第一部分1201a。在一些實施例中，開口1303可具有介於約100微米與約300微米之間的寬度W3 。
參看圖14，導電柱1401形成於開口1303中。在一些實施例中，導電柱1401可使用與上文參看圖5所描述之導電柱501類似的材料以及方法形成且在本文中不重複描述。在一些實施例中，導電柱1401亦可被稱作導電通孔（conductive vias）1401或模塑通孔（through molding vias）1401。在一些實施例中，導電柱1401可具有實質上與開口1303相同的寬度。
參看圖15，在形成導電柱1401之後，移除圖案化罩幕1301（參看圖14）。在圖案化罩幕1301包括乾式光可圖案化膜的一些實施例中，可使用例如灰化製程以及隨後進行的濕式清潔製程來移除圖案化罩幕1301。隨後，移除晶種層1107之經暴露部分。在一些實施例中，晶種層1107之經暴露部分可使用與上文參看圖6所描述之晶種層301之被暴露部分類似的方法移除且在本文中不重複描述。在一些實施例中，在移除製程之後，受導電材料1201之第一部分1201a保護的晶種層1107之第一部分1107a以及受導電材料1201之第二部分1201b保護的晶種層1107之第二部分1107b保留。在一些實施例中，導電材料1201以及晶種層1107之剩餘部分可共同地被稱作重佈線層（redistribution layer，RDL）1501。在一些實施例中，重佈線層 1501以及絕緣層1105可共同地被稱作重佈線結構1503。在一些實施例中，導電材料1201之第一部分1201a以及相對應的晶種層1107之第一部分1107a可被稱作重佈線層 1501之接觸墊1501a。在一些實施例中，導電材料1201之第二部分1201b以及相對應的晶種層1107之第二部分1107b可被稱作重佈線層 1501之焊墊1501b。在一些實施例中，接觸墊1501a電耦接至相對應的導電柱1401。如下文更詳細地描述，在後續製程中，積體電路晶粒結合至焊墊1501b。在一些實施例中，接觸墊1501a可彼此電耦接。在一些實施例中，焊墊1501b中之每一者可與其他焊墊1501b以及接觸墊1501a中之每一者電隔離。在其他實施例中，接觸墊1501a以及焊墊1501b可彼此電耦接。
如圖15中所示，重佈線結構1503包括一個絕緣層（諸如絕緣層1105）以及一個重佈線層（諸如重佈線層 1501）。本領域技術人員可知絕緣層之數目以及重佈線層之數目僅是為了說明而提供且不限制本發明之範疇。在其他實施例中，重佈線結構可包括視所得封裝元件的設計要求而定的適當數目之絕緣層以及重佈線層。
參看圖16，積體電路晶粒901（參看圖10）貼附至重佈線層 1501之對應的焊墊1501b。在一些實施例中，積體電路晶粒901使用（例如）取放設備而置放於重佈線層 1501之對應的焊墊1501b上。在其他實施例中，積體電路晶粒901可手動地或使用任何其他適合的方法而置放於重佈線層1501之對應的焊墊1501b上。在一些實施例中，在將積體電路晶粒901置放於重佈線層1501之對應的焊墊1501b上之後，對焊料膏1001（參看圖10）施以回焊製程以形成焊料接合（solder joint）1601，所述焊料接合1601將積體電路晶粒901貼附至重佈線層1501之對應的焊墊1501b。在一些實施例中，焊料接合1601之寬度實質上與積體電路晶粒901之寬度相同。在一些實施例中，回焊製程可在介於約110℃與約260℃之間的溫度下執行。在一些實施例中，回焊製程在焊料接合1601與對應的晶種層801之間的介面處以及在焊料接合1601與重佈線層1501之對應的焊墊1501b之間的介面處形成金屬間化合物（圖中未示）。藉由使用焊料接合1601代替黏著膜（諸如晶粒貼附膜）來貼附積體電路晶粒901，熱阻可減少約1.2%。在一些實施例中，在將積體電路晶粒901置放於重佈線層1501之對應的焊墊1501b上之後，積體電路晶粒901可未對準相對於重佈線層1501之對應的焊墊1501b。在一些實施例中，回焊製程可減小積體電路晶粒901與重佈線層1501之對應的焊墊1501b之間的過度偏移，且可使積體電路晶粒901相對於重佈線層1501之對應的焊墊1501b自動對準。在所說明的實施例中，積體電路晶粒901之背側貼附至重佈線層1501之對應的焊墊1501b。因此，重佈線層1501亦可稱作背側重佈線層1501且重佈線結構1503亦可稱作背側重佈線結構1503。
參看圖17，密封體1701形成於載具1101上方以及積體電路晶粒901及導電柱1401上方且包圍積體電路晶粒901及導電柱1401。在一些實施例中，密封體1701可包括模塑料，諸如環氧樹脂、樹脂、可模製聚合物或其類似者。模塑料可在實質上為液態時被施加，且隨後可諸如在環氧樹脂或樹脂中經由化學反應而固化。在其他實施例中，模塑料可為被作為能夠安置於積體電路晶粒901及導電柱1401周圍及之間的凝膠或展性固體而施加的紫外線（UV）或熱固化聚合物。
參看圖18，在一些實施例中，密封體1701使用化學機械研磨製程、研磨製程、其組合或其類似製程來平坦化。在一些實施例中，執行平坦化製程直至積體電路晶粒901之導電柱501暴露。在一些實施例中，導電柱501之頂表面與導電柱1401之頂表面以及密封體1701之頂表面實質上共面。在上文參看圖6所描述之電測試製程之後不立即移除焊料層503（參看圖6）的一些實施例中，平坦化製程亦可自導電柱501上方移除焊料層503。
參看圖19，重佈線結構1901形成於積體電路晶粒901、導電柱1401以及密封體1701上方。在一些實施例中，重佈線結構1901可包括絕緣層19031 至絕緣層19033 ，以及安置在絕緣層19031 至絕緣層19033 內之重佈線層19051 以及重佈線層19052 （包括導電線以及通孔）。在一些實施例中，絕緣層19031 至絕緣層19033 可使用與上文參看圖2所描述之緩衝層201類似的材料以及方法形成且在本文中不重複描述。在一些實施例中，重佈線層19051 以及重佈線層19052 可使用與上文參看圖5所描述之導電柱501類似的材料形成且在本文中不重複描述。在所說明的實施例中，重佈線結構1901形成於積體電路晶粒901之前側上。因此，重佈線結構1901亦可稱作前側重佈線結構1901且重佈線層19051 以及重佈線層19052 亦可稱作前側重佈線層19051 以及前側重佈線層19052 。
進一步參看圖19，在一些實施例中，用於形成重佈線結構1901之製程步驟可包括圖案化絕緣層19031 以在其中形成開口。在一些實施例中，絕緣層19031 可使用與（例如）上文參看圖2所描述之用於圖案化緩衝層201之類似的方法來圖案化且在本文中不重複描述。重佈線層19051 形成於絕緣層19031 上方及絕緣層19031 中之開口中以接觸導電柱1401以及導電柱501。重佈線層19051 可包括各種線/跡線（「水平地」延伸穿過絕緣層19031 之頂表面）及/或通孔（「垂直地」延伸至絕緣層19031 中）。在一些實施例中，晶種層（圖中未示）沈積於絕緣層19031 上方及絕緣層19031 內之開口中。晶種層可使用與上文參看圖3所描述之晶種層301類似的材料以及方法形成且在本文中不重複描述。隨後，圖案化罩幕（圖中未示）形成於晶種層上方以定義重佈線層19051 的所需圖案。在一些實施例中，其中具有開口的圖案化罩幕可使用與上文參看圖4所描述之圖案化罩幕401類似的材料以及方法形成且在本文中不重複描述。在一些實施例中，導電材料藉由電化學電鍍製程、無電電鍍製程、原子層沈積、物理氣相沈積、濺鍍、其組合或其類似製程而形成於晶種層上。隨後，移除圖案化罩幕，且亦移除在移除圖案化罩幕之後暴露的晶種層之部分。在一些實施例中，圖案化罩幕可使用與上文參看圖6所描述之圖案化罩幕401類似的方法移除且在本文中不重複描述。在一些實施例中，晶種層之經暴露部分使用與上文參看圖6所描述之晶種層301之經暴露部分類似的方法移除且在本文中不重複描述。在一些實施例中，絕緣層19032 、重佈線層19052 以及絕緣層19033 形成於絕緣層19031 以及重佈線層19051 上方，其使重佈線結構1901之形成完成。在一些實施例中，重佈線層19052 可使用與重佈線層19051 類似的方法形成於絕緣層19032 上方且在本文中不重複描述。在一些實施例中，重佈線層19052 延伸穿過絕緣層19032 以及接觸重佈線層 19051 之部分。
如圖19中所示，重佈線結構1901包括三個絕緣層（諸如絕緣層19031 至絕緣層19033 ）以及插入於對應的絕緣層之間的兩個重佈線層（諸如重佈線層19051 以及重佈線層19052 ）。本領域技術人員可知絕緣層之數目以及重佈線層之數目僅是為了說明而提供且不限制本發明之範疇。在其他實施例中，重佈線結構可包括視所得封裝元件的設計要求而定的適當數目之絕緣層以及重佈線層。
進一步參看圖19，凸塊下金屬（underbump metallization，UBM）1907形成於重佈線結構1901上方且電耦接至重佈線結構1901。在一些實施例中，可形成一組穿過絕緣層19033 的開口以暴露重佈線層19052 之部分。在一些實施例中，凸塊下金屬1907可包括多個導電材料層，諸如鈦層、銅層以及鎳層。然而，本領域的普通技術人員可知存在適合於形成凸塊下金屬1907的許多適合之材料及層的配置，諸如鉻/鉻銅合金/銅/金之配置、鈦/鈦鎢/銅之配置，或銅/鎳/金之配置。可用於凸塊下金屬1907之任何適合的材料或材料層全部意欲包括於當前申請案的範疇內。在一些實施例中，連接件1909形成於凸塊下金屬1907上方且電耦接至凸塊下金屬1907。在一些實施例中，連接件1909可為焊料球、受控塌陷晶粒連接（C4）凸塊、球柵陣列封裝（ball grid array，BGA）球、微凸塊、化學鍍鎳鈀浸金（electroless nickel-electroless palladium-immersion gold technique，ENEPIG）所形成之凸塊，或其類似者。在連接件1909由焊料材料形成之一些實施例中，可執行回焊製程以便使焊料材料成形為所需凸塊形狀。在其他實施例中，連接件1909可為導電柱，其可使用與上文參看圖5所描述之導電柱501類似的材料以及方法形成且在本文中不重複描述。在連接件1909包括導電柱之一些實施例中，連接件1909可進一步包括可形成於導電柱之頂部上的頂蓋層。在一些實施例中，頂蓋層可包括焊料、鎳、錫、錫-鉛、金、銀、鈀、銦、鎳-鈀-金、鎳-金、類似者、其組合或其類似者，且可使用電化學電鍍製程、無電電鍍製程、其組合或其類似製程形成。
參看圖20，在於重佈線結構1901上方形成連接件1909之後，所得結構貼附至藉由框架2003支撐之膠帶2005，使得連接件1909接觸膠帶2005。在一些實施例中，膠帶2005可包括晶粒貼附膜、分割帶或其類似者。隨後，載具1101（參看圖19）自所得結構剝離以暴露絕緣層1105。在剝離載具1101之後，所得結構可分割以形成個別積體電路封裝2001。在一些實施例中，所得結構可藉由切割、雷射燒蝕方法、其組合或其類似者而分割。隨後，積體電路封裝2001中之每一者可經測試以識別已知良好封裝體（known good package，KGP）以供進一步處理。
參看圖21，在一些實施例中，工件2101藉由一組連接件2103延伸穿過絕緣層1105中之開口而結合至積體電路封裝2001，以形成堆疊半導體元件2100。在所說明的實施例中，工件2101為封裝件。在其他實施例中，工件2101可為一或多個晶粒、印刷電路板（printed circuit board，PCB）、封裝基底、插入件或其類似者。在其中工件2101為封裝件之一些實施例中，堆疊半導體元件2100為疊層封裝（PoP）元件。在其中工件2101為晶粒之其他實施例中，堆疊半導體元件2100為晶片封裝（CoP）元件。在一些實施例中，連接件2103可使用與上文參看圖19所描述之連接件1909類似的材料以及方法形成且在本文中不重複描述。在其他實施例中，在上文參看圖20所描述之分割製程之前，工件2101可結合至重佈線結構1503之重佈線層 1501。
進一步參看圖21，底填充材料2105可注入在工件2101與積體電路封裝2001之間的空間中或者以其他方式形成於其中且包圍連接件2103。底填充材料2105可為分配於結構之間的（例如）流體環氧樹脂、可變形凝膠、矽橡膠或其類似者，且隨後固化以硬化。此外，可使用底填充材料2105來降低對連接件2103之損害且保護連接件2103。
圖22及圖23是根據一些實施例在製造積體電路封裝期間之各種處理步驟的截面圖。圖22說明與圖20中所說明之結構類似的結構，其中相同元件使用相同數值參考來標記。區別於圖20之結構，圖22之結構包括含有多個重佈線層以及多個絕緣層之背側重佈線結構2203，所述多個重佈線層諸如重佈線層1501以及重佈線層2207，所述多個絕緣層諸如絕緣層1105以及絕緣層2205。
參看圖22，在一些實施例中，如上文參看圖11至圖15所描述在於載具1101上方形成絕緣層1105之後且在形成重佈線層1501以及導電柱1401之前，重佈線層2207形成於絕緣層1105上方且絕緣層2205形成於重佈線層2207上方。在一些實施例中，絕緣層2205可使用與上文參看圖11所描述之絕緣層1105類似的材料以及方法形成且在本文中不重複描述。在一些實施例中，重佈線層2207可使用與（例如）上文參看圖19所描述之重佈線層19051 類似的材料以及方法形成且在本文中不重複描述。在一些實施例中，在形成重佈線層2207以及絕緣層2205之後，可執行上文參看圖11至圖19所描述之製程步驟以形成圖22中所說明之結構。本領域技術人員可知重佈線層以及絕緣層之數目僅是為了說明而提供且不限制本發明之範疇。在其他實施例中，重佈線結構2203可包括視所得封裝元件的設計要求而定的適當數目之重佈線層以及絕緣層。隨後，可分割所得結構以形成個別積體電路封裝2201。在一些實施例中，所得結構可藉由切割、雷射燒蝕方法、其組合或其類似者而分割。隨後，積體電路封裝2201中之每一者可經測試以識別已知良好封裝體（KGP）以供進一步處理。
參看圖23，在一些實施例中，工件2301藉由一組連接件2303延伸穿過絕緣層1105中之開口而結合至積體電路封裝2201，以形成堆疊半導體元件2300。在所說明的實施例中，工件2301為封裝件。在其他實施例中，工件2301可為一或多個晶粒、印刷電路板（PCB）、封裝基底、插入件或其類似者。在其中工件2301為封裝件之一些實施例中，堆疊半導體元件2300為疊層封裝（PoP）元件。在其中工件2301為晶粒之其他實施例中，堆疊半導體元件2300為晶片封裝（CoP）元件。在一些實施例中，連接件2303可使用與上文參看圖19所描述之連接件1909類似的材料以及方法形成且在本文中不重複描述。在其他實施例中，在上文參看圖22所描述之分割製程之前，工件2301可結合至重佈線結構2203之重佈線層2207。
進一步參看圖23，底填充材料2305可注入在工件2301與積體電路封裝2201之間的空間中或者以其他方式形成於其中且包圍連接件2303。底填充材料2305可為分配於結構之間的（例如）流體環氧樹脂、可變形凝膠、矽橡膠或其類似者，且隨後固化以硬化。此外，可使用底填充材料2305來降低對連接件2303之損害且保護連接件2303。
圖24是說明根據一些實施例之形成積體電路晶粒之方法2400的流程圖。方法開始於步驟2401，其中接觸墊（諸如圖1中所說明之接觸墊111）形成於基底（諸如圖1中所說明之基底105）的前側（主動側）上方，如上文參看圖1所描述。在步驟2403中，導電柱（諸如圖6中所說明之導電柱）形成於接觸墊上方，如上文參看圖1至圖6所描述。在步驟2405中，保護層（諸如圖7中所說明之保護層701）形成於導電柱上方且包圍導電柱，如上文參看圖7所描述。在步驟2407中，薄化基底之背側，如上文參看圖7所描述。在步驟2409中，晶種層（諸如圖8中所說明之晶種層801）形成於基底之背側上，如上文參看圖8所描述。在步驟2411中，基底單一化為多個積體電路晶粒（諸如圖9中所說明之積體電路晶粒901），如上文參看圖9所描述。在步驟2413中，將焊料膏（諸如圖10中所說明之焊料膏1001）施加至多個積體電路晶粒之每一晶種層上，如上文參看圖10所描述。在替代實施例中，步驟2411與步驟1413可調換。
圖25是說明根據一些實施例之形成積體電路封裝之方法2500的流程圖。方法開始於步驟2501，其中第一重佈線層（諸如圖15中所說明之重佈線層1501）形成於載具（諸如圖15中所說明之載具1101）上方，所述第一重佈線層包括接觸墊（諸如圖15中所說明之接觸墊1501a）以及焊墊（諸如圖15中所說明之焊墊1501b），如上文參看圖11至圖15所描述。在步驟2503中，導電柱（諸如圖14中所說明之導電柱1401）形成於接觸墊上方，如上文參看圖13以及圖14所描述。在步驟2505中，使用焊料接合（諸如圖16中所說明之焊料接合1601）將積體電路晶粒（諸如圖16中所說明之積體電路晶粒901）貼附至焊墊，如上文參看圖16所描述。在步驟2507中，密封體（諸如圖17中所說明之密封體1701）形成於導電柱以及積體電路晶粒上方且包圍導電柱以及積體電路晶粒，如上文參看圖17所描述。在步驟2509中，第二重佈線層（諸如圖19中所說明之重佈線層19051 ）形成於密封體、導電柱以及積體電路晶粒上方，如上文參看圖18以及圖19所描述。
根據一實施例，方法包括：於載具上方形成第一重佈線層，所述第一重佈線層包括接觸墊以及焊墊；於接觸墊上方形成導電柱；使用焊料接合將積體電路晶粒之背側表面貼附至焊墊；沿著導電柱之側壁以及積體電路晶粒之側壁形成密封體，所述積體電路晶粒之前側表面實質上與密封體之最頂表面以及導電柱之最頂表面齊平；以及於積體電路晶粒之前側表面、密封體之最頂表面以及導電柱之最頂表面上方形成第二重佈線層。在一實施例中，使用焊料接合將積體電路晶粒之背側表面貼附至焊墊包括：將焊料膏施加至積體電路晶粒之背側表面上；將積體電路晶粒置放於焊墊上方，所述焊料膏與所述焊墊實體接觸(physical contact)；以及回焊焊料膏以形成焊料接合。在一實施例中，於載具上方形成的第一重佈線層包括：於載具上方形成晶種層；於所述晶種層上方形成第一圖案化罩幕，所述第一圖案化罩幕具有第一開口以及第二開口；使第一導電材料沈積於第一開口以及第二開口中，以形成第一開口中之第一導電特徵以及第二開口中之第二導電特徵；移除第一圖案化罩幕；以及移除晶種層之經暴露部分，第一導電特徵與在第一導電特徵下的晶種層之第一部分形成接觸墊，第二導電特徵與在第二導電特徵下的晶種層之第二部分形成焊墊。在一實施例中，於接觸墊上方形成的導電柱包括：於晶種層、第一導電特徵以及第二導電特徵上方形成第二圖案化罩幕，所述第二圖案化罩幕具有第三開口，所述第三開口暴露所述第一導電特徵之一部分，所述第二圖案化罩幕覆蓋第二導電特徵；使第二導電材料沈積於第三開口中以形成導電柱；以及移除第二圖案化罩幕。在一實施例中，導電柱將第一重佈線層之接觸墊電連接至第二重佈線層。在一實施例中，焊墊之寬度比接觸墊之寬度大。在一實施例中，接觸墊與焊墊彼此電隔離。
根據另一實施例，方法包括：於載具上方形成絕緣層；於所述絕緣層上方形成晶種層；於所述晶種層上方形成第一圖案化罩幕，所述第一圖案化罩幕具有第一開口以及第二開口，所述第一開口以及所述第二開口暴露晶種層；使第一導電材料沈積於第一開口以及第二開口中，以形成第一開口中之第一導電特徵以及第二開口中之第二導電特徵；移除第一圖案化罩幕；於晶種層、第一導電特徵以及第二導電特徵上方形成第二圖案化罩幕，所述第二圖案化罩幕具有第三開口，所述第三開口暴露第一導電特徵；使第二導電材料沈積於第三開口中以形成所述第三開口中之導電柱；移除第二圖案化罩幕；移除晶種層之經暴露部分；以及使用焊料接合將積體電路晶粒之背側表面貼附至第二導電特徵。在一實施例中，方法更包括沿著所述導電柱之側壁以及所述積體電路晶粒之側壁形成密封體，所述積體電路晶粒之前側表面實質上與所述密封體之最頂表面以及所述導電柱之最頂表面齊平。在一實施例中，方法更包括於所述積體電路晶粒之前側表面、所述密封體之最頂表面以及所述導電柱之最頂表面上方形成重佈線層。在一實施例中，導電柱將重佈線層電耦接至第一導電特徵。在一實施例中，使用焊料接合將積體電路晶粒之背側表面貼附至第二導電特徵包括：將焊料膏施加至積體電路晶粒之背側表面上；將積體電路晶粒置放於第二導電特徵上方，所述焊料膏與第二導電特徵實體接觸；以及回焊焊料膏以形成焊料接合。在一實施例中，將焊料膏施加至積體電路晶粒之背側表面上包括將所述焊料膏印刷至積體電路晶粒之背側表面上。在一實施例中，在移除晶種層之經暴露部分之後，第一導電特徵與第二導電特徵彼此電隔離。
根據又一實施例，半導體結構包括：積體電路晶粒，所述積體電路晶粒具有前側以及與前側相對的背側，所述積體電路晶粒具有在所述前側上之多個接觸構件；密封體，沿著積體電路晶粒之側壁延伸；第一重佈線層，在積體電路晶粒之背側上，所述第一重佈線層包括接觸墊以及焊墊；焊料接合，插入於積體電路晶粒之背側與焊墊之間；第二重佈線層，在積體電路晶粒之前側上；以及導電通孔，在密封體內，所述導電通孔自第一重佈線層延伸至第二重佈線層。在一實施例中，導電通孔將第一重佈線層之接觸墊電連接至第二重佈線層。在一實施例中，接觸墊與焊墊彼此電隔離。在一實施例中，密封體之一部分沿著接觸墊之側壁以及焊墊之側壁延伸。在一實施例中，多個接觸構件電耦接至第二重佈線層。在一實施例中，焊料接合之寬度實質上與積體電路晶粒之寬度相同。
亦可包括其他特徵及製程。舉例而言，可包括測試結構以幫助對三維封裝或三維積體電路元件之驗證測試。測試結構可包括例如形成於重佈線層中或基底上的測試襯墊，從而允許測試三維封裝或三維積體電路、使用探測器及/或探測卡以及其類似處理。驗證測試可對中間結構以及最終結構執行。另外，本文中所揭露的結構及方法可結合對已知良好晶粒的中間驗證的測試方法一同使用，以提高產率及降低成本。
前文概述若干實施例的特徵，使得本領域技術人員可更好地理解本發明的態樣。本領域技術人員應理解，其可易於使用本發明作為設計或修改用於實現本文中所引入之實施例的相同目的及/或達成相同優點的其他處理程序及結構的基礎。本領域技術人員亦應認識到，此類等效構造並不脫離本發明的精神以及範疇，且其可在不脫離本發明的精神以及範疇的情況下在本文中進行各種改變、替代以及更改。
100‧‧‧工件
101‧‧‧晶粒區域
103‧‧‧切割道
105‧‧‧基底
105b‧‧‧基底之背側
107‧‧‧主動元件及/或被動元件
109‧‧‧內連線結構
111‧‧‧接觸墊
113‧‧‧鈍化層
115‧‧‧開口
201‧‧‧緩衝層
203‧‧‧開口
301‧‧‧晶種層
401‧‧‧圖案化罩幕
403‧‧‧開口
501‧‧‧導電柱
503‧‧‧焊料層
701‧‧‧保護層
703‧‧‧膠帶
801‧‧‧晶種層
901‧‧‧積體電路晶粒
903‧‧‧框架
905‧‧‧黏合劑
1001‧‧‧焊料膏
1101‧‧‧載具
1103‧‧‧釋放層
1105‧‧‧絕緣層
1107‧‧‧晶種層
1107a‧‧‧第一部分
1107b‧‧‧第二部分
1109‧‧‧圖案化罩幕
1111‧‧‧開口
1113‧‧‧開口
1201‧‧‧導電材料
1201a‧‧‧第一部分
1201b‧‧‧第二部分
1301‧‧‧圖案化罩幕
1303‧‧‧開口
1401‧‧‧導電柱/導電通孔/模塑通孔
1501‧‧‧重佈線層
1501a‧‧‧接觸墊
1501b‧‧‧焊墊
1503‧‧‧重佈線結構
1601‧‧‧焊料接合
1701‧‧‧密封體
1901‧‧‧重佈線結構
19031‧‧‧絕緣層
19032‧‧‧絕緣層
19033‧‧‧絕緣層
19051‧‧‧重佈線層
19052‧‧‧重佈線層
1907‧‧‧凸塊下金屬
1909‧‧‧連接件
2001‧‧‧積體電路封裝
2003‧‧‧框架
2005‧‧‧膠帶
2100‧‧‧堆疊半導體元件
2101‧‧‧工件
2103‧‧‧連接件
2105‧‧‧底填充材料
2201‧‧‧積體電路封裝
2203‧‧‧重佈線結構
2205‧‧‧絕緣層
2207‧‧‧重佈線層
2300‧‧‧堆疊半導體元件
2301‧‧‧工件
2303‧‧‧連接件
2305‧‧‧底填充材料
2400‧‧‧方法
2401~2413‧‧‧步驟
2500‧‧‧方法
2501~2509‧‧‧步驟
W1、W2、W3‧‧‧寬度
當結合附圖閱讀時，自以下實施方式(detailed description)最佳地理解本發明的態樣。應注意，根據業界中的標準慣例，各種特徵未按比例繪製。實際上，為論述清楚起見，可任意增大或減小各種特徵之尺寸。 圖1至圖10是根據一些實施例在製造積體電路晶粒期間之各種處理步驟的截面圖。 圖11至圖21是根據一些實施例在製造積體電路封裝期間之各種處理步驟的截面圖。 圖22及圖23是根據一些實施例在製造積體電路封裝期間之各種處理步驟的截面圖。 圖24是說明根據一些實施例之形成積體電路晶粒之方法的流程圖。 圖25是說明根據一些實施例之形成積體電路封裝之方法的流程圖。

Claims (20)

  1. 一種方法，包括： 於載具上方形成第一重佈線層，所述第一重佈線層包括接觸墊以及焊墊； 於所述接觸墊上方形成導電柱； 使用焊料接合將積體電路晶粒之背側表面貼附至所述焊墊； 沿著所述導電柱之側壁及所述積體電路晶粒之側壁形成密封體，所述積體電路晶粒的前側表面實質上與所述密封體之最頂表面及所述導電柱之最頂表面齊平；以及 於所述積體電路晶粒之所述前側表面、所述密封體之所述最頂表面以及所述導電柱之所述最頂表面之上方形成第二重佈線層。
  2. 如申請專利範圍第1項所述的方法，其中使用所述焊料接合將所述積體電路晶粒之所述背側表面貼附至所述焊墊包括： 將焊料膏施加至所述積體電路晶粒之所述背側表面上； 將所述積體電路晶粒置放於所述焊墊上，所述焊料膏與所述焊墊實體接觸；以及 回焊所述焊料膏以形成所述焊料接合。
  3. 如申請專利範圍第1項所述的方法，其中於所述載具上方形成所述第一重佈線層包括： 於所述載具上方形成晶種層； 於所述晶種層上方形成第一圖案化罩幕，所述第一圖案化罩幕具有第一開口以及第二開口； 使第一導電材料沈積於所述第一開口以及所述第二開口中，以形成所述第一開口中之第一導電特徵以及所述第二開口中之第二導電特徵； 移除所述第一圖案化罩幕；以及 移除所述晶種層之被暴露部分，所述第一導電特徵與在所述第一導電特徵下的所述晶種層之第一部分形成所述接觸墊，所述第二導電特徵與在所述第二導電特徵下的所述晶種層之第二部分形成所述焊墊。
  4. 如申請專利範圍第3項所述的方法，其中於所述接觸墊上方形成所述導電柱包括： 於所述晶種層、所述第一導電特徵以及所述第二導電特徵上方形成第二圖案化罩幕，所述第二圖案化罩幕具有第三開口，所述第三開口暴露所述第一導電特徵之一部分，所述第二圖案化罩幕覆蓋所述第二導電特徵； 使第二導電材料沈積於所述第三開口中，以形成所述導電柱；以及 移除所述第二圖案化罩幕。
  5. 如申請專利範圍第1項所述的方法，其中所述導電柱將所述第一重佈線層之所述接觸墊電連接至所述第二重佈線層。
  6. 如申請專利範圍第1項所述的方法，其中所述焊墊之寬度比所述接觸墊之寬度大。
  7. 如申請專利範圍第1項所述的方法，其中所述接觸墊與所述焊墊彼此電隔離。
  8. 一種方法，包括： 於載具上方形成絕緣層； 於所述絕緣層上方形成晶種層； 於所述晶種層上方形成第一圖案化罩幕，所述第一圖案化罩幕具有第一開口以及第二開口，所述第一開口以及所述第二開口暴露所述晶種層； 使第一導電材料沈積於所述第一開口以及所述第二開口中，以形成所述第一開口中之第一導電特徵以及所述第二開口中之第二導電特徵； 移除所述第一圖案化罩幕； 於所述晶種層、所述第一導電特徵以及所述第二導電特徵上方形成第二圖案化罩幕，所述第二圖案化罩幕具有第三開口，所述第三開口暴露所述第一導電特徵； 使第二導電材料沈積於所述第三開口中以在所述第三開口中形成導電柱； 移除所述第二圖案化罩幕； 移除所述晶種層之被暴露部分；以及 使用焊料接合將積體電路晶粒之背面表面貼附至所述第二導電特徵。
  9. 如申請專利範圍第8項所述的方法，更包括沿著所述導電柱之側壁以及所述積體電路晶粒之側壁形成密封體，所述積體電路晶粒之前側表面實質上與所述密封體之最頂表面以及所述導電柱之最頂表面齊平。
  10. 如申請專利範圍第9項所述的方法，更包括於所述積體電路晶粒之所述前側表面、所述密封體之所述最頂表面以及所述導電柱之所述最頂表面上方形成重佈線層。
  11. 如申請專利範圍第10項所述的方法，其中所述導電柱將所述重佈線層電耦接至所述第一導電特徵。
  12. 如申請專利範圍第8項所述的方法，其中使用所述焊料接合將所述積體電路晶粒之所述背側表面貼附至所述第二導電特徵包括： 將焊料膏施加至所述積體電路晶粒之所述背側表面上； 將所述積體電路晶粒置放於所述第二導電特徵上方，所述焊料膏與所述第二導電特徵實體接觸；以及 回焊所述焊料膏以形成所述焊料接合。
  13. 如申請專利範圍第12項所述的方法，其中將所述焊料膏施加至所述積體電路晶粒之所述背側表面上包括將所述焊料膏印刷至所述積體電路晶粒之所述背側表面上。
  14. 如申請專利範圍第8項所述的方法，其中在移除所述晶種層之所述被暴露部分之後，所述第一導電特徵與所述第二導電特徵彼此電隔離。
  15. 一種半導體結構，包括： 積體電路晶粒，所述積體電路晶粒具有前側以及與所述前側相對的背側，所述積體電路晶粒具有在所述前側上之多個接觸構件； 密封體，沿著所述積體電路晶粒之側壁延伸； 第一重佈線層，在所述積體電路晶粒之所述背側上，所述第一重佈線層包括接觸墊以及焊墊； 焊料接合，插入於所述積體電路晶粒之所述背側與所述焊墊之間； 第二重佈線層，在所述積體電路晶粒之所述前側上；以及 導電通孔，在所述密封體內，所述導電通孔自所述第一重佈線層延伸至所述第二重佈線層。
  16. 如申請專利範圍第15項所述的半導體結構，其中所述導電通孔將所述第一重佈線層之所述接觸墊電連接至所述第二重佈線層。
  17. 如申請專利範圍第15項所述的半導體結構，其中所述接觸墊與所述焊墊彼此電隔離。
  18. 如申請專利範圍第15項所述的半導體結構，其中所述密封體之一部分沿著所述接觸墊之側壁以及所述焊墊之側壁延伸。
  19. 如申請專利範圍第15項所述的半導體結構，其中所述多個接觸構件電耦接至所述第二重佈線層。
  20. 如申請專利範圍第15項所述的半導體結構，其中所述焊料接合之寬度實質上與所述積體電路晶粒之寬度相同。
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