TWI714403B - 半導體結構及其製造方法 - Google Patents

半導體結構及其製造方法 Download PDF

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TWI714403B
TWI714403B TW108147192A TW108147192A TWI714403B TW I714403 B TWI714403 B TW I714403B TW 108147192 A TW108147192 A TW 108147192A TW 108147192 A TW108147192 A TW 108147192A TW I714403 B TWI714403 B TW I714403B
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Taiwan
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layer
semiconductor
bonding
interconnection
connector
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TW108147192A
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TW202109811A (zh
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胡致嘉
陳憲偉
陳明發
詹森博
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台灣積體電路製造股份有限公司
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Publication of TW202109811A publication Critical patent/TW202109811A/zh

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Abstract

提供一種半導體結構及其製造方法。半導體結構包括半導體基板、多個內連層、第一連接件及第二連接件。半導體基板在所述半導體基板中包括多個半導體裝置。內連層設置在半導體基板之上且電性耦合到半導體裝置。第一連接件設置在所述多個內連層之上且延伸到與所述多個內連層的第一層級接觸。第二連接件設置在所述多個內連層之上且與第一連接件實質上齊平。第二連接件比第一連接件延伸得更遠，以與位於所述多個內連層的第一層級與半導體基板之間的所述多個內連層的第二層級接觸，第一連接件寬於第二連接件。

Description

半導體結構及其製造方法
本發明的實施例是有關於一種半導體結構及其製造方法，特別是有關於一種包含不同尺寸連接件的半導體結構及其製造方法。
近年來，由於各種電子元件(例如電晶體、二極體、電阻器、電容器等)的積體密度的持續提高，半導體工業已經歷了快速增長。在很大程度上，積體密度的這種提高來自於最小特徵尺寸(minimum feature size)的持續減小，使得更多元件能夠整合到給定面積中。舉例來說，積體元件所佔用的面積接近於半導體晶圓的表面，然而，在形成二維(two-dimensional，2D)積體電路中，可實現的密度存在實體限制。舉例來說，這些限制中的一個限制來自於隨著半導體裝置的數量增加，半導體裝置之間的內連的數量及長度明顯增大。由於現存的積體電路設計規則要求在半導體裝置的內連結構中減小導電配線佈局的距離，因而內連結構的線距及間距也變得非常小。使得內連結構中的導電配線之 間的寄生電容變高。因此，積體電路的電阻-電容(resistance-capacitance，RC)延遲會增大。另外，由於導電配線之間的間距較小，因此洩漏電流(leakage current)可能會變得明顯。因此，正不斷努力開發用於形成半導體裝置的新機制。
根據本公開的一些實施例，提供一種半導體結構，所述半導體結構包括半導體基板、多個內連層、第一連接件及第二連接件。所述半導體基板在所述半導體基板中包括多個半導體裝置。所述內連層設置在所述半導體基板之上且電性耦合到所述半導體裝置。所述第一連接件設置在所述多個內連層之上且延伸到與所述多個內連層的第一層級接觸。所述第二連接件設置在所述多個內連層之上且與所述第一連接件實質上齊平。所述第二連接件比所述第一連接件延伸得更遠，以與位於所述多個內連層的所述第一層級與所述半導體基板之間的所述多個內連層的第二層級接觸，所述第一連接件寬於所述第二連接件。
根據本公開的一些實施例，提供一種半導體結構，所述半導體結構包括第一半導體晶粒及堆疊在所述第一半導體晶粒上且接合到所述第一半導體晶粒的第二半導體晶粒。所述第一半導體晶粒包括第一接合連接件及第二接合連接件。所述第二接合連接件的高度對寬度的比例大於所述第一接合連接件的高度對寬度的比例。所述第二半導體晶粒包括接合到所述第一半導體晶粒的 所述第一接合連接件的第三接合連接件以及接合到所述第一半導體晶粒的所述第二接合連接件的第四接合連接件。所述第三接合連接件的尺寸及所述第四接合連接件的尺寸分別對應於所述第一接合連接件的尺寸及所述第二接合連接件的尺寸。
根據本公開的一些實施例，一種半導體結構的製造方法包括至少以下步驟。在第一半導體基板之上的第一內連結構上形成第一表面介電層。形成第一通孔開口及第二通孔開口，其中所述第二通孔開口穿透過所述第一表面介電層且比所述第一通孔開口延伸得更遠，以可觸及的方式顯露出所述第一內連結構的至少一部分，所述第二通孔開口比所述第一通孔開口窄。在所述第一通孔開口及所述第二通孔開口中形成導電材料，以對應地形成第一接合連接件及第二接合連接件。
10、20、30:半導體結構
40:結構
42:第一元件
44:第二元件
44a:端子
110:第一半導體基板
112:第一半導體裝置
120:第一內連結構
122:第一內連層/內連層
124:第一介電層
210:第二半導體基板
212:第二半導體裝置
220:第二內連結構
220a:第一部分
220b:第二部分
222:第二內連層
224:第二介電層
230、330:半導體穿孔(TSV)
240:隔離層
250:重佈線結構
252、252a、252b:圖案化導電層
254、254a:圖案化介電層
260:外部端子
AP1:第一接觸墊
AP2:第二接觸墊
AP3:外部接觸墊
BC0、BC1、BC2、BC3、BC4、BF0、BF1、BF2、BF3、BF4:第一接合連接件
BD1:第一表面介電層/表面介電層
BD2:第二表面介電層
BD3:第一表面介電層
BD4:第三表面介電層
BE0、BE1、BE2、BE3、BE4:第二接合連接件
BG0、BG1、BG2:第三接合連接件
DV1、DV2:開口深度
IF、IF’:接合介面
M1:底部內連層
M2:第二層級內連層
M3:第三層級內連層
Mt:頂部內連層
OP:開口
PS1:第一鈍化層
PS2:第二鈍化層
PS3:第三鈍化層
S1、S1’:第一表面
S2:第二表面
S3:第三表面
S4:第四表面
S4’:經薄化的第四表面
S5:第五表面
T1、T1’:第一層
T2:第二層
T3:第三層
TD:厚度方向
TR0、TR1、TR2、TR3、TR4:溝槽
VO1、VO2、VO3、VO4:通孔開口
W1、W2、WT1、WT2、WV1、WV2:頂部寬度
結合附圖閱讀以下詳細說明，會最佳地理解本發明的各個態樣。應注意，根據行業中的標準慣例，各種特徵並非按比例繪製。事實上，為論述清晰起見，可任意增大或減小各種特徵的尺寸。
圖1A到圖1C是示出根據本公開一些實施例的半導體結構的第一層的製造方法中各個階段的示意性剖視圖。
圖2A到圖2D是示出根據本公開一些實施例的半導體結構的第二層的製造方法中各個階段的示意性剖視圖。
圖3A到圖3D是示出根據本公開一些實施例的半導體結構的製造方法中各個階段的示意性剖視圖。
圖4是示出根據本公開一些實施例的半導體結構的第一層的示意性剖視圖。
圖5A到圖5C是示出根據本公開一些實施例的半導體結構的製造方法中各個階段的示意性局部剖視圖。
圖6是示出根據本公開一些實施例的半導體結構的示意性剖視圖。
圖7是示出根據本公開一些實施例的半導體結構的應用的示意性剖視圖。
以下揭露內容提供用於實作本發明的不同特徵的諸多不同的實施例或實例。以下闡述組件及排列的具體實例以簡化本揭露內容。當然，該些僅為實例且不旨在進行限制。舉例而言，以下說明中將第一特徵形成於第二特徵「之上」或第二特徵「上」可包括其中第一特徵及第二特徵被形成為直接接觸的實施例，且亦可包括其中第一特徵與第二特徵之間可形成有附加特徵、進而使得所述第一特徵與所述第二特徵可能不直接接觸的實施例。另外，本發明可能在各種實例中重複使用參考編號及/或字母。此種重複使用是出於簡潔及清晰的目的，但自身並不表示所論述的各種實施例及/或配置之間的關係。
另外，為了易於描述圖中所示的一個元件或特徵與另一元件或特徵的關係，本文中可使用例如「在...下」、「在...下方」、「下部」、「上覆」、及「上部」等空間相對用語。除了圖中所繪示的取向之外，所述空間相對用語亦旨在涵蓋裝置在使用或操作時的不同取向。設備可被另外取向(旋轉90度或在其他取向)，而本文所用的空間相對描述語可同樣相應地作出解釋。
還可包括其他特徵及製程。舉例來說，可包括測試結構以說明對三維(three-dimensional，3D)封裝或三維積體電路(three-dimensional integrated circuit，3DIC)裝置進行驗證測試。所述測試結構可包括例如在重佈線層中或基板上形成的測試墊(test pad)，以便能夠對3D封裝或3DIC進行測試、使用探針及/或探針卡(probe card)等。可對中間結構以及最終結構執行驗證測試。另外，本文中所公開的結構及方法可與包含對已知良好晶粒(known good die)進行中間驗證的測試方法接合使用以提高良率並降低成本。
圖1A到圖1C是示出根據本公開一些實施例的半導體結構的第一層的製造方法中各個階段的示意性剖視圖。參照圖1A，在第一半導體基板110上形成第一內連結構120。舉例來說，第一半導體基板110包括可為經摻雜的或未經摻雜的塊狀半導體、絕緣體上半導體(semiconductor-on-insulator，SOI)基板、其他支撐基板(例如石英、玻璃等)、其組合等。在一些實施例中，第一半導體基板110包含元素半導體(例如結晶結構、多晶結構或非 晶結構中的矽或鍺等)、化合物半導體(例如碳化矽、砷化鎵、磷化鎵、磷化銦、砷化銦及/或銻化銦等)、合金半導體(例如矽-鍺(SiGe)、磷砷化鎵(GaAsP)、砷化鋁銦(AlInAs)、砷化鋁鎵(AlGaAs)、砷化鎵銦(GaInAs)、磷化鎵銦(GaInP)等)、其組合或其他合適的材料。舉例來說，化合物半導體基板可具有多層式結構或者所述基板可包括多層式化合物半導體結構。在一些實施例中，合金SiGe形成在矽基板之上。在其他實施例中，SiGe基板是應變型(strained)的。在一些實施例中，第一半導體基板110是裝置晶圓。舉例來說，第一半導體基板110包括形成在第一半導體基板110中的多個第一半導體裝置112。第一半導體裝置112可為或可包括主動裝置(例如電晶體、二極體等)及/或被動裝置(例如電容器、電阻器、電感器等)或其他合適的電子元件。
第一半導體基板110可包括在前段製程(front-end-of-line，FEOL)中形成的電路系統(未示出)，第一內連結構120可在後段製程(back-end-of-line，BEOL)中形成。在一些實施例中，第一內連結構120包括形成在第一半導體基板110之上的層間介電(inter-layer dielectric，ILD)層以及形成在ILD層之上的金屬間介電(inter-metallization dielectric，IMD)層。在一些實施例中，ILD層及IMD層由例如以下的低介電常數(low-K)介電材料形成：磷矽酸鹽玻璃(phosphosilicate glass，PSG)、硼磷矽酸鹽玻璃(borophosphosilicate glass，BPSG)、SiOxCy、旋塗玻璃(Spin-On-Glass)、旋塗聚合物(Spin-On-Polymer)、矽碳材料、 其化合物、其複合物、其組合等。ILD層及IMD層可包括任何合適數量的介電材料層，所述介電材料層的數量並非僅限於此。
在一些實施例中，第一內連結構120對第一半導體裝置112進行內連。舉例來說，第一內連結構120包括設置在第一半導體基板110上的至少一個第一介電層124以及嵌在第一介電層124中的多個第一內連層122。舉例來說，第一內連層122中的每一者包括導電線、導電接墊、導通孔等。第一內連層122的材料可包括銅或銅合金，但也可使用其他金屬(例如鋁、銀、金及其組合)。在一些實施例中，第一內連層122的兩層或更多層導電線由第一內連層122的導通孔在垂直方向上進行內連且埋在第一介電層124中。設置在第一半導體基板110之上的第一內連結構120的第一內連層122可將形成在第一半導體基板110中及/或第一半導體基板110上的第一半導體裝置112彼此電性耦合且將第一半導體裝置112電性耦合到外部元件。
舉例來說，第一內連結構120的第一內連層122包括底部內連層M1、頂部內連層Mt(即所述多個內連層的第一層級)及位於底部內連層M1與頂部內連層Mt之間的中間層級內連層(例如直接位於底部內連層M1之上的第二層級內連層M2、直接位於第二層級內連層M2之上的第三層級內連層M3等)。為易於說明，本文中使用術語“頂部”來代表相對於其他內連層來說距離第一半導體基板110最遠的內連層，使用術語“底部”來代表相對於其他內連層來說距離第一半導體基板110最近的內連層。應注 意，圖中所繪示四層級的內連層結構僅為一個例子，第一內連結構120可依據電路設計的要求而包括更多或更少的內連層。
在一些實施例中，在第一內連結構120的頂部內連層Mt之上設置至少一個第一鈍化層PS1。在一些實施例中，第一鈍化層PS1是非低介電常數介電層。舉例來說，第一鈍化層PS1包含氧化矽、氮化矽、未經摻雜的矽酸鹽玻璃、聚醯亞胺等。作為另外一種選擇，省略第一鈍化層PS1。在一些實施例中，在第一鈍化層PS1上形成第一接觸墊AP1，第一接觸墊AP1可藉由導通孔來與頂部內連層Mt電性接觸。第一接觸墊AP1的材料可包括鋁，但也可使用其他合適的導電材料(例如銅)。應注意，結合圖1A所闡述的結構僅為一個例子。圖1A中所示的結構可包括更多元件且其他的配置也是可能的。
參照圖1B及圖1C，形成第一表面介電層BD1及多個第一接合連接件(例如BC0、BC1、BC2、BC3及BC4)。舉例來說，表面介電材料形成在第一鈍化層PS1之上且覆蓋第一接觸墊AP1。表面介電材料可為或可包括氮氧化物層(例如氮氧化矽(SiON)層)或任何合適的介電材料(例如氧化矽(SiO2)、氮化矽(SiN)等)。接下來，利用鑲嵌技術(damascene technique)或其他合適的製程將表面介電材料圖案化以形成第一表面介電層BD1。在一些實施例中，對表面介電材料執行雙鑲嵌製程(dual damascene process)以形成具有多個溝槽(例如TR0、TR1、TR2、TR3及TR4)及通孔開口(例如VO1、VO2、VO3及VO4)的第一表面 介電層BD1，如圖1B中所示。應理解，結合圖1B闡述的雙鑲嵌技術僅為一個例子，在其他實施例中可利用單鑲嵌製程(single damascene process)或其他合適的製程。
在一些實施例中，溝槽是在通孔開口之前形成。舉例來說，執行蝕刻步驟以移除表面介電材料的一些部分，從而形成溝槽TR0、TR1、TR2、TR3及TR4。在此階段，下面的導電特徵(例如第一接觸墊AP1及第一內連層122)未被表面介電材料顯露出。接著，形成通孔開口VO1、VO2、VO3及VO4以在預期位置處暴露出下面的導電特徵。通孔開口的數量可對應於或可不對應於溝槽的數量。應理解，可在第一內連結構120中設置或可在表面介電材料與第一內連結構120之間設置蝕刻停止層(未示出)。舉例來說，在形成溝槽的製程期間，通孔開口VO1、VO2、VO3及VO4從對應的溝槽TR1、TR2、TR3及TR4的底部向下延伸，直到下面的第一接觸墊AP1及/或內連層122被以可觸及的方式暴露出為止。溝槽TR0在剖面中可不對應於通孔開口中的任何通孔開口，舉例來說，溝槽TR0可用於形成導電線或作為虛擬墊(dummy pad)。
通孔開口中的一些通孔開口(例如VO1)可向下延伸以至嵌在表面介電材料中的第一接觸墊AP1，以使第一接觸墊AP1的至少一部分被第一表面介電層BD1的溝槽TR1及通孔開口VO1以可觸及的方式暴露出以進行進一步的電性連接。在一些實施例中，省略暴露出第一接觸墊AP1的溝槽TR1及對應的通孔開口 VO1。通孔開口中的一些通孔開口(例如VO2)可穿過第一鈍化層PS1以至頂部內連層Mt，以使頂部內連層Mt的至少一部分被溝槽TR2及通孔開口VO2以可觸及的方式暴露出。通孔開口中的一些通孔開口(例如VO3及VO4)可穿過第一鈍化層PS1且延伸到第一內連結構120的第一介電層124中，以至底部內連層M1及/或任何中間層級的內連層(例如第二層級內連層M2或第三層級內連層M3)。在其他實施例中，通孔開口是在溝槽之前形成。作為另外一種選擇，使用例如半調型罩幕(half tone mask)在同一製程期間形成溝槽與通孔開口。
繼續參照圖1B，溝槽及/或通孔開口可從頂部到底部漸縮。作為另外一種選擇，表面介電層BD1在形成溝槽及/或通孔開口的位置處包括實質上垂直的側壁。在一些實施例中，每一個溝槽的頂部寬度(或直徑)大於對應的通孔開口的頂部寬度(或直徑)。溝槽及對應的通孔開口的尺寸可依據隨後形成的第一接合連接件的功能及製程要求來決定大小。在一些實施例中，多個溝槽中的任一個溝槽的頂部寬度及與所述一個溝槽對應的通孔的頂部寬度不同於這些溝槽中的另一溝槽的頂部寬度及與所述另一溝槽對應的通孔的頂部寬度。
舉例來說，溝槽TR2的頂部寬度WT1大於溝槽TR3的頂部寬度WT2。在一些實施例中，溝槽TR0及/或溝槽TR1的頂部寬度可實質上相同於或類似於溝槽TR2的頂部寬度WT1。在一些實施例中，溝槽TR2的頂部寬度WT1介於約0.4μm到約5μm 的範圍內。在一些實施例中，溝槽TR4的頂部寬度可實質上相同於或類似於溝槽TR3的頂部寬度WT2。在一些實施例中，溝槽TR3的頂部寬度WT2介於約0.36μm到約4.5μm的範圍內。與溝槽TR2對應的通孔開口VO2的頂部寬度WV1可大於與溝槽TR3對應的通孔開口VO3的頂部寬度WV2。在一些實施例中，通孔開口VO1的頂部寬度可實質上相同於或類似於通孔開口VO2的頂部寬度WV1。在一些實施例中，通孔開口VO2的頂部寬度WV1介於約0.36μm到約2μm的範圍內。在一些實施例中，通孔開口VO4的頂部寬度可實質上相同於或類似於通孔開口VO3的頂部寬度WV2。在一些實施例中，通孔開口VO3的頂部寬度WV2介於約0.1μm到約2μm的範圍內。應注意，圖中所示的第一內連結構120的佈局僅為一個例子，頂部內連層Mt或下面的內連層可分佈在通孔開口VO2與通孔開口VO3之間及/或通孔開口VO3與通孔開口VO4之間。由於通孔開口VO3及/或VO4的寬度比通孔開口VO2的寬度窄，因此第一內連層122的分佈佈局面積可延伸得更寬且更加可行。
仍參照圖1B，在一些實施例中，通孔開口VO3的開口深度(或高度)DV2大於通孔開口VO2的開口深度DV1，以使通孔開口VO3比通孔開口VO2延伸得更遠，而暴露出頂部內連層Mt下方的第二層級內連層M2。暴露出第一接觸墊AP1的通孔開口VO1在通孔開口VO1、VO2、VO3及VO4中可具有最小的開口深度。應注意，圖1B中所示的通孔開口VO2及VO3僅為一個例子， 具有較窄寬度的通孔開口VO2及VO3可延伸至到達第一內連層122的位於頂部內連層Mt之下的任何層級(例如底部內連層M1、第二層級內連層M2、第三層級內連層M3)。在一些實施例中，具有較窄寬度的通孔開口VO2及/或VO3可向下延伸以暴露出第一半導體裝置112中的金屬柵極或鎢接觸件。通孔開口VO2的尺寸與通孔開口VO3的尺寸可相同或相似，但並非僅限於此。舉例來說，通孔開口VO2與通孔開口VO3可到達第一內連層122的位於頂部內連層Mt之下的同一層級或不同層級。作為另外一種選擇，省略通孔開口VO2及通孔開口VO3中的一者。具有較窄寬度的通孔開口的數量在本公開中不受限制。在一些實施例中，通孔開口VO3的高寬比(aspect ratio；開口深度DV2/頂部寬度WV2)大於通孔開口VO2的高寬比(開口深度DV1/頂部寬度WV1)。在一些實施例中，通孔開口VO3的高寬比(開口深度DV2/頂部寬度WV2)為約0.3到約20。通孔開口VO2的高寬比(開口深度DV1/頂部寬度WV1)可大於暴露出第一接觸墊AP1的通孔開口VO1的高寬比。
繼續參照圖1C，在形成第一表面介電層BD1之後，在溝槽(TR0、TR1、TR2、TR3及TR4)及通孔開口(VO1、VO2、VO3及VO4)中形成導電材料，以形成第一接合連接件(BC0、BC1、BC2、BC3及BC4)。在實施例中，形成第一接合連接件(BC0、BC1、BC2、BC3及BC4)的方法包括至少以下步驟。舉例來說，在第一表面介電層BD1上共形地形成擴散阻擋層(diffusion barrier layer；未示出)且擴散阻擋層覆蓋溝槽(TR0、TR1、TR2、TR3及TR4)的側壁及底部以及通孔開口(VO1、VO2、VO3及VO4)的側壁及底部，以與被通孔開口(VO1、VO2、VO3及VO4)暴露出的第一接觸墊AP1及內連層122實體接觸及電性接觸。擴散阻擋層可包含阻擋材料(例如鈦、氮化鈦、鉭、氮化鉭及其組合)，可利用例如物理氣相沉積(physical vapor deposition，PVD)或其他合適的沉積製程形成。接下來，可利用濺鍍(sputtering)、鍍覆(plating)或其他合適的沉積製程在擴散阻擋層上共形地形成晶種層(未示出)。舉例來說，晶種層可為銅層、鈦/銅雙層或有助於在後續處理步驟期間形成更厚的導電材料的其他合適的金屬層。隨後，利用鍍覆、印刷(printing)或其他合適的沉積製程在溝槽(TR0、TR1、TR2、TR3及TR4)及通孔開口(VO1、VO2、VO3及VO4)中形成導電材料(例如銅、鋁、銀、金、金屬合金等)以形成第一接合連接件(BC0、BC1、BC2、BC3及BC4)。之後，可利用平坦化製程(例如化學機械拋光(chemical mechanical polish，CMP))來移除過量的導電材料以形成平坦表面。應注意，可利用其他合適的技術形成第一接合連接件(BC0、BC1、BC2、BC3及BC4)。至此，實質上形成了半導體結構的第一層T1。在一些實施例中，半導體結構的第一層T1被視為半導體晶粒。在一些實施例中，第一層T1的上述製造步驟是以晶圓級來執行，在進行下一步驟(例如接合)之前第一層T1可被或可不被單體化成多個半導體晶粒(或晶圓)。
仍參照圖1C，第一層T1包括第一表面S1及與第一表面S1相對的第二表面S2。第一接合連接件(BC0、BC1、BC2、BC3及BC4)的頂表面與第一表面介電層BD1的頂表面在第一表面S1處可實質上齊平。第一層T1的第一接合連接件BC0在圖1C所示的剖面中可不接觸下面的導電特徵中的任何下面的導電特徵，舉例來說，第一接合連接件BC0作為金屬線或接合墊。在一些實施例中，第一層T1的第一接合連接件BC0是電性浮置的虛擬連接件或虛擬線。在一些實施例中，第一接合連接件(例如BC1、BC2、BC3及BC4)包括溝槽部分(或接墊部分)及從對應的溝槽部分向下延伸的通孔部分。第一接合連接件(BC0、BC1、BC2、BC3及BC4)的溝槽部分可實質上齊平。在一些實施例中，第一接合連接件(BC0、BC1、BC2、BC3及BC4)與第一表面介電層BD1實質上共面。在一些實施例中，第一接合連接件BC1的通孔部分從第一接合連接件BC1的溝槽部分到第一接觸墊AP1漸縮，第一接合連接件BC2的通孔部分從第一接合連接件BC2的溝槽部分到頂部內連層Mt漸縮，第一接合連接件BC3及BC4的通孔部分從第一接合連接件BC3及BC4的對應的溝槽部分到底部內連層M1及/或第一內連層122的中間層級漸縮。在一些實施例中，第一接合連接件BC3或BC4的通孔部分窄於且長於第一接合連接件BC1或BC2的通孔部分。在一些實施例中，第一接合連接件中的一者(例如BC1或BC2)的尺寸比第一接合連接件中的另一者(例如BC3或BC4)的尺寸大至少約四倍。
在一些實施例中，電源佈線(power routing)在第一內連結構120的至少頂部內連層Mt或在第一內連層122中的靠近第一表面介電層BD1的一些第一內連層122。舉例來說，直接連接到頂部內連層Mt的第一接合連接件BC2可作為用於電源分配的電源連接件(power connector)。在一些實施例中，藉由第一接觸墊AP1連接到頂部內連層Mt的第一接合連接件BC1也可作為電源連接件。在一些實施例中，訊號佈線(signal routing)在底部內連層M1及/或位於頂部內連層Mt下方的任何中間層級，第一接合連接件BC3及BC4可作為用於電訊號分配的訊號連接件，所述第一接合連接件BC3及BC4與在頂部內連層Mt之下的第一內連層122連接。由於連接到訊號佈線的第一接合連接件(例如BC3及BC4)比連接到電源佈線的第一接合連接件(例如BC1及BC2)更細，因此電源佈線可在不損害積體電路的其他特性的情況下延伸及分佈。由於第一接合連接件(例如BC3、BC4)較細，頂部內連層Mt的線距及間距(line and spacing)可增大，從而可實現電阻-電容延遲(RC delay)的減小且可改善電氣性能。應理解，第一接合連接件的實際尺寸取決於所採用的製程技術節點、所需的第一接合連接件的數量(無論是藉由特定的接合連接件傳遞電源還是傳遞訊號)以及基於產品需求的其他因素。
圖2A到圖2D是示出根據本公開一些實施例的半導體結構的第二層的製造方法中各個階段的示意性剖視圖。參照圖2A及圖2B，在第二半導體基板210上形成第二內連結構220(標示在 圖2C中)的第一部分220a。第二半導體基板210可包括形成在第二半導體基板210中的多個第二半導體裝置212。第二半導體基板210及第二半導體裝置212可相同於或類似於圖1A中所述的第一半導體基板110及第一半導體裝置112，因此為簡明起見，本文中不再對其予以贅述。第二內連結構220的第一部分220a可類似於圖1A中所述的第一內連結構120的下部部分。舉例來說，第一部分220a包括第二介電層224的一部分及嵌在第二介電層224的所述一部分中的第二內連層222的一部分。舉例來說，第一部分220a中的第二內連層222包括電性耦合到第二半導體裝置212的底部內連層M1及電性連接到底部內連層M1的第二層級內連層M2。應注意，儘管在圖2A及圖2B中示出了第一部分220a的兩個層級的內連結構，然而在第一部分220a中可形成更多或更少的內連層。第一部分220a的材料可類似於圖1A中所述的第一內連結構120的材料，為簡明起見不再對其予以贅述。
繼續參照圖2A，利用微影(lithography)及/或蝕刻或其他合適的技術在第一部分220a上形成開口OP且開口OP向下延伸到第二半導體基板210中。開口OP在俯視圖(未示出)中可包括圓形、橢圓形、正方形、矩形、多邊形或其他形狀。在一些實施例中，開口OP從第一部分220a到第二半導體基板210漸縮。作為另外一種選擇，依據形成製程而定，開口OP可具有實質上垂直的側壁。第二半導體裝置212及第二內連層222可位在遠離開口OP的地方。在此階段，開口OP不穿透過第二半導體基板210。 在其他實施例中，開口OP可穿透過第二半導體基板210。
隨後，如圖2B中所示，可利用鍍覆、印刷或其他合適的沉積製程在開口OP中形成導電材料，以形成半導體穿孔(through semiconductor via，TSV)230。舉例來說，可藉由以下方式形成導電材料：沉積一個或多個擴散阻擋層或隔離層、沉積晶種層、及藉由鍍覆或其他合適的製程將導電材料(例如鎢、鈦、鋁、銅、其任意組合及/或類似材料)沉積到開口OP中。在一些實施例中，利用平坦化製程(例如CMP製程)移除形成在第一部分220a上的過量的材料，以使TSV 230與第一部分220a(例如第一部分220a的介電層224的頂表面)實質上齊平。
參照圖2C，在第一部分220a及TSV 230上形成第二內連結構220的第二部分220b。第二內連結構220的第二部分220b可類似於圖1A中所述的第一內連結構120的上部部分。舉例來說，第二部分220b包括第二介電層224的一部分及嵌在第二介電層224的所述一部分中的第二內連層222的一部分。舉例來說，第二部分220b中的第二內連層222的所述一部分包括嵌在第二介電層224的所述一部分中且電性連接到第二層級內連層M2及TSV 230的第三層級內連層M3以及電性連接到第三層級內連層M3且嵌在第二介電層224的所述一部分中的頂部內連層Mt。應理解，第二內連結構220的第二部分220b可包括位於第一部分220a與頂部內連層Mt之間的多於一個內連層。第二部分220b的材料可類似於第一部分220a的材料，為簡明起見不再對其予以贅述。
在所示出的實施例中，TSV 230與第二內連層222的中間層級實體接觸及電性接觸。在其他實施例中，TSV 230與第二內連結構220的頂部內連層Mt或底部內連層M1實體接觸及電性接觸。應注意，儘管圖中僅示出一個TSV 230，然而依據設計要求而定，可形成多於一個TSV 230。在其他實施例中，可利用先形成通孔(via-first)製程形成TSV 230。舉例來說，在形成第二內連結構220之前形成TSV 230，以使TSV 230僅延伸到對第二半導體裝置212進行覆蓋的第二內連結構220的ILD層，而不延伸到第二內連結構220的IMD層中。作為另外一種選擇，可利用後形成通孔(via-last)製程來形成TSV 230(例如在形成第二內連結構220之後形成TSV)。
在形成第二內連結構220的第二部分220b之後，在第二內連結構220的第二部分220b上形成第二鈍化層PS2，在第二鈍化層PS2上形成第二接觸墊AP2，第二接觸墊AP2電性耦合到第二內連結構220的下面的第二內連層222。TSV 230與第二接觸墊AP2可藉由第二內連層222電性耦合。第二鈍化層PS2及第二接觸墊AP2的材料可類似於圖1A中所述的第一鈍化層PS1及第一接觸墊AP1的材料，因此為簡明起見不再對其予以贅述。
參照圖2D，在第二鈍化層PS2及第二接觸墊AP2上形成第二表面介電層BD2及多個第二接合連接件(例如BE0、BE1、BE2、BE3及BE4)。至此，便形成了半導體結構的第二層T2。在一些實施例中，半導體結構的第二層T2被視為半導體晶粒。第二 表面介電層BD2及第二接合連接件(BE0、BE1、BE2、BE3及BE4)的形成製程及材料可類似於圖1B及圖1C中所述的第一表面介電層BD1及第一接合連接件(BC0、BC1、BC2、BC3及BC4)的形成製程及材料，因此為簡明起見，本文中不再對其予以贅述。
在一些實施例中，延伸到第二內連結構220中以與內連層的中間層級(例如第二層級內連層M2)或底部內連層M1實體接觸及電性接觸的第二接合連接件中的一些第二接合連接件(例如BE3、BE4)可比與頂部內連層Mt及/或第二接觸墊AP2實體接觸及電性接觸的其他第二接合連接件(例如BE1、BE2)更細。在一些實施例中，第二接合連接件(BE0、BE1、BE2、BE3及BE4)的尺寸分別對應於第一接合連接件(BC0、BC1、BC2、BC3及BC4)的尺寸。第二層T2可包括彼此相對的第三表面S3與第四表面S4。第二接合連接件(BE0、BE1、BE2、BE3及BE4)與第二表面介電層BD2可在第三表面S3處實質上齊平。在一些實施例中，由於第二接合連接件(例如BC1、BC2、BC3及BC4)的形成，引入到TSV 230的電源或訊號可藉由具有不同長度的第二接合連接件來提供。在一些實施例中，與傳統結構相比，在第二層T2中，通往位於不同內連層上的導電特徵的路徑明顯縮短，從而提高了電源連接效率。在此階段，TSV 230可被或可不被以可觸及的方式在第四表面S4處顯露出。第二層T2的上述製造步驟可在晶圓級來執行，在進行下一步驟(例如接合)之前第二層T2可被或可不被單體化成多個半導體晶粒(或晶圓)。
圖3A到圖3D是示出根據本公開一些實施例的半導體結構的製造方法中各個階段的示意性剖視圖。參照圖3A，將第一層T1與第二層T2以面對面(face-to-face)的配置形式接合在一起。舉例來說，將第一層T1與第二層T2以第一層T1的第一表面S1與第二層T2的第三表面S3彼此面對的方式佈置，對第一層T1與第二層T2進行接合。在一些實施例中，第一層T1與第二層T2之間的接合介面IF包括介電質對介電質(dielectric-to-dielectric)接合(例如氧化物對氧化物接合)、金屬對金屬(metal-to-metal)接合(例如銅對銅接合)、金屬對介電質(metal-to-dielectric)接合(例如銅對氧化物接合)、其任意組合及/或類似的接合技術。
在一些實施例中，分開製作第一層T1與第二層T2，對第一層T1與第二層T2執行混合接合製程(hybrid bonding process)。舉例來說，為有利於混合接合，執行對接合表面(例如第一層T1的第一表面S1與第二層T2的第三表面S3)的表面準備(surface preparation)以移除所述表面上的顆粒。表面準備可包括表面清潔及活化(activation)或其他合適的製程。在一些實施例中，在執行接合製程之前可藉由濕式清潔(wet cleaning)來對第一接合連接件(BC0、BC1、BC2、BC3及BC4)的頂表面及第二接合連接件(BE0、BE1、BE2、BE3及BE4)的頂表面進行清潔。藉由例如在濕式清潔中使用的化學製品(chemical)，不僅會移除顆粒，而且還可移除形成在第一層T1的第一接合連接件(BC0、BC1、BC2、BC3及BC4)的頂表面及第二層T2的第二接合連接件(BE0、 BE1、BE2、BE3及BE4)的頂表面上的原生氧化物(native oxide)。在清潔之後，可執行對第一表面介電層BD1的頂表面及第二表面介電層BD2的頂表面的活化以產生高的接合強度。在一些實施例中，可執行電漿活化(plasma activation)以對第一表面介電層BD1的頂表面及第二表面介電層BD2的頂表面進行處理。
在一些實施例中，第一層T1與第二層T2對準且可實現亞微米(sub-micron)對準精度。舉例來說，每一第一接合連接件(BC0、BC1、BC2、BC3及BC4)可與對應的第二接合連接件(BE0、BE1、BE2、BE3及BE4)實質上對準。在一些實施例中，作為第一層T1的電源連接件的第一接合連接件中的一些第一接合連接件(例如BC1、BC2)與同樣作為第二層T2的電源連接件的第二接合連接件(例如BE1、BE2)實質上對準。舉例來說，第一層T1及第二層T2中的電源連接具有短的路徑，從而減小了電源路徑的電阻。作為第一層T1的訊號連接件的第一接合連接件中的一些第一接合連接件(例如BC3、BC4)可與同樣作為第二層T2的訊號連接件的第二接合連接件(例如BE3、BE4)實質上對準。一旦第一層T1與第二層T2精確地對準，便將第一層T1或第二層T2放置在彼此上且使第一層T1與第二層T2彼此接觸。當第一層T1的第一表面介電層BD1的經活化的頂表面與第二層T2的第二表面介電層BD2的經活化的頂表面接觸時，對第一層T1的第一表面介電層BD1與第二層T2的第二表面介電層BD2進行預接合(pre-bond)。換句話說，藉由第一表面介電層BD1與第二表面介 電層BD2的預接合對第一層T1與第二層T2進行預接合。在預接合之後，第一接合連接件(BC0、BC1、BC2、BC3及BC4)可分別對應於第二接合連接件(BE0、BE1、BE2、BE3及BE4)且可與第二接合連接件(BE0、BE1、BE2、BE3及BE4)實體接觸。
在一些實施例中，在對第一層T1與第二層T2進行預接合之後，執行對第一層T1與第二層T2的混合接合。第一層T1與第二層T2的混合接合可包括用於介電質接合的處理、用於增強第一表面介電層BD1與第二表面介電層BD2之間的接合的處理、以及熱退火(thermal annealing)的處理，這些處理有利於第一層T1的第一接合連接件(BC0、BC1、BC2、BC3及BC4)與第二層T2的第二接合連接件(BE0、BE1、BE2、BE3及BE4)之間的接合。在一些實施例中，用於連接件接合的熱退火的製程溫度高於用於介電質接合的處理的製程溫度。由於對第一層T1的第一接合連接件(BC0、BC1、BC2、BC3及BC4)及第二層T2的第二接合連接件(BE0、BE1、BE2、BE3及BE4)執行的熱退火是在相對較高的溫度下執行，因此在第一層T1的第一接合連接件(BC0、BC1、BC2、BC3及BC4)與第二層T2的第二接合連接件(BE0、BE1、BE2、BE3及BE4)之間的接合介面IF處可能會發生金屬擴散及晶粒生長(grain growth)。在執行對第一層T1與第二層T2的接合之後，第一接合連接件(BC0、BC1、BC2、BC3及BC4)及第二接合連接件(BE0、BE1、BE2、BE3及BE4)在第一層T1與第二層T2之間提供垂直電性連接，第一層T1的第一內連結構 120與第二層T2的第二內連結構220藉由第一接合連接件(BC0、BC1、BC2、BC3及BC4)及第二接合連接件(BE0、BE1、BE2、BE3及BE4)而彼此實體接觸及電性接觸。
參照圖3B，在對第一層T1與第二層T2進行接合之後，可對第二層T2的第四表面S4(標示在圖3A中)執行薄化製程(thinning process)，從而TSV 230以可觸及的方式被顯露出。舉例來說，將第二半導體基板210薄化到暴露出TSV 230為止。在一些實施例中，可在薄化製程期間稍微移除TSV 230。薄化製程可包括研磨(grinding)、拋光及/或蝕刻或其他合適的技術。在一些實施例中，在第二層T2的經薄化的第四表面S4’之上形成隔離層240。舉例來說，隔離層240包含藉由第二半導體基板210的熱氧化形成的氧化物。在其他實施例中，隔離層240是利用沉積製程或其他合適的技術形成且可包含氧化矽、氮化矽等。在形成之後，TSV 230可至少在橫向上被隔離層240覆蓋。
參照圖3C，在隔離層240及TSV 230上形成重佈線結構250。重佈線結構250可包括至少一個圖案化介電層254及設置在圖案化介電層254中的至少一個圖案化導電層252(例如導線、導通孔、接墊)。舉例來說，可利用合適的沉積技術、圖案化技術及金屬化技術(例如介電質沉積、微影、蝕刻、晶種層沉積、鍍覆、平坦化等)或其他合適的製程形成圖案化導電層252及圖案化介電層254。應注意，儘管圖3C中繪示兩層式的重佈線結構，然而重佈線結構250可包括更多或更少的圖案化導電層及圖案化介電 層。圖案化導電層及圖案化介電層的數量並非僅限於此。
圖案化導電層中的最底層252a可嵌在圖案化介電層中的最底層254a中且可與下面的TSV 230實體接觸及電性接觸。TSV 230可包括連接到第二內連結構220及重佈線結構250的傾斜側壁。舉例來說，TSV 230從第二內連結構220到重佈線結構250的圖案化導電層中的最底層252a漸縮。圖案化導電層中的最頂層252b可被圖案化介電層中的最頂層254b以可觸及的方式顯露出。在一些實施例中，圖案化導電層中的最頂層252b包括外部接觸墊AP3以進行進一步電性連接。外部接觸墊AP3可為用於後續植球製程(ball-mounting process)的凸塊下金屬(under-bump metallurgy，UBM)接墊。外部接觸墊AP3可包含與第一接觸墊AP1或第二接觸墊AP2相似的材料。應注意，雖僅示出一個外部接觸墊AP3，但外部接觸墊AP3的數量在本公開中不受限制。
在一些實施例中，圖案化介電層中的最頂層254b可包含一種或多種合適的鈍化材料及/或保護材料，以為下面的導電特徵提供一定程度的保護。舉例來說，圖案化介電層中的最頂層254b包括鈍化層(例如氧化矽層、氮化矽層、其組合等)、聚合物層(例如環氧樹脂層、聚醯亞胺層、苯並環丁烯(benzocyclobutene，BCB)層、聚苯並噁唑(polybenzoxazole，PBO)層等)或由其他合適的電絕緣材料製成的介電層。重佈線結構250的圖案化導電層252可對下面的電路系統進行重新佈線且可對第一層T1及第二層T2的訊號或電源進行重新佈線。
參照圖3D，在重佈線結構250上形成外部端子260。舉例來說，在圖案化導電層中的最頂層252b的外部接觸墊AP3上形成排列成陣列的多個外部端子260(例如導電球)。在一些實施例中，外部端子260可為藉由植球(ball placement)及回焊(reflowing)製程形成的焊球。在一些其他實施例中，外部端子260可為或可包括銅柱、受控塌陷晶片連接(controlled collapse chip connection，C4)凸塊、微凸塊(micro-bump)、銅層、鎳層、無鉛(lead free，LF)層、無電鍍鎳鈀浸金(electroless nickel electroless palladium immersion gold，ENEPIG)層、Cu/LF層、Sn/Ag層、Sn/Pb層、其組合等。應注意，可利用任何合適的外部端子及任何合適的製程來形成外部端子260。
在一些實施例中，在形成外部端子260之後，可沿切割道(scribe line；未示出)執行單體化製程以將所得結構切成多個半導體結構10。在一些實施例中，上述步驟可以用晶圓對晶圓級(wafer-to-wafer level)來執行，其中第一層T1及第二層T2是以晶圓的形式提供來用於接合，在接合之後，將接合的結構單體化而成多個半導體結構10。在其他實施例中，上述步驟可以晶粒對晶粒級(die-to-die level)或晶粒對晶圓級(die-to-wafer level)來執行，其中在接合之前將第一層T1及第二層T2中的至少一者單體化成多個半導體晶粒(或晶圓)。
如圖3D中所示，半導體結構10包括垂直堆疊且整合在一起的第一層T1與第二層T2。在一些實施例中，包括積體電路 的半導體結構10可在一個積體電路(integrated circuit，IC)元件中提供整個系統。在一些實施例中，TSV 230用於藉由第二層T2的背側提供用於將積體電路接地的短的接地路徑(grounding path)，第二層T2的背側可被接地金屬膜(grounded metallic film；未示出)覆蓋。應注意，圖3A到圖3D中所示的接墊對接墊(pad-to-pad)接合(即將第一接合連接件(BC0、BC1、BC2、BC3及BC4)的溝槽部分接合到第二接合連接件(BE0、BE1、BE2、BE3及BE4)的溝槽部分)的所示實施例僅為一個例子，第一層T1及/或第二層T2的接合連接件可為或可包括導通孔(例如銅通孔)、導電墊(例如銅墊)或其組合。舉例來說，第一層T1的第一接合連接件(BC0、BC1、BC2、BC3及BC4)與第二層T2的第二接合連接件(BE0、BE1、BE2、BE3及BE4)之間的接合可為通孔對通孔(via-to-via)接合、接墊對接墊接合或通孔對接墊(via-to-pad)接合，將在以下的其他實施例中進行更詳細的闡述。
圖4是示出根據本公開一些實施例的半導體結構的第一層的示意性剖視圖。參照圖4，第一層T1’類似於圖1C中所示的第一層T1，第一層T1’與第一層T1之間的不同之處在於第一接合連接件。為易於理解，所有圖式中相同的元件使用相同的標號且本文中不再對其予以重複贅述。舉例來說，在第一層T1’的第一表面介電層BD3上形成多個通孔開口(未示出)，在第一表面介電層BD3上未形成溝槽。在一些實施例中，通孔開口的至少一部分可利用單鑲嵌製程或其他合適的技術向下延伸到第一內連結構120 中。接下來，在通孔開口中形成導電材料，以形成多個第一接合連接件(例如BF0、BF1、BF2、BF3及BF4)。在一些實施例中，第一接合連接件(BF0、BF1、BF2、BF3及BF4)具有傾斜側壁且可在第一層T1’的厚度方向TD上從第一表面S1’朝第二表面S2漸縮。作為另外一種選擇，每一個第一接合連接件(例如BF0、BF1、BF2、BF3及BF4)包括實質上垂直的側壁。
在一些實施例中，第一接合連接件中的一些第一接合連接件(例如BF3、BF4)與位於頂部內連層Mt之下的第一內連層122實體接觸及電性接觸。在一些實施例中，第一接合連接件中的一些第一接合連接件(例如BF1、BF2)與第一接觸墊AP1及/或頂部內連層Mt實體接觸及電性接觸，其他第一接合連接件(例如BF0)可作為虛擬連接件。在一些實施例中，與位於頂部內連層Mt之下的第一內連層122連接的第一接合連接件(例如BF3、BF4)具有相同或相似的頂部寬度。其餘的第一接合連接件(例如BF0、BF1、BF2)的頂部寬度可彼此相同或相似，但可不同於與位於頂部內連層Mt之下的第一內連層122連接的第一接合連接件(例如BF3、BF4)的頂部寬度。以第一接合連接件BF2及BF3為例，第一接合連接件BF2的頂部寬度W1大於第一接合連接件BF3的頂部寬度W2，第一接合連接件BF3比第一接合連接件BF2從第一層T1’的第一表面S1’延伸得更遠。在一些實施例中，第一接合連接件BF2的頂部寬度W1介於約0.3μm到約4.5μm的範圍內。在一些實施例中，第一接合連接件BF3的頂部寬度W2介於約0.1μm 到約2.5μm的範圍內。第一接合連接件BF3可比第一接合連接件BF2更細且比第一接合連接件BF2更長。在一些實施例中，第一接合連接件BF3的高寬比(高度/頂部寬度)為約0.3到約20。
在一些實施例中，利用通孔對接墊接合(即將第一接合連接件(BF0、BF1、BF2、BF3及BF4)接合到第二接合連接件(BE0、BE1、BE2、BE3及BE4)的溝槽部分)將第一層T1’以面對面的配置形式接合到圖2D中所示的第二層T2，以形成接合結構，接著可對接合結構進行處理以形成半導體結構(未示出)。在其他實施例中，可利用通孔對通孔接合(即將第一層T1’中的一者的第一接合連接件接合到第一層T1’中的另一者的第一接合連接件)將兩個第一層T1’以面對面的配置形式接合在一起，以形成接合結構，接著可在第一半導體基板中的至少一者上形成TSV、重佈線結構及外部端子，以提供對外部元件的電性連接。應注意，依據設計要求而定，可以任何組合形式在垂直方向上堆疊任何數量的第一層T1或T1’及/或第二層T2，不同的層可至少藉由接合連接件、TSV及其他導電特徵而彼此電性連通。
圖5A到圖5C是示出根據本公開一些實施例的半導體結構的製造方法中各個階段的示意性局部剖視圖。應注意，圖5A到圖5C僅示出所述結構的一部分。舉例來說，可形成兩個圖1C中所示的第一層T1(或兩個圖4中所示的第一層T1’)，接著將所述兩個第一層T1(或所述兩個第一層T1’)以面對面的配置形式接合在一起以形成接合結構，圖5A到圖5C可示出接合結構的第一 層T1(或圖4中所示的第一層T1’)中的一者。在一些實施例中，可將第一層T1與第二層T2接合在一起以形成圖3A中所示的接合結構，圖5A到圖5C可示出在對接合結構進行翻轉(例如上下顛倒)之後接合結構的第一層T1。作為另外一種選擇，接合結構的第一層T1可由圖4中所示的第一層T1’取代。應注意，接合結構可包括多於兩個彼此堆疊及接合的層，接合結構的堆疊層數在本公開中不受限制。
參照圖5A及圖5B，在第一半導體基板110上形成開口OP。舉例來說，開口OP穿過第一半導體基板110且向下延伸到第一內連結構120，從而以可觸及的方式暴露出第一內連層122。開口OP可從第一半導體基板110到第一內連層122漸縮。作為另外一種選擇，開口OP可包括實質上垂直的側壁。應注意，依據設計要求而定，開口OP可延伸至暴露出第一內連層122的任何層級，圖5A的說明僅為一個例子。隨後，在開口OP中形成導電材料以形成TSV 330。舉例來說，TSV 330與第一內連層122中的任何層級實體接觸及電性接觸。TSV 330的材料可類似於圖2B中所述的TSV 230的材料，因此為簡明起見不再對其予以贅述。舉例來說，可利用鍍覆、印刷或其他合適的沉積製程來形成導電材料，接著可利用例如CMP製程來移除過量的材料，以使TSV 330可與第一半導體基板110的第二表面S2實質上齊平。
參照圖5C，在第一半導體基板110的第二表面S2及TSV 330上形成重佈線結構250，接著在重佈線結構250上形成外部端 子260。重佈線結構250的圖案化導電層中的最底層252a可與TSV 330實體接觸及電性接觸。重佈線結構250及外部端子260可藉由TSV 330電性耦合到第一內連結構120。在一些實施例中，TSV 330可具有傾斜的側壁且可從圖案化導電層中的最底層252a到第一內連層122漸縮。重佈線結構250及外部端子260的形成製程及材料可類似於圖3C及圖3D中所述的重佈線結構250及外部端子260的形成製程及材料，因此為簡明起見不再對其予以贅述。在形成重佈線結構250及外部端子260之後，可沿切割道(未示出)執行單體化製程以將所得結構切成多個半導體結構20。
圖6是示出根據本公開一些實施例的半導體結構的示意性剖視圖。參照圖6，提供包括第一層T1及堆疊在第一層T1上的第三層T3的半導體結構30。在一些實施例中，第一層T1與第三層T3以面對背(face-to-back)的配置形式接合在一起。舉例來說，第三層T3包括第二半導體裝置212的第二半導體基板210、形成在第二半導體基板210上且電性耦合到第二半導體基板210的第二內連結構220以及與頂部內連層Mt實體接觸及電性接觸的第二接觸墊AP2。在一些實施例中，第三層T3包括第三表面介電層BD4以及多個第三接合連接件(例如BG1及BG2)，所述第三表面介電層BD4在第二半導體基板210上與第二內連結構220相對地形成，所述多個第三接合連接件(例如BG1及BG2)穿透過第三表面介電層BD4及第二半導體基板210以與第二內連結構220的第二內連層222實體接觸及電性接觸。舉例來說，第三接合 連接件BG1從第一層T1與第三層T3之間的接合介面IF’延伸、穿過第二半導體基板210且延伸到第二介電層224中，以到達第二內連層222的頂部內連層Mt。在一些實施例中，第三接合連接件BG2從接合介面IF’延伸、穿過第二半導體基板210且延伸到第二介電層224中，以至第二內連層222的中間層級(例如第二層級內連層M2)或第二內連層222的底部內連層M1。第三接合連接件BG1可比第三接合連接件BG2從接合介面IF’延伸得更遠。在一些實施例中，第三接合連接件BG1及第三接合連接件BG2對應地接合到可分別作為電源連接件及訊號連接件的第一接合連接件BC1及第一接合連接件BC4。
應理解，第三接合連接件(例如BG1、BG2)可依據產品要求而與第二內連層222中的任何層級接觸，圖6中所示的第三接合連接件的配置僅為一個例子。第三接合連接件(例如BG1及BG2)的數量可對應於或可不對應於第一層T1的第一接合連接件(例如BC0、BC1、BC2、BC3及BC4)的數量。第三接合連接件(例如BG1及BG2)可在形成第三表面介電層BD4之後形成。在其他實施例中，穿過第二半導體基板210且延伸到第二內連結構220中的第三接合連接件(例如BG1及BG2)的一些部分可在第三接合連接件(例如BG1及BG2)的在橫向上嵌在第三表面介電層BD4中的部分之前形成。
在一些實施例中，將第一層T1與第三層T3以第一層T1的第一表面S1與第三層T3的第五表面S5彼此面對的方式佈置且 對第一層T1與第三層T3進行接合。第三接合連接件(例如BG1及BG2)與第三表面介電層BD4可在第三層T3的第五表面S5處實質上齊平。在一些實施例中，第一層T1與第三層T3之間的接合介面IF’包括介電質對介電質接合(例如氧化物對氧化物接合)、金屬對金屬接合(例如銅對銅接合)、金屬對介電質接合(例如銅對氧化物接合)、其任意組合及/或類似接合。接合介面IF’可位於第一層T1的第一表面介電層BD1與第三層T3的第三表面介電層BD4之間。第一層T1的第一表面介電層BD1及第三層T3的第三表面介電層BD4可位於第一層T1的第一內連結構120與第三層T3的第二半導體基板210之間。
在一些實施例中，與第二內連層222的頂部內連層Mt電性連接的第二接觸墊AP2可作為外部接墊，可在第二接觸墊AP2上形成外部端子260。舉例來說，形成在第二鈍化層PS2上的第三鈍化層PS3可以可觸及的方式顯露出用於隨後形成的外部端子260的第二接觸墊AP2的至少一部分。外部端子260可藉由第二接觸墊AP2及第二內連層222電性耦合到第二半導體裝置212。在一些實施例中，第一層T1的電源訊號或電訊號可藉由第三接合連接件(例如BG1、BG2)、第二內連層222及第二接觸墊AP2傳輸到外部端子260。應理解，半導體結構30可包括多於兩層且接合連接件及/或TSV可用於提供兩個相鄰的層之間的垂直電性連接。
圖7是示出根據本公開一些實施例的半導體結構的應用 的示意性剖視圖。參照圖7，提供包括第一元件42及設置在第一元件42之上的第二元件44的結構40。第一元件42可為或可包括印刷電路板(printed circuit board，PCB)、印刷配線板(printed wiring board)、中介層、封裝基板及/或能夠承載積體電路的其他載體。在一些實施例中，安裝在第一元件42上的第二元件44類似於以上分別結合圖3D、圖5C及圖6所闡述的半導體結構10、20或30。舉例來說，半導體結構10、20或30可藉由多個端子44a(例如外部端子260)電性耦合到第一元件42。在一些其他實施例中，安裝在第一元件42上的第二元件44可以是包括封裝在其中的至少一個半導體結構(例如以上結合圖3D、圖5C及圖6所闡述的半導體結構10、20或30)的整合扇出型(integrated fan-out，InFO)封裝。舉例來說，第二元件44可包括多個半導體結構(例如以上結合圖3D、圖5C及圖6所闡述的半導體結構10、20或30的任意組合)、扇出型重佈線結構(未示出)及多個端子44a，所述多個半導體結構被絕緣包封體(未示出)分隔地在橫向上包封，所述扇出型重佈線結構可形成在絕緣包封體及這些半導體結構上以電性耦合到這些半導體結構，所述多個端子44a形成在扇出型重佈線結構上以電性耦合到扇出型重佈線結構及第一元件42。可利用其他封裝技術，所述封裝技術在本公開中不受限制。結構40可為例如以下裝置的電子系統的部分：電腦(例如高性能電腦(high-performance computer，HPC))、與人工智慧(artificial intelligence，AI)系統結合使用的計算裝置、無線通訊裝置、電 腦相關的周邊設備、娛樂裝置等。應注意，也可存在其他應用。
根據本公開的一些實施例，提供一種半導體結構，所述半導體結構包括半導體基板、多個內連層、第一連接件(例如為上述的第一接合連接件BC2)及第二連接件(例如為上述的第一接合連接件BC3或BC4)。所述半導體基板在所述半導體基板中包括多個半導體裝置。所述內連層設置在所述半導體基板之上且電性耦合到所述半導體裝置。所述第一連接件設置在所述多個內連層之上且延伸到與所述多個內連層的第一層級接觸。所述第二連接件設置在所述多個內連層之上且與所述第一連接件實質上齊平。所述第二連接件比所述第一連接件延伸得更遠，以與位於所述多個內連層的所述第一層級與所述半導體基板之間的所述多個內連層的第二層級接觸，所述第一連接件寬於所述第二連接件。
在一些實施例中，半導體結構還包括接觸墊，所述接觸墊設置在所述多個內連層的所述第一層級之上且藉由所述多個內連層電性耦合到所述半導體基板的所述半導體裝置。在一些實施例中，半導體結構還包括第三連接件(例如為上述的第一接合連接件BC1)，所述第三連接件的頂表面與所述第一連接件的頂表面及所述第二連接件的頂表面實質上齊平，所述第三連接件延伸到與所述接觸墊接觸。在一些實施例中，所述第三連接件的高寬比小於所述第二連接件的高寬比。在一些實施例中，所述第二連接件的高寬比介於約0.3到約20的範圍內。在一些實施例中，半導體結構還包括半導體穿孔，所述半導體穿孔穿透過所述半導體基 板以與所述多個內連層中的任一個接觸，所述半導體穿孔藉由所述多個內連層電性耦合到所述半導體基板的所述半導體裝置。在一些實施例中，所述半導體穿孔從所述多個內連層中的所述一個到所述半導體基板漸縮。
根據本公開的一些實施例，提供一種半導體結構，所述半導體結構包括第一半導體晶粒及堆疊在所述第一半導體晶粒上且接合到所述第一半導體晶粒的第二半導體晶粒。所述第一半導體晶粒包括第一接合連接件(例如為上述的第一接合連接件BC2)及第二接合連接件(例如為上述的第一接合連接件BC3)。所述第二接合連接件的高度對寬度的比例大於所述第一接合連接件的高度對寬度的比例。所述第二半導體晶粒包括接合到所述第一半導體晶粒的所述第一接合連接件的第三接合連接件(例如為上述的第二接合連接件BE2)以及接合到所述第一半導體晶粒的所述第二接合連接件的第四接合連接件(例如為上述的第二接合連接件BE3)。所述第三接合連接件的尺寸及所述第四接合連接件的尺寸分別對應於所述第一接合連接件的尺寸及所述第二接合連接件的尺寸。
在一些實施例中，所述第一半導體晶粒的所述第一接合連接件在所述第一半導體晶粒與所述第二半導體晶粒之間的接合介面處與所述第一半導體晶粒的所述第二接合連接件實質上齊平。在一些實施例中，所述第一接合連接件及所述第二接合連接件在所述第一半導體晶粒的厚度方向上延伸，所述第二接合連接件比 所述第一接合連接件從所述接合介面延伸得更遠。在一些實施例中，所述第一半導體晶粒還包括第一半導體基板以及多個第一內連層，所述第一半導體基板在所述第一半導體基板中包括多個第一半導體裝置，所述多個第一內連層設置在所述第一半導體基板之上且電性耦合到所述第一半導體裝置，其中所述第一接合連接件設置在所述多個第一內連層之上且從位於所述第一半導體晶粒與所述第二半導體晶粒之間的接合介面延伸到所述多個第一內連層的第一層級。在一些實施例中，所述第一半導體晶粒的所述第二接合連接件設置在所述多個第一內連層之上且從所述接合介面延伸到位於所述第一半導體基板與所述多個第一內連層的所述第一層級之間的所述多個第一內連層的第二層級。在一些實施例中，所述第一半導體晶粒還包括第一半導體穿孔，所述第一半導體穿孔穿透過所述第一半導體基板以與所述多個第一內連層中的任一層接觸。在一些實施例中，所述第一半導體晶粒還包括外部接觸墊以及外部端子，所述外部接觸墊與所述多個第一內連層相對地設置在所述第一半導體基板之上且電性耦合到所述第一半導體穿孔，所述外部端子設置在所述外部接觸墊上且電性耦合到所述外部接觸墊。在一些實施例中，所述第二半導體晶粒還包括第二半導體基板以及多個第二內連層，所述第二半導體基板在所述第二半導體基板中包括多個第二半導體裝置，所述多個第二內連層設置在所述第二半導體基板之上且電性耦合到所述第二半導體裝置，其中所述第一半導體晶粒與所述第二半導體晶粒之間的所述接合 介面位於所述第二半導體晶粒的所述第二半導體基板與所述第一半導體晶粒的所述多個第一內連層的所述第一層級之間。在一些實施例中，所述第二半導體晶粒的所述第二半導體基板及所述第一半導體晶粒的所述多個第一內連層位於所述第二半導體晶粒的所述多個第二內連層與所述第一半導體晶粒的所述第一半導體基板之間，所述第二半導體晶粒的所述第三接合連接件及所述第四接合連接件穿透過所述第二半導體基板以與所述多個第二內連層中的任一層接觸。
根據本公開的一些實施例，一種半導體結構的製造方法包括至少以下步驟。在第一半導體基板之上的第一內連結構上形成第一表面介電層(例如為圖1C中的第一表面介電層BD1或例如為圖2D中的第二表面介電層BD2)。形成第一通孔開口及第二通孔開口，其中所述第二通孔開口穿透過所述第一表面介電層且比所述第一通孔開口延伸得更遠，以可觸及的方式顯露出所述第一內連結構的至少一部分，所述第二通孔開口比所述第一通孔開口窄。在所述第一通孔開口及所述第二通孔開口中形成導電材料，以對應地形成第一接合連接件及第二接合連接件。
在一些實施例中，所述的製造方法還包括將第二表面介電層、第三接合連接件及第四接合連接件分別接合到所述第一表面介電層、所述第一接合連接件及所述第二接合連接件，其中所述第三接合連接件的尺寸及所述第四接合連接件的尺寸對應於所述第一接合連接件的尺寸及所述第二接合連接件的尺寸。在一些 實施例中，執行鑲嵌製程以形成所述第一通孔開口及所述第二通孔開口，其中所述第二通孔開口的高寬比大於所述第一通孔開口的高寬比。在一些實施例中，在形成所述第一表面介電層(例如為圖2D中的第二表面介電層BD2)之前，所述製造方法還包括在所述第一半導體基板上形成所述第一內連結構的一部分、形成從所述第一內連結構的所述一部分延伸到所述第一半導體基板的半導體穿孔、以及在所述第一內連結構的所述一部分及所述半導體穿孔上形成所述第一內連結構的其餘部分。
雖然本發明已以實施例揭露如上，然其並非用以界定本發明的實施例，任何所屬技術領域中具有通常知識者，在不脫離本發明實施例的精神和範圍內，當可作些許的更動與潤飾，故本發明的保護範圍當視後附的申請專利範圍所界定者為準。
110:第一半導體基板
112:第一半導體裝置
120:第一內連結構
122:第一內連層/內連層
124:第一介電層
AP1:第一接觸墊
BC0、BC1、BC2、BC3、BC4:第一接合連接件
BD1:第一表面介電層/表面介電層
M1:底部內連層
M2:第二層級內連層
M3:第三層級內連層
Mt:頂部內連層
PS1:第一鈍化層
S1:第一表面
S2:第二表面
T1:第一層
TR0、TR1、TR2、TR3、TR4:溝槽
VO1、VO2、VO3、VO4:通孔開口

Claims (10)

  1. 一種半導體結構，包括：半導體基板，在所述半導體基板中包括多個半導體裝置；多個內連層，設置在所述半導體基板之上且電性耦合到所述半導體裝置；第一連接件，設置在所述多個內連層之上且延伸到與所述多個內連層的第一層級接觸，其中所述多個內連層的所述第一層級包括電源佈線；以及第二連接件，設置在所述多個內連層之上且與所述第一連接件實質上齊平，所述第二連接件比所述第一連接件延伸得更遠，以與位於所述多個內連層的所述第一層級與所述半導體基板之間的所述多個內連層的第二層級接觸，所述第一連接件寬於所述第二連接件，其中所述多個內連層的所述第二層級包括訊號佈線。
  2. 如申請專利範圍第1項所述的半導體結構，還包括：接觸墊，設置在所述多個內連層的所述第一層級之上且藉由所述多個內連層電性耦合到所述半導體基板的所述半導體裝置。
  3. 如申請專利範圍第2項所述的半導體結構，還包括：第三連接件，所述第三連接件的頂表面與所述第一連接件的頂表面及所述第二連接件的頂表面實質上齊平，所述第三連接件延伸到與所述接觸墊接觸。
  4. 如申請專利範圍第1項所述的半導體結構，還包括：半導體穿孔，穿透過所述半導體基板以與所述多個內連層中 的任一個接觸，所述半導體穿孔藉由所述多個內連層電性耦合到所述半導體基板的所述半導體裝置。
  5. 一種半導體結構，包括：第一半導體晶粒，包括虛擬連接件、第一接合連接件及第二接合連接件，所述第二接合連接件的高度對寬度的比例大於所述第一接合連接件的高度對寬度的比例，所述虛擬連接件設置在所述第一接合連接件旁且為電性浮置；以及第二半導體晶粒，堆疊在所述第一半導體晶粒上且接合到所述第一半導體晶粒，所述第二半導體晶粒包括接合到所述第一半導體晶粒的所述第一接合連接件的第三接合連接件及接合到所述第一半導體晶粒的所述第二接合連接件的第四接合連接件，其中所述第三接合連接件的尺寸及所述第四接合連接件的尺寸分別對應於所述第一接合連接件的尺寸及所述第二接合連接件的尺寸。
  6. 如申請專利範圍第5項所述的半導體結構，其中所述第一半導體晶粒的所述第一接合連接件在所述第一半導體晶粒與所述第二半導體晶粒之間的接合介面處與所述第一半導體晶粒的所述第二接合連接件實質上齊平。
  7. 如申請專利範圍第5項所述的半導體結構，其中所述第一半導體晶粒還包括：第一半導體基板，在所述第一半導體基板中包括多個第一半導體裝置；以及多個第一內連層，設置在所述第一半導體基板之上且電性耦 合到所述第一半導體裝置，其中所述第一接合連接件設置在所述多個第一內連層之上且從位於所述第一半導體晶粒與所述第二半導體晶粒之間的接合介面延伸到所述多個第一內連層的第一層級。
  8. 一種半導體結構的製造方法，包括：在第一半導體基板上形成第一內連結構的一部分；形成從所述第一內連結構的所述一部分延伸到所述第一半導體基板的半導體穿孔；在所述第一內連結構的所述一部分及所述半導體穿孔上形成所述第一內連結構的其餘部分；在所述第一半導體基板之上的所述第一內連結構的所述其餘部分上形成第一表面介電層；形成第一通孔開口及第二通孔開口，其中所述第二通孔開口穿透過所述第一表面介電層且比所述第一通孔開口延伸得更遠，以能夠觸及的方式顯露出所述第一內連結構的至少一部分，所述第二通孔開口比所述第一通孔開口窄；以及在所述第一通孔開口及所述第二通孔開口中形成導電材料，以對應地形成第一接合連接件及第二接合連接件。
  9. 如申請專利範圍第8項所述的半導體結構的製造方法，還包括：將第二表面介電層、第三接合連接件及第四接合連接件分別接合到所述第一表面介電層、所述第一接合連接件及所述第二接 合連接件，其中所述第三接合連接件的尺寸及所述第四接合連接件的尺寸對應於所述第一接合連接件的尺寸及所述第二接合連接件的尺寸。
  10. 如申請專利範圍第8項所述的半導體結構的製造方法，其中：在形成所述第一通孔開口及所述第二通孔開口之前，形成溝槽在所述第一表面介電層，其中在形成所述第一通孔開口及所述第二通孔開口之後，所述溝槽在所述第一通孔開口旁；以及在所述第一通孔開口及所述第二通孔開口中形成所述導電材料時，形成所述導電材料在所述溝槽中，以形成電性浮置的虛擬連接件。
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