SG10201408768XA - Device without zero mark layer - Google Patents

Device without zero mark layer

Info

Publication number
SG10201408768XA
SG10201408768XA SG10201408768XA SG10201408768XA SG10201408768XA SG 10201408768X A SG10201408768X A SG 10201408768XA SG 10201408768X A SG10201408768X A SG 10201408768XA SG 10201408768X A SG10201408768X A SG 10201408768XA SG 10201408768X A SG10201408768X A SG 10201408768XA
Authority
SG
Singapore
Prior art keywords
mark layer
zero mark
zero
layer
mark
Prior art date
Application number
SG10201408768XA
Inventor
Gong Shunqiang
Boon Tan Juan
Wang Shijie
Bhatkar Mahesh
Wang Daxiang
Original Assignee
Globalfoundries Sg Pte Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Globalfoundries Sg Pte Ltd filed Critical Globalfoundries Sg Pte Ltd
Priority to SG10201408768XA priority Critical patent/SG10201408768XA/en
Priority to US14/981,873 priority patent/US9773702B2/en
Publication of SG10201408768XA publication Critical patent/SG10201408768XA/en
Priority to US15/710,854 priority patent/US10553488B2/en

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76898Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics formed through a semiconductor substrate
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/544Marks applied to semiconductor devices or parts, e.g. registration marks, alignment structures, wafer maps
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2223/00Details relating to semiconductor or other solid state devices covered by the group H01L23/00
    • H01L2223/544Marks applied to semiconductor devices or parts
    • H01L2223/5442Marks applied to semiconductor devices or parts comprising non digital, non alphanumeric information, e.g. symbols
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2223/00Details relating to semiconductor or other solid state devices covered by the group H01L23/00
    • H01L2223/544Marks applied to semiconductor devices or parts
    • H01L2223/54426Marks applied to semiconductor devices or parts for alignment
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2223/00Details relating to semiconductor or other solid state devices covered by the group H01L23/00
    • H01L2223/544Marks applied to semiconductor devices or parts
    • H01L2223/54453Marks applied to semiconductor devices or parts for use prior to dicing
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/52Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/525Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body with adaptable interconnections
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001Technical content checked by a classifier
    • H01L2924/0002Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Geometry (AREA)
SG10201408768XA 2014-12-29 2014-12-29 Device without zero mark layer SG10201408768XA (en)

Priority Applications (3)

Application Number Priority Date Filing Date Title
SG10201408768XA SG10201408768XA (en) 2014-12-29 2014-12-29 Device without zero mark layer
US14/981,873 US9773702B2 (en) 2014-12-29 2015-12-28 Device without zero mark layer
US15/710,854 US10553488B2 (en) 2014-12-29 2017-09-21 Device without zero mark layer

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
SG10201408768XA SG10201408768XA (en) 2014-12-29 2014-12-29 Device without zero mark layer

Publications (1)

Publication Number Publication Date
SG10201408768XA true SG10201408768XA (en) 2016-07-28

Family

ID=56165077

Family Applications (1)

Application Number Title Priority Date Filing Date
SG10201408768XA SG10201408768XA (en) 2014-12-29 2014-12-29 Device without zero mark layer

Country Status (2)

Country Link
US (2) US9773702B2 (en)
SG (1) SG10201408768XA (en)

Families Citing this family (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP6955852B2 (en) * 2016-07-27 2021-10-27 ラピスセミコンダクタ株式会社 Semiconductor devices and manufacturing methods for semiconductor devices
KR20180041297A (en) * 2016-10-13 2018-04-24 삼성전자주식회사 Manufacturing method of interposer and manufacturing method of semiconductor package including the same
EP3563308A1 (en) * 2016-12-27 2019-11-06 Intel Corporation Superconducting qubit device packages
US10636757B2 (en) * 2017-08-29 2020-04-28 Taiwan Semiconductor Manufacturing Co., Ltd. Integrated circuit component package and method of fabricating the same
KR102450580B1 (en) 2017-12-22 2022-10-07 삼성전자주식회사 Semiconductor Device having a Structure for Insulating Layer under Metal Line
US11600590B2 (en) * 2019-03-22 2023-03-07 Advanced Semiconductor Engineering, Inc. Semiconductor device and semiconductor package
KR20210008957A (en) 2019-07-15 2021-01-26 삼성전자주식회사 Semiconductor package
US11094613B2 (en) * 2019-08-22 2021-08-17 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor structure and manufacturing method thereof
US10978405B1 (en) * 2019-10-29 2021-04-13 Taiwan Semiconductor Manufacturing Company, Ltd. Integrated fan-out package

Family Cites Families (15)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2006210368A (en) * 1999-07-02 2006-08-10 Toyota Central Res & Dev Lab Inc Vertical semiconductor device and its fabrication process
JP4467318B2 (en) 2004-01-28 2010-05-26 Necエレクトロニクス株式会社 Semiconductor device, chip alignment method for multi-chip semiconductor device, and method for manufacturing chip for multi-chip semiconductor device
US7005377B2 (en) * 2004-05-24 2006-02-28 Bcd Semiconductor Manufacturing Ltd. Bimetal layer manufacturing method
US20100089748A1 (en) * 2008-10-15 2010-04-15 C Forster John Control of erosion profile on a dielectric rf sputter target
US7838337B2 (en) 2008-12-01 2010-11-23 Stats Chippac, Ltd. Semiconductor device and method of forming an interposer package with through silicon vias
KR101616044B1 (en) * 2009-07-03 2016-04-28 삼성전자주식회사 Semiconductor device comprising landing pad formed by electroless plating
US9293366B2 (en) * 2010-04-28 2016-03-22 Taiwan Semiconductor Manufacturing Company, Ltd. Through-substrate vias with improved connections
US8492878B2 (en) * 2010-07-21 2013-07-23 International Business Machines Corporation Metal-contamination-free through-substrate via structure
US8928159B2 (en) 2010-09-02 2015-01-06 Taiwan Semiconductor Manufacturing & Company, Ltd. Alignment marks in substrate having through-substrate via (TSV)
US8492241B2 (en) * 2010-10-14 2013-07-23 International Business Machines Corporation Method for simultaneously forming a through silicon via and a deep trench structure
US8546961B2 (en) 2011-01-10 2013-10-01 International Business Machines Corporation Alignment marks to enable 3D integration
US8563403B1 (en) 2012-06-27 2013-10-22 International Business Machines Corporation Three dimensional integrated circuit integration using alignment via/dielectric bonding first and through via formation last
US20140147984A1 (en) 2012-11-27 2014-05-29 United Microelectronics Corp. Semiconductor device and method of fabricating through silicon via structure
KR102114340B1 (en) * 2013-07-25 2020-05-22 삼성전자주식회사 Integrated circuit device having through-silicon via structure and decoupling capacitor and method of manufacturing the same
CN103633067B (en) 2013-11-04 2016-04-13 中国航天科技集团公司第九研究院第七七一研究所 Based on the Roundabout alignment mark of the three-dimensional integrated technique of TSV

Also Published As

Publication number Publication date
US20180012800A1 (en) 2018-01-11
US10553488B2 (en) 2020-02-04
US9773702B2 (en) 2017-09-26
US20160190041A1 (en) 2016-06-30

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