TWI555101B - 封裝結構及其製法 - Google Patents

封裝結構及其製法 Download PDF

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Publication number
TWI555101B
TWI555101B TW103118366A TW103118366A TWI555101B TW I555101 B TWI555101 B TW I555101B TW 103118366 A TW103118366 A TW 103118366A TW 103118366 A TW103118366 A TW 103118366A TW I555101 B TWI555101 B TW I555101B
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Taiwan
Prior art keywords
bump
substrate
conductive
package structure
layer
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TW103118366A
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English (en)
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TW201545250A (zh
Inventor
蕭惟中
林俊賢
白裕呈
孫銘成
邱士超
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矽品精密工業股份有限公司
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Application filed by 矽品精密工業股份有限公司 filed Critical 矽品精密工業股份有限公司
Priority to TW103118366A priority Critical patent/TWI555101B/zh
Priority to CN201410247337.2A priority patent/CN105225975B/zh
Priority to US14/452,731 priority patent/US9490225B2/en
Publication of TW201545250A publication Critical patent/TW201545250A/zh
Application granted granted Critical
Publication of TWI555101B publication Critical patent/TWI555101B/zh

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Description

封裝結構及其製法
本發明係有關一種封裝結構及其製法，尤指一種能具有凸塊之封裝結構及其製法。
隨著電子產品係朝多功能、高電性及高速運作之方向發展，半導體封裝技術的演進已開發出不同的封裝型態，例如多晶片模組(Multi Chip Module，MCM)，多晶片模組係能整合複數晶片之半導體裝置(Semiconductor device)，藉以符合電子產品之需求。
請參閱第1A至1B圖，前述能整合複數晶片之半導體裝置的主要類型係於單一之半導體裝置中整合複數晶片者，其係如第1A圖所示，該半導體裝置在一基板10上承載複數堆疊之半導體晶片11，或於一基板10上佈設複數置於同一平面上之半導體晶片11，如第1B圖所示。然而，該種半導體裝置之缺點在於其完成封裝後始能對各半導體晶片11進行電性及信賴性等測試，若其中有任一半導體晶片11無法通過測試，將導致整個半導體裝置無法使用。
為改善前揭缺失，第6,303,997號美國專利揭露一種整 合有複數晶片之半導體裝置的類型，其係如第1C圖所示，於一基板10之上表面安置一電性連接至該基板10之半導體晶片11與另一半導體封裝件12，製作該半導體裝置時，係先將該半導體晶片11藉由銲線111電性連接至該基板10上表面並進行測試，俟確認功能正常後，再以表面藕接技術(Surface Mount Technology，SMT)將另一已完成封裝並經測試之BGA型式半導體封裝件12藉銲球121電性連接至該基板10，最後再進行整體測試，以避免前述傳統之多晶片模組所存在之已知良晶片(Known Good Die，KGD)的問題。
然而，於前揭方法中，該半導體裝置必須在該基板10上表面同時設置多數之銲線墊與銲球墊，俾供該半導體晶片11與半導體封裝件12電性連接至該基板10，不僅造成基板佈局限制，同時必須使用高密度之製程，如積層基板(Build-Up substrate)，導致生產成本之提昇。
因此，請參閱第1D圖，第5,783,870號美國專利揭露另一整合有複數晶片之半導體裝置的類型，其係將複數半導體封裝件整合為單一之模組化之半導體裝置(Module Semiconductor Device)。該模組化半導體裝置係於一第一半導體封裝件12a上疊接一第二半導體封裝件12b，並藉該第二半導體封裝件12b之複數銲球121b銲接至該第一半導體封裝件12a；同理，第三半導體封裝件12c與第二半導體封裝件12b之疊接亦然，且該第一半導體封裝件12a係藉由複數銲球121a電性連接至基板10，使該第二半導體 封裝件12b與第三半導體封裝件12c得以電性連接至該基板10，且該模組化之半導體裝置所使用之半導體封裝件12a,12b,12c得先個別予以測試，俟測試通過後再加以疊接。
然而，前述方法雖可利用一般基板解決多晶片模組所存在之已知良晶片(Known Good Die，KGD)的問題。惟，該種具複數疊接半導體封裝件之裝置中，位於下層之半導體封裝件亦具有安置半導體晶片之晶片接置區。因此，僅能在該晶片接置區以外的其餘部分之區域才可供上層半導體封裝件之銲球進行銲接以電性連接至下層半導體封裝件，亦即，使該電性連接區域(electrically-connecting area)大小受到限制，而影響到基板之電路佈局性，遂亦侷限往上層半導體封裝件之輸入/輸出連接端(I/O Connection)之數量與佈設，導致整體封裝裝置之設計靈活性(design flexibility)受到不利之影響。
因此，如何藉由簡單之製程技術與花費較少之成本，克服習知技術中之問題，實為業界迫切待解之題。
鑒於上述習知技術之缺失，本發明提供一種封裝結構，係包括：基板，係具有複數第一連接墊及相對之頂面及外露該複數第一連接墊之底面；複數導電柱，係嵌埋於該基板中，且與該第一連接墊電性連接，該導電柱之端面並係外露於該基板之頂面；複數第一凸塊，係形成於該導電柱之端面上；複數第二凸塊，係形成於該基板之頂面上，且該第二凸塊之高度係大於該第一凸塊之高度；以及至少 一第一電子元件，係設置於該基板之頂面上方，且與該第一凸塊電性連接。
為得到本發明之封裝結構，本發明復提供一種封裝結構之製法，係包括：提供一具有複數第一連接墊及相對之頂面及外露有該複數第一連接墊之底面的基板，該基板中嵌埋有複數與該第一連接墊電性連接之導電柱，且該導電柱係外露於該基板之頂面；於該基板之頂面形成導電層；於該導電層上形成複數第一凸塊及第二凸塊，該第二凸塊之高度係大於該第一凸塊之高度；移除該導電層未為該第二凸塊及第一凸塊所覆蓋之部分；以及設置並電性連接至少一第一電子元件於該第一凸塊上。
由上可知，本發明封裝結構及其製法主要係藉由在該基板上形成複數高度大於第一凸塊之第二凸塊，並藉此使設置第一電子元件後，後續堆疊之第二電子元件能使該第一電子元件收納於該第二電子元件、第二凸塊與基板所形成之容置空間，而不僅能避免電性連接區域之大小受到限制，更能有效降低封裝結構之高度。
10‧‧‧基板
11‧‧‧半導體晶片
111‧‧‧銲線
12‧‧‧半導體封裝件
12a‧‧‧第一半導體封裝件
12b‧‧‧第二半導體封裝件
12c‧‧‧第三半導體封裝件
121、121a、121b‧‧‧銲球
20、20’‧‧‧離型件
20a‧‧‧第一表面
20b‧‧‧第二表面
200‧‧‧鐵
201‧‧‧金屬材料
21‧‧‧基板
21a‧‧‧頂面
21b‧‧‧底面
210‧‧‧第一阻層
210a‧‧‧第一開口
211‧‧‧第一連接墊
212‧‧‧第二阻層
212a‧‧‧第二開口
213‧‧‧導電柱
213a‧‧‧端面
214‧‧‧絕緣體
22‧‧‧聚合物層
22a‧‧‧開口
23‧‧‧導電層
24‧‧‧第三阻層
24a‧‧‧第三開口
24b‧‧‧第四開口
25‧‧‧第一凸塊
26‧‧‧第四阻層
26a‧‧‧第五開口
27‧‧‧第二凸塊
270‧‧‧支撐部
271‧‧‧連接部
29‧‧‧表面處理層
3‧‧‧第二電子元件
3a‧‧‧容置空間
30‧‧‧第一電子元件
第1A至1D圖係為習知封裝堆疊結構之製法的剖視圖；第2A至2D圖係為本發明之基板之製法的剖視圖；以及第3A至3I圖係為本發明之封裝結構之製法的剖視圖，其中，第3G’圖係第3G圖之另一實施態樣。
以下係藉由特定的具體實例說明本發明之實施方式，熟悉此技藝之人士可由本說明書所揭示之內容輕易地瞭解本發明之其他優點與功效。本發明亦可藉由其他不同的具體實例加以施行或應用，本說明書中的各項細節亦可基於不同觀點與應用，在不悖離本發明之精神下進行各種修飾與變更。
須知，本說明書所附圖式所繪示之結構、比例、大小等，均僅用以配合說明書所揭示之內容，以供熟悉此技藝之人士之瞭解與閱讀，並非用以限定本創作可實施之限定條件，故不具技術上之實質意義，任何結構之修飾、比例關係之改變或大小之調整，在不影響本創作所能產生之功效及所能達成之目的下，均應仍落在本創作所揭示之技術內容得能涵蓋之範圍內。同時，本說明書中所引用之如「第一」、「第二」、「上」及「一」等之用語，亦僅為便於敘述之明瞭，而非用以限定本創作可實施之範圍，其相對關係之改變或調整，在無實質變更技術內容下，當亦視為本創作可實施之範疇。
請參閱第2A至2D圖係顯示本發明之基板之製法剖視圖。
如第2A圖所示，提供一具有相對之第一表面20a與第二表面20b之離型件20。
於本實施例中，係以表面形成有金屬材料201的鐵200組成的金屬複合材料做為離型件20。於本發明之製法中， 對於該金屬材料之材質並未有特殊限制，僅需為可被蝕刻之金屬即可。
如第2B至2C圖所示，於該離型件20之第一表面20a上形成複數第一連接墊211，並於該第一連接墊211上形成導電柱213。
於本實施例中，係如第2B圖所示，先於該離型件20之第一表面20a上形成具有第一開口210a之第一阻層210，再於該第一開口210a中填充導電材料，以形成該第一連接墊211，接著，於該第一阻層210上形成具有外露出部分該第一連接墊211之第二開口212a的第二阻層212。
如第2C圖所示，於該第二開口212a中填充導電材料，以形成該導電柱213。
於本實施例中，對於該導電材料之材質並未有特殊限制，包括但不限於銅。
如第2D圖所示，移除該第一阻層210及第二阻層212，以外露出該導電柱213與第一連接墊211，並於該離型件20上形成絕緣體214，使該導電柱213與第一連接墊211嵌埋於該絕緣體214中。該絕緣體214係具有相對之頂面21a及底面21b，且該底面21b係連接該離型件20。
於本實施例中，於形成包覆該導電柱213與第一連接墊211之該絕緣體214後，研磨該絕緣體214之頂面21a，以使該頂面21a外露出該導電柱213之端面213a，而得到外露有導電柱213的端面213a之基板21。
請參閱第3A至3I圖，係顯示本發明之封裝結構之製 法剖視圖，其中，第3G’圖係第3G圖之另一實施態樣。
如第3A圖所示，係延續自第2D圖。先提供一具有相對之頂面21a及外露有該等第一連接墊211之底面21b的該基板21，並於該基板21之頂面21a上形成具有複數外露出該導電柱213的端面213a之開口22a的聚合物層22。
於本實施例中，該基板21之底面21b係連接至該離型件20。於本實施例中，該聚合物層22之材料並未有特殊限制，該聚合物層22可為環氧樹脂等電性隔絕之薄型(low profile)聚合膠材。
如第3B圖所示，於該聚合物層22上形成導電層23。
於本實施例中該導電層23之材料為沉積銅，本發明可藉由該聚合物層22達到提升導電層23與該基板21間之接著能力之功效。
接著，依據第3C至3F圖所示之步驟，於該導電層23上形成複數第一凸塊25及第二凸塊27。
如第3C圖所示，於該導電層23上形成第三阻層24，該第三阻層24係具有複數外露出該導電層23對應於該導電柱213之端面213a之部分的第三開口24a以及複數外露出部分未對應於該導電柱213之端面213a之該導電層23的第四開口24b。
於本實施例中該第三開口24a的寬度係小於該第四開口24b之寬度。
如第3D圖所示，於該第三開口24a與第四開口24b中填充導電材料，以構成與該導電柱213電性連接的第一 凸塊25及支撐部270。
於本實施例中，該第一凸塊25之高度係等於該支撐部270之高度，且該第一凸塊25之寬度係小於該支撐部270之寬度。
如第3E圖所示，於該第三阻層24上形成第四阻層26，且該第四阻層26形成有外露出該支撐部270之第五開口26a；於該第五開口26a中填充導電材料，以於該支撐部270上形成連接部271，俾由該支撐部270與連接部271構成第二凸塊27。
於本實施例中，該支撐部270的寬度係大於或等於該連接部271的寬度。
如第3F圖所示，移除該第三阻層24與第四阻層26，以外露出該第一凸塊25及第二凸塊27。
於本實施例中，該第二凸塊27之高度係大於該第一凸塊25，且該第一凸塊25之寬度係小於該第二凸塊27之寬度。
如第3G圖所示，移除該導電層23未為該第一凸塊25及第二凸塊27所覆蓋之部分，以外露出部分該聚合物層22。
於本實施例中，由於該基板21係形成於離型件20上，因此，於移除該離型件20後，即外露出該第一連接墊211及該基板21之底面21b。
另外，於本實施例之另一實施方式中，係於該第一凸塊25、第二凸塊27及第一連接墊211上形成表面處理層 29，例如有機保銲層(OSP)。於前述實施例中，於移除該離型件20時，可僅移除部份該離型件20，以外露出該第一連接墊211，並保留部分該離型件20’以防止所欲形成之該表面處理層29發生溢流並提供剛性支撐，如第3G’圖所示。
如第3H圖所示，係接續第3G圖之步驟，設置並電性連接至少一第一電子元件30於該第一凸塊25上。
於本實施例中，各該第二凸塊27之高度係大於各該第一凸塊25與第一電子元件30的高度之總和。於本實施例，該第一電子元件30係為半導體晶片、經封裝或未經封裝之半導體元件，較佳者係為經測試為良晶片之半導體晶片。
如第3I圖所示，設置並電性連接至少一第二電子元件3至該第二凸塊27，使該第二凸塊27與該第二電子元件3間形成一容置空間3a以供收納該第一電子元件30，即該第一電子元件30係位於該基板21與該第二電子元件3之間。
於本實施例中，該第二電子元件3係為基板、半導體晶片、中介板、經封裝或未經封裝之半導體元件。
請參閱第3H圖，本發明之封裝結構係具有：基板21，係具有複數第一連接墊211及相對之頂面21a及外露有該複數第一連接墊211之底面21b；複數導電柱213，係嵌埋於該基板21中，且與該第一連接墊電性連接211，該導電柱213之端面213a係外露於該基板21之頂面21a；複數第一凸塊25，係形成於該導電柱213之端面213a；複數第二 凸塊27，係形成於該基板21之頂面21a，該第二凸塊27之高度係大於該第一凸塊25之高度；以及至少一第一電子元件30，係設置於該基板21之頂面21a上方，且與該第一凸塊25電性連接。
於本實施例中，本發明之封裝結構復包括聚合物層22與導電層23，該聚合物層22係形成於該基板21之頂面21a，並外露出該導電柱213之端面213a，該導電層23係形成於該導電柱213之端面213a與第一凸塊25間以及該聚合物層22與第二凸塊27間。
於本實施例中，該第二凸塊27係包括形成於該基板21之頂面21a的支撐部270與形成於該支撐部270上的連接部271，該第二凸塊27之高度係大於該第一凸塊25與第一電子元件30的高度之總和。
於本發明之封裝結構及其製法中，該基板21之頂面21a復可形成有線路層(未圖示)，其係將該第一凸塊25與該第二凸塊27電性連接至該導電柱213。
綜上所述，本發明之封裝結構及其製法係藉由第二凸塊之高度大於第一凸塊之高度，使得於該封裝結構之第二凸塊上接置第二電子元件(如，外部元件)時，第一電子元件能收納於基板與該第二電子元件之間，藉以在現有封裝技術下，不需改變或增加機台即能避免電性連接區域之大小受到限制，進而能提升電路佈局性。
上述實施例僅例示性說明本發明之原理及其功效，而非用於限制本發明。任何熟習此項技藝之人士均可在不違 背本發明之精神及範疇下，對上述實施例進行修飾與改變。因此，本發明之權利保護範圍，應如後述之申請專利範圍所列。
21‧‧‧基板
21a‧‧‧頂面
21b‧‧‧底面
211‧‧‧第一連接墊
213‧‧‧導電柱
213a‧‧‧端面
214‧‧‧絕緣體
22‧‧‧聚合物層
23‧‧‧導電層
25‧‧‧第一凸塊
27‧‧‧第二凸塊
270‧‧‧支撐部
271‧‧‧連接部
30‧‧‧第一電子元件

Claims (19)

  1. 一種封裝結構之製法，係包括：提供一具有複數第一連接墊及相對之頂面及外露有該複數第一連接墊之底面的基板，該基板中嵌埋有複數與該第一連接墊電性連接之導電柱，且該導電柱係外露於該基板之頂面；於該基板之頂面形成導電層；於該導電層上形成複數第一凸塊及第二凸塊，該第二凸塊之高度係大於該第一凸塊之高度；移除該導電層未為該第二凸塊及第一凸塊所覆蓋之部分；以及設置並電性連接至少一第一電子元件於該第一凸塊上。
  2. 如申請專利範圍第1項所述之封裝結構之製法，其中，提供該基板之步驟係包括：提供一具有相對之第一表面與第二表面之離型件；於該離型件之第一表面上形成該等第一連接墊；於該第一連接墊上形成該導電柱；於該離型件之第一表面上形成絕緣體，俾使該等第一連接墊及導電柱嵌埋於該絕緣體中，而得到具有相對之外露出該導電柱之端面的頂面與底面之該基板，該基板係以該底面與該離型件之第一表面接觸；以及 移除該離型件以使該第一連接墊外露於該基板之底面。
  3. 如申請專利範圍第2項所述之封裝結構之製法，其中，形成該等第一連接墊與導電柱之步驟係包括：於該離型件之第一表面上形成具有第一開口之第一阻層；於該第一開口中形成該等第一連接墊；於該第一阻層與該等第一連接墊上形成具有外露出部分該第一連接墊之第二開口的第二阻層；於該第二開口中形成該等導電柱；以及移除該第一阻層及第二阻層。
  4. 如申請專利範圍第2項所述之封裝結構之製法，於形成該絕緣體之後，復包括研磨該絕緣體，以使該導電柱之端面外露出該頂面。
  5. 如申請專利範圍第1項所述之封裝結構之製法，於形成該導電層之前，復包括於該基板之頂面上形成外露出該導電柱之端面的聚合物層，以供該導電層形成於該聚合物層及該外露出該聚合物層之導電柱之端面上。
  6. 如申請專利範圍第5項所述之封裝結構之製法，其中，形成該等第一凸塊及第二凸塊之步驟係包括：於該導電層上形成具有複數第三開口與複數第四開口之第三阻層，以供部分對應於該導電柱之端面之該導電層外露於該第三開口，及供部分未對應於該導 電柱之端面之該導電層外露於該第四開口；於該第三開口與第四開口中分別形成與該導電柱電性連接的該第一凸塊及支撐部；於該第三阻層上形成具有複數外露出該支撐部之第五開口之第四阻層；於該第五開口中的該支撐部上形成連接部，俾供該支撐部與連接部構成該第二凸塊；以及移除該第三阻層與第四阻層。
  7. 如申請專利範圍第1項所述之封裝結構之製法，復包括於設置該第一電子元件前，於該第一凸塊、第二凸塊及第一連接墊上形成表面處理層。
  8. 如申請專利範圍第1項所述之封裝結構之製法，復包括設置並電性連接至少一第二電子元件至該第二凸塊，而令該第一電子元件係位於該基板與該第二電子元件之間。
  9. 如申請專利範圍第1項所述之封裝結構之製法，其中，該基板之頂面復形成有線路層，以由該線路層將該第一凸塊與該第二凸塊電性連接至該導電柱。
  10. 一種封裝結構，係包括：基板，係具有複數第一連接墊及相對之頂面及外露該複數第一連接墊之底面；複數導電柱，係嵌埋於該基板中，且與該第一連接墊電性連接，該導電柱之端面並係外露於該基板之頂面； 複數第一凸塊，係形成於該導電柱之端面上；複數第二凸塊，係形成於該基板之頂面上，且該第二凸塊之高度係大於該第一凸塊之高度，其中，該第二凸塊係包括形成於該基板之頂面的支撐部與形成於該支撐部上的連接部；以及至少一第一電子元件，係設置於該基板之頂面上方，且與該第一凸塊電性連接。
  11. 如申請專利範圍第10項所述之封裝結構，其中，各該第二凸塊之高度係大於各該第一凸塊與該第一電子元件的高度之總和。
  12. 如申請專利範圍第10項所述之封裝結構，復包括聚合物層，係形成於該基板之頂面，並外露出該導電柱之端面，以使該第二凸塊形成於該聚合物層上。
  13. 如申請專利範圍第10項所述之封裝結構，復包括導電層，係形成於該導電柱之端面與第一凸塊間及該基板之頂面與第二凸塊間。
  14. 如申請專利範圍第10項所述之封裝結構，其中，該支撐部的寬度係大於或等於該連接部的寬度。
  15. 如申請專利範圍第10項所述之封裝結構，其中，該第一電子元件為半導體晶片、經封裝或未經封裝之半導體元件。
  16. 如申請專利範圍第10項所述之封裝結構，復包括至少一第二電子元件，係接合至並電性連接於該第二凸塊，而令該第一電子元件位於該基板與該第二電子元 件之間。
  17. 如申請專利範圍第16項所述之封裝結構，其中，該第二電子元件為基板、半導體晶片、中介板、經封裝或未經封裝之半導體元件。
  18. 如申請專利範圍第10項所述之封裝結構，復包括表面處理層，係形成於該第一凸塊、第二凸塊及第一連接墊上。
  19. 如申請專利範圍第10項所述之封裝結構，復包括線路層，係形成於該基板之頂面，以將該第一凸塊與該第二凸塊電性連接至該導電柱。
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