TWI654675B - 半導體裝置結構的形成方法 - Google Patents

半導體裝置結構的形成方法

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Publication number
TWI654675B
TWI654675B TW106135678A TW106135678A TWI654675B TW I654675 B TWI654675 B TW I654675B TW 106135678 A TW106135678 A TW 106135678A TW 106135678 A TW106135678 A TW 106135678A TW I654675 B TWI654675 B TW I654675B
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TW
Taiwan
Prior art keywords
conductive
conductive bumps
semiconductor structure
dummy
top surface
Prior art date
Application number
TW106135678A
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English (en)
Other versions
TW201839826A (zh
Inventor
施孟甫
黃震麟
李建成
朱則榮
陳文明
劉國洲
Original Assignee
台灣積體電路製造股份有限公司
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Publication of TW201839826A publication Critical patent/TW201839826A/zh
Application granted granted Critical
Publication of TWI654675B publication Critical patent/TWI654675B/zh

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    • H01L21/76879—Filling of holes, grooves or trenches, e.g. vias, with conductive material by selective deposition of conductive material in the vias, e.g. selective C.V.D. on semiconductor material, plating
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Abstract

提供半導體裝置結構的形成方法，此方法包含提供半導體結構，半導體結構具有中央部分和圍繞中央部分的周邊部分。此方法包含在半導體結構的表面上方形成複數個第一導電凸塊和複數個虛設導電凸塊，第一導電凸塊在中央部分上方並電性連接至半導體結構，虛設導電凸塊在周邊部分上方並與半導體結構電性絕緣，第一導電凸塊的每一個具有第一厚度和第一寬度，虛設導電凸塊的每一個具有第二厚度和第二寬度，第二厚度小於第一厚度，且第二寬度大於第一寬度。

Description

半導體裝置結構的形成方法
本發明實施例係有關於半導體技術，且特別是有關於半導體裝置結構的形成方法。
半導體積體電路(integrated circuit，IC)工業已經歷了快速成長。在積體電路材料和設計上的技術進步產生了數代積體電路，每一代都比前一代具有更小且更複雜的電路。然而，這些進步增加了加工與製造積體電路的複雜性。
在積體電路的發展史中，功能密度(即每一晶片區互連的裝置數目)增加，同時幾何尺寸(即製造過程中所產生的最小的組件(或線路))縮小。此元件尺寸微縮化的製程一般來說具有增加生產效率與降低相關費用的益處。
然而，由於部件(feature)尺寸持續縮減，製造製程持續變的更加難以實施。因此，形成越來越小的尺寸的可靠的半導體裝置是個挑戰。
在一些實施例中，提供一種半導體裝置結構的形成方法，此方法包含提供半導體結構，其中半導體結構具有中央部分和圍繞中央部分的周邊部分；以及在半導體結構的表面 上方形成複數個第一導電凸塊和複數個虛設導電凸塊，其中第一導電凸塊在中央部分上方並電性連接至半導體結構，虛設導電凸塊在周邊部分上方並與半導體結構電性絕緣，第一導電凸塊的每一個具有第一厚度和第一寬度，虛設導電凸塊的每一個具有第二厚度和第二寬度，第二厚度小於第一厚度，且第二寬度大於第一寬度。
在一些其他實施例中，提供一種半導體裝置結構的形成方法，此方法包含提供半導體結構，其中半導體結構具有中央部分和圍繞中央部分的周邊部分；以及在半導體結構的表面上形成複數個第一導電凸塊和複數個虛設導電凸塊，其中第一導電凸塊在中央部分上方並電性連接至半導體結構，虛設導電凸塊在周邊部分上方並與半導體結構電性絕緣，第一導電凸塊的每一個具有第一厚度，虛設導電凸塊的每一個具有第二厚度，第二厚度小於第一厚度，且虛設導電凸塊與半導體結構之間的接觸面積大於第一導電凸塊與半導體結構之間的接觸面積。
在另外一些實施例中，提供一種半導體裝置結構的形成方法，此方法包含提供半導體結構，其中半導體結構具有中央部分和圍繞中央部分的周邊部分；以及在半導體結構的表面上方形成複數個第一導電凸塊和複數個虛設導電凸塊，其中第一導電凸塊在中央部分上方並電性連接至半導體結構，虛設導電凸塊在周邊部分上方並與半導體結構電性絕緣，第一導電凸塊的每一個具有第一厚度，虛設導電凸塊的每一個具有第二厚度，第二厚度小於第一厚度，且虛設導電凸塊的寬度大於 第一導電凸塊的相鄰兩者之間的距離。
110‧‧‧半導體結構
110C‧‧‧中央部分
110P‧‧‧周邊部分
110a‧‧‧中央晶片
110b‧‧‧周邊晶片
111、142‧‧‧半導體基底
111a、111b‧‧‧表面
112、114c‧‧‧導通孔
113‧‧‧絕緣層
114‧‧‧重佈線結構
114a、146、220‧‧‧介電層
114b‧‧‧線路層
116‧‧‧第一導電墊
118‧‧‧第二導電墊
119‧‧‧介電層
119a、124a、124b、146a‧‧‧開口
122、152‧‧‧凸塊下金屬層
124‧‧‧遮罩層
126、128、154‧‧‧導電層
130、160、170‧‧‧銲料層
140‧‧‧晶片
144、210‧‧‧導電墊
150、230、B‧‧‧導電凸塊
150a、S1、S2‧‧‧頂表面
180‧‧‧底部填充層
190‧‧‧模塑層
300‧‧‧晶片封裝體
DB‧‧‧虛設導電凸塊
Rc‧‧‧中央晶片區域
Rp‧‧‧周邊晶片區域
SC‧‧‧切割道
D1、D2、D3、D4‧‧‧距離
G1、G2‧‧‧間隙
H1、H2‧‧‧高度
S3、S4‧‧‧底表面
SW‧‧‧彎曲側壁
T1、T2‧‧‧厚度
W1、W2、W3、W4‧‧‧寬度
根據以下的詳細說明並配合所附圖式可以更加理解本發明實施例。應注意的是，根據本產業的標準慣例，圖示中的各種部件並未必按照比例繪製。事實上，可能任意的放大或縮小各種部件的尺寸，以做清楚的說明。
第1A-1I圖為依據一些實施例之形成半導體裝置結構的製程的各種階段的剖面示意圖。
第1A-1圖到第1D-1圖為依據一些實施例之第1A-1D圖的半導體裝置結構的上視圖。
第1A-2圖為依據一些實施例，沿第1A-1圖的線II-II’，半導體裝置結構的剖面示意圖。
第1I-1圖為依據一些實施例之第1I圖的半導體裝置結構的上視圖。
第2圖為依據一些實施例之半導體裝置結構的上視圖。
第3圖為依據一些實施例之半導體裝置結構的上視圖。
要瞭解的是以下的揭露內容提供許多不同的實施例或範例，以實施提供之主體的不同部件。以下敘述各個構件及其排列方式的特定範例，以求簡化揭露內容的說明。當然，這些僅為範例並非用以限定本發明實施例。例如，以下的揭露內容敘述了將一第一部件形成於一第二部件之上或上方，即表示其包含了所形成的上述第一部件與上述第二部件是直接接觸的實施例，亦包含了尚可將附加的部件形成於上述第一部件 與上述第二部件之間，而使上述第一部件與上述第二部件可能未直接接觸的實施例。此外，揭露內容中不同範例可能使用重複的參考符號及/或用字。這些重複符號或用字係為了簡化與清晰的目的，並非用以限定各個實施例及/或所述外觀結構之間的關係。
再者，為了方便描述圖式中一元件或部件與另一(複數)元件或(複數)部件的關係，可使用空間相關用語，例如“在...之下”、“下方”、“下部”、“上方”、“上部”及類似的用語。除了圖式所繪示的方位之外，空間相關用語也涵蓋裝置在使用或操作中的不同方位。所述裝置也可被另外定位(例如，旋轉90度或者位於其他方位)，並對應地解讀所使用的空間相關用語的描述。應當理解的是，可提供額外的操作於本發明實施例的方法之前、本發明實施例的方法中和本發明實施例的方法之後，且在本發明實施例的方法的其他實施例中，可取代或消除所述的一些操作。
也可包含其他部件和製程，舉例來說，可包含測試結構來幫助三維(3D)封裝或三維積體電路(3DIC)裝置的驗證測試。舉例來說，測試結構可包含形成於重佈線層中或基底上的測試墊，以允許三維封裝或三維積體電路的測試、探針及/或探針卡和類似物的使用。可實施驗證測試於中間結構和最終結構。此外，此處揭露的結構和方法可與包含良好晶粒的中間驗證(intermediate verification)的測試方法結合使用，以增加產率並降低成本。
第1A-1I圖為依據一些實施例之形成半導體裝置結 構的製程的各種階段的剖面示意圖。第1A-1圖到第1D-1圖為依據一些實施例之第1A-1D圖的半導體裝置結構的上視圖。第1A-1D圖為依據一些實施例，沿第1A-1到1D-1圖的線I-I’，半導體裝置結構的剖面示意圖。第1A-2圖為依據一些實施例，沿第1A-1圖的線II-II’，半導體裝置結構的剖面示意圖。
依據一些實施例，如第1A圖、第1A-1圖和第1A-2圖所示，提供半導體結構110。在一些實施例中，半導體結構110為晶圓。依據一些實施例，半導體結構110包含半導體基底111、導通孔112、重佈線結構114、第一導電墊116、第二導電墊118和介電層119。
依據一些實施例，半導體基底111具有表面(有時也被稱為頂表面)111a和111b。在一些實施例中，半導體基底111由包含單晶、多晶或非晶結構中之矽或鍺的元素半導體材料製成。
在一些其他實施例中，半導體基底111由化合物半導體(例如碳化矽、砷化鎵、磷化鎵、磷化銦或砷化銦)、合金半導體(例如SiGe或GaAsP)或前述之組合製成。半導體基底111也可包含多層半導體、絕緣層上覆半導體(semiconductor on insulator，SOI)(例如絕緣層上覆矽或絕緣層上覆鍺)或前述之組合。
在一些實施例中，半導體結構110為中介層晶圓。依據一些實施例，導通孔112形成於半導體結構110中。導通孔112可形成為從表面111a延伸至半導體基底111中。
依據一些實施例，絕緣層113形成於導通孔112與 半導體基底111之間。依據一些實施例，絕緣層113被配置使導通孔112與半導體基底111電性絕緣。
在一些其他實施例中，半導體結構110為包含主動裝置或電路的裝置晶圓。主動裝置可包含形成於表面111a上的電晶體(未顯示)。依據一些實施例，半導體結構110也可包含形成於半導體基底111中或半導體基底111上方的被動裝置(未顯示)。被動裝置包含電阻、電容或其他合適的被動裝置。
依據一些實施例，重佈線結構114形成於半導體基底111上方。依據一些實施例，第一導電墊116和第二導電墊118形成於重佈線結構114上方。
依據一些實施例，重佈線結構114包含介電層114a、線路層114b和導通孔114c。依據一些實施例，介電層114a形成於表面111a上方。依據一些實施例，線路層114b形成於介電層114a中。
依據一些實施例，如第1A圖和第1A-2圖所示，導通孔114c在不同的線路層114b之間和線路層114b、第一導電墊116與第二導電墊118之間電性連接。為了簡潔起見，依據一些實施例，第1A圖和第1A-2圖僅顯示其中一種線路層114b。依據一些實施例，導通孔112透過線路層114b和導通孔114c分別電性連接至第一導電墊116和第二導電墊118。
依據一些實施例，介電層119形成於介電層114a上方。依據一些實施例，介電層119覆蓋整個第二導電墊118。依據一些實施例，介電層119具有多個開口119a各自暴露出第一導電墊116。
依據一些實施例，半導體結構110具有中央部分110C和圍繞中央部分110C的周邊部分110P。依據一些實施例，第一導電墊116形成於中央部分110C的半導體基底111上方。依據一些實施例，第二導電墊118形成於周邊部分110P的半導體基底111上方。
依據一些實施例，如第1A圖和第1A-1圖所示，半導體結構110具有晶片區域R。在一些實施例中，預定的切割道SC在晶片區域R之間。依據一些實施例，晶片區域R包含中央晶片區域Rc和周邊晶片區域Rp。依據一些實施例，第一導電墊116形成於中央晶片區域Rc中。依據一些實施例，第二導電墊118形成於周邊晶片區域Rp中。
依據一些實施例，如第1B圖和第1B-1圖所示，凸塊下金屬(under bump metallurgy，UBM)層122形成於介電層119和第一導電墊116上。依據一些實施例，凸塊下金屬層122直接接觸介電層119和第一導電墊116。依據一些實施例，凸塊下金屬層122包含擴散阻障層(未顯示)和晶種層(未顯示)。
依據一些實施例，晶種層形成於擴散阻障層上方。擴散阻障層可為鈦層、氮化鈦層、鉭層或氮化鉭層。晶種層的材料可包含銅或銅合金。晶種層的材料可包含其他金屬，例如銀、金、鋁和前述之組合。在一些其他實施例中，不形成擴散阻障層。
依據一些實施例，如第1B圖和第1B-1圖所示，遮罩層124形成於凸塊下金屬層122上方。依據一些實施例，遮罩層124具有開口124a和124b。依據一些實施例，開口124a在中 央晶片區域Rc中。依據一些實施例，開口124a暴露出第一導電墊116上方的凸塊下金屬層122。
依據一些實施例，開口124b在周邊晶片區域Rp中。依據一些實施例，開口124b暴露出周邊晶片區域Rp中的凸塊下金屬層122。依據一些實施例，開口124a具有寬度W1。依據一些實施例，開口124b具有寬度W2。在一些實施例中，寬度W1等於全部開口124a的平均寬度。在一些實施例中，寬度W2等於全部開口124b的平均寬度。
依據一些實施例，寬度W2大於寬度W1。在一些實施例中，寬度W2與寬度W1的比率在約2至約10的範圍內。依據一些實施例，寬度W2與寬度W1的比率在約4至約6的範圍內。依據一些實施例，寬度W1在約20μm至約45μm的範圍內。依據一些實施例，寬度W2在約100μm至約250μm的範圍內。在一些實施例中，開口124b的開口面積大於開口124a的開口面積。依據一些實施例，遮罩層124包含聚合物材料，例如光阻材料。
開口124a在其中一個中央晶片區域Rc具有第一總開口面積，且此中央晶片區域Rc具有第一面積。依據一些實施例，遮罩層124在一個中央晶片區域Rc中的第一開口比率等於第一總開口面積與第一面積的比率。
開口124b在其中一個周邊晶片區域Rp具有第二總開口面積，且此周邊晶片區域Rp具有第二面積。依據一些實施例，遮罩層124在一個周邊晶片區域Rp中的第二開口比率等於第二總開口面積與第二面積的比率。
依據一些實施例，第一開口比率接近或等於第二 開口比率，以改善後續電鍍製程期間電力線分布的均勻性。在一些實施例中，第一開口比率與第二開口比率之間的差異在約-0.1至約0.1的範圍內。
依據一些實施例，如第1C圖和第1C-1圖所示，導電層126形成於開口124a中，導電層128形成於開口124b中。依據一些實施例，導電層126比導電層128厚。導電層126和128包含銅或其他合適的導電材料。
依據一些實施例，導電層126和128由相同的材料製成。依據一些實施例，導電層126和128的形成包含實施電鍍製程或其他合適的製程。依據一些實施例，導電層126和128在相同的製程(例如相同的電鍍製程)中形成。依據一些實施例，導電層126和128同時形成。
依據一些實施例，如第1D圖和第1D-1圖所示，移除遮罩層124和遮罩層124下的凸塊下金屬層122。依據一些實施例，在移除製程之後，導電層126和其下的凸塊下金屬層122共同形成導電凸塊B。
依據一些實施例，導電凸塊B形成於第一導電墊116的頂表面116a上方。依據一些實施例，導電凸塊B電性連接至第一導電墊116。依據一些實施例，導電凸塊B直接接觸第一導電墊116。
依據一些實施例，導電層128和其下的凸塊下金屬層122共同形成虛設(dummy)導電凸塊DB。依據一些實施例，虛設導電凸塊DB圍繞導電凸塊B。依據一些實施例，整個虛設導電凸塊DB形成於介電層119的頂表面119b上。
依據一些實施例，虛設導電凸塊DB直接接觸介電層119。依據一些實施例，虛設導電凸塊DB透過介電層119與其下的第二導電墊118電性絕緣。
依據一些實施例，每一導電凸塊B具有厚度T1和寬度W3。依據一些實施例，每一虛設導電凸塊DB具有厚度T2和寬度W4。依據一些實施例，寬度W4大於寬度W3。在一些實施例中，寬度W4與寬度W3的比率在約2至約10的範圍內。依據一些實施例，寬度W4與寬度W3的比率在約4至約6的範圍內。
依據一些實施例，寬度W3在約20μm至約45μm的範圍內。依據一些實施例，寬度W4在約100μm至約250μm的範圍內。
依據一些實施例，厚度T2小於厚度T1。在一些實施例中，厚度T1與厚度T2的比率在約5至約15的範圍內。依據一些實施例，厚度T1在約25μm至約40μm的範圍內。依據一些實施例，厚度T2在約2μm至約20μm的範圍內。依據一些實施例，厚度T2在約2μm至約5μm的範圍內。
在一些實施例中，厚度T1和T2分別為導電凸塊B和虛設導電凸塊DB的最大厚度。在一些實施例中，寬度W3和W4分別為導電凸塊B和虛設導電凸塊DB的最大寬度。
在一些實施例中，導電凸塊B的頂表面S1相對於第一導電墊116的頂表面116a具有高度H1。依據一些實施例，高度H1等於頂表面S1與頂表面116a之間的距離。
在一些實施例中，虛設導電凸塊DB的頂表面S2相對於介電層119的頂表面119b具有高度H2。依據一些實施例， 高度H2等於頂表面S2與頂表面119b之間的距離。依據一些實施例，高度H2小於高度H1。也就是說，依據一些實施例，頂表面S1和S2並非共平面。再者，依據一些實施例，導電凸塊B的底表面S3和虛設導電凸塊DB的底表面S4並非共平面。
依據一些實施例，高度H1在約25μm至約40μm的範圍內。依據一些實施例，高度H2在約2μm至約20μm的範圍內。依據一些實施例，高度H2在約2μm至約5μm的範圍內。
在一些實施例中，虛設導電凸塊DB與半導體結構110之間的接觸面積大於導電凸塊B與半導體結構110之間的接觸面積。虛設導電凸塊DB與半導體結構110之間大的接觸面積可改善虛設導電凸塊DB與半導體結構110之間的黏著力。
因此，依據一些實施例，在後續製程期間，可防止有著大的接觸面積和較小高度H2的虛設導電凸塊DB從介電層119脫落。因此，依據一些實施例，改善了產率。
依據一些實施例，導電凸塊B形成於中央部分110C上方並電性連接至半導體結構110。依據一些實施例，虛設導電凸塊DB在周邊部分110P上方並與半導體結構110電性絕緣。
依據一些實施例，導電凸塊B在中央晶片區域Rc中。依據一些實施例，虛設導電凸塊DB在周邊晶片區域Rp中。在一些實施例中，在一個周邊晶片區域Rp中之虛設導電凸塊DB的數量少於在一個中央晶片區域Rc中之導電凸塊B的數量。
在一些實施例中，如第1D-1圖所示，在一個周邊晶片區域Rp中之兩相鄰虛設導電凸塊DB之間的最小距離D2大於在一個中央晶片區域Rc中之兩相鄰導電凸塊B之間的最小距 離D1。
依據一些實施例，最小距離D1大於25μm。依據一些實施例，最小距離D1在約25μm至約200μm的範圍內。依據一些實施例，最小距離D2大於100μm。依據一些實施例，最小距離D2在約100μm至約300μm的範圍內。在一些實施例中，虛設導電凸塊DB的寬度W4大於兩相鄰導電凸塊B之間的距離D1。
在一些實施例中，虛設導電凸塊DB的頂表面面積大於導電凸塊B的頂表面面積。在一些實施例中，在一個中央晶片區域Rc中之導電凸塊B的總頂表面面積大於在一個周邊晶片區域Rp中之虛設導電凸塊DB的總頂表面面積。
依據一些實施例，如第1D圖和第1D-1圖所示，銲料層130形成於導電凸塊B的頂表面S1和虛設導電凸塊DB的頂表面S2上方。依據一些實施例，銲料層130直接接觸導電凸塊B和虛設導電凸塊DB。
銲料層130可為由例如SnAg形成的無鉛預銲料(pre-solder)層，或包括錫、鉛、銅、鎳、鉍或前述之組合的銲料層。在一些實施例中，助銲(flux)層(未顯示)形成於銲料層130和導電凸塊B上方以降低銲料層130的熔點。
在一些實施例中，虛設導電凸塊DB與預定切割道SC之間的最小距離D3大於導電凸塊B與預定切割道SC之間的最小距離D4。依據一些實施例，最小距離D3在約100μm至約200μm的範圍內。依據一些實施例，最小距離D4在約70μm至約150μm的範圍內。
虛設導電凸塊DB為圓形、環形(如第2圖所示)、長 條形(如第3圖所示)或其他合適的形狀。為了簡潔起見，第2-3圖不顯示銲料層130。依據一些實施例，如第2圖所示，僅一個虛設導電凸塊DB形成於一個周邊晶片區域Rp中。
依據一些實施例，如第1E圖所示，提供晶片140。為了簡潔起見，依據一些實施例，第1E圖僅顯示其中一個晶片140。依據一些實施例，晶片140包含半導體基底142、導電墊144和介電層146。
依據一些實施例，導電墊144形成於半導體基底142上方。依據一些實施例，介電層146形成於半導體基底142上方。依據一些實施例，介電層146具有開口146a暴露出其下的導電墊144。
依據一些實施例，如第1E圖所示，導電凸塊150形成於導電墊144上。依據一些實施例，導電凸塊150包含凸塊下金屬層152和導電層154。依據一些實施例，導電層154形成於凸塊下金屬層152上方。
依據一些實施例，凸塊下金屬層152可包含擴散阻障層(未顯示)和晶種層(未顯示)。擴散阻障層可為鈦層、氮化鈦層、鉭層或氮化鉭層。
晶種層的材料可包含銅或銅合金。晶種層的材料可包含其他金屬，例如銀、金、鋁和前述之組合。在一些其他實施例中，不形成擴散阻障層。導電層154包含銅或其他合適的導電材料。
依據一些實施例，如第1E圖所示，銲料層160形成於導電凸塊150的頂表面150a上方。銲料層160可為由例如SnAg 形成的無鉛預銲料層，或包括錫、鉛、銅、鎳、鉍或前述之組合的銲料層。在一些實施例中，助銲(flux)層(未顯示)形成於銲料層160和導電凸塊150上方以降低銲料層160的熔點。
依據一些實施例，如第1F圖所示，將晶片140翻轉，以透過晶片140與半導體結構110之間的導電凸塊150和B接合至半導體結構110。依據一些實施例，接合製程包含將銲料層160接合至銲料層130，並將銲料層130和160回銲(reflow)，以形成銲料層170於導電凸塊150與導電凸塊B之間。
依據一些實施例，在回銲製程之後，實施清潔製程(或清洗製程)於晶片140和半導體結構110上方，以移除助銲層。由於虛設導電凸塊DB具有(在虛設導電凸塊DB與半導體結構110之間)大的接觸面積和較低高度H2，因此在清潔製程之後可保留虛設導電凸塊DB。因此，依據一些實施例，改善了清潔製程的產率。
再者，依據一些實施例，由於虛設導電凸塊DB的寬度W4大於兩相鄰導電凸塊B之間的距離D1，因此即使虛設導電凸塊DB從介電層119脫落，虛設導電凸塊DB不會落入導電凸塊B之間的間隙G1。
依據一些實施例，如第1G圖所示，底部填充層180形成於半導體結構110與每一晶片140之間的間隙G2中。依據一些實施例，底部填充層180包含聚合物材料。
依據一些實施例，如第1G圖所示，模塑層190形成於半導體結構110上方以圍繞晶片140以及導電凸塊B和150。依據一些實施例，模塑層190包含聚合物材料。
依據一些實施例，如第1H圖所示，移除半導體基底111的下部。依據一些實施例，此移除製程包含化學機械研磨製程。
依據一些實施例，在移除製程之後，暴露出導通孔112和絕緣層113。依據一些實施例，導通孔112和絕緣層113穿透半導體基底111。依據一些實施例，當半導體基底111為矽基底時，導通孔112也可被稱為基底通孔電極或矽通孔電極。
依據一些實施例，如第1H圖所示，導電墊210形成於導通孔112上方。依據一些實施例，如第1H圖所示，介電層220形成於半導體基底111的表面111b上方。依據一些實施例，如第1H圖所示，導電凸塊230形成於導電墊210上方。導電凸塊230包含錫、銅或其他合適的導電材料。
依據一些實施例，第1I-1圖為依據一些實施例之第1I圖的半導體裝置結構的上視圖。依據一些實施例，如第1I圖和第1I-1圖所示，實施切割製程以沿預定地切割道SC切割穿透介電層220、半導體結構110和模塑層190，以形成晶片封裝體300。
依據一些實施例，在切割製程之後，將半導體結構110切割為個別的中央晶片110a和周邊晶片110b。依據一些實施例，每一晶片封裝體300包含一個中央晶片110a、一個晶片140、中央晶片110a與晶片140之間的導電凸塊150和B以及銲料層170。
依據一些實施例，在晶片封裝體300中，中央晶片110a的表面111a上方的導電凸塊B具有第一總頂表面面積。依 據一些實施例，中央晶片110a具有第一頂表面面積。依據一些實施例，周邊晶片110b的表面111b上方的虛設導電凸塊DB具有第二總頂表面面積。依據一些實施例，周邊晶片110b具有第二頂表面面積。
在一些實施例中，第一總頂表面面積與第一頂表面面積的第一比率接近或等於第二總頂表面面積與第二頂表面面積的第二比率。在一些實施例中，第一總頂表面面積與第一頂表面面積的第一比率與第二總頂表面面積與第二頂表面面積的第二比率之間的差異在約-0.1至約0.1的範圍內。依據一些實施例，周邊晶片110b具有彎曲側壁SW。
依據一些實施例，提供半導體裝置結構的形成方法。這些(用於形成半導體裝置結構的)方法分別形成導電凸塊和虛設導電凸塊於晶圓的中央區域和周邊區域上方。虛設導電凸塊相對於導電凸塊具有(在凸塊與晶圓之間)較大的接觸面積和較小的高度。因此，在後續的製程期間，可防止虛設導電凸塊從晶圓脫落。因此，改善了產率。
依據一些實施例，提供半導體裝置結構的形成方法，此方法包含提供半導體結構，半導體結構具有中央部分和圍繞中央部分的周邊部分。此方法包含在半導體結構的表面上方形成複數個第一導電凸塊和複數個虛設導電凸塊，第一導電凸塊在中央部分上方並電性連接至半導體結構，虛設導電凸塊在周邊部分上方並與半導體結構電性絕緣，第一導電凸塊的每一個具有第一厚度和第一寬度，虛設導電凸塊的每一個具有第二厚度和第二寬度，第二厚度小於第一厚度，且第二寬度大於 第一寬度。
依據一些實施例，提供半導體裝置結構的形成方法，此方法包含提供半導體結構，半導體結構具有中央部分和圍繞中央部分的周邊部分。此方法包含在半導體結構的表面上形成複數個第一導電凸塊和複數個虛設導電凸塊，第一導電凸塊在中央部分上方並電性連接至半導體結構，虛設導電凸塊在周邊部分上方並與半導體結構電性絕緣，第一導電凸塊的每一個具有第一厚度，虛設導電凸塊的每一個具有第二厚度，第二厚度小於第一厚度，且虛設導電凸塊與半導體結構之間的接觸面積大於第一導電凸塊與半導體結構之間的接觸面積。
依據一些實施例，提供半導體裝置結構的形成方法，此方法包含提供半導體結構，半導體結構具有中央部分和圍繞中央部分的周邊部分。此方法包含在半導體結構的表面上方形成複數個第一導電凸塊和複數個虛設導電凸塊，第一導電凸塊在中央部分上方並電性連接至半導體結構，虛設導電凸塊在周邊部分上方並與半導體結構電性絕緣，第一導電凸塊的每一個具有第一厚度，虛設導電凸塊的每一個具有第二厚度，第二厚度小於第一厚度，且虛設導電凸塊的寬度大於第一導電凸塊的相鄰兩者之間的距離。
前述內文概述了許多實施例的特徵，使本技術領域中具有通常知識者可以從各個方面更佳地了解本發明實施例。本技術領域中具有通常知識者應可理解，且可輕易地以本發明實施例為基礎來設計或修飾其他製程及結構，並以此達到相同的目的及/或達到與在此介紹的實施例等相同之優點。本 技術領域中具有通常知識者也應了解這些相等的結構並未背離本發明的發明精神與範圍。在不背離本發明的發明精神與範圍之前提下，可對本發明進行各種改變、置換或修改。

Claims (9)

  1. 一種半導體裝置結構的形成方法，包括：提供一半導體結構，其中該半導體結構具有一中央部分和圍繞該中央部分的一周邊部分，該半導體結構包括複數個晶片區域，複數個預定的切割道在該些晶片區域之間，該些晶片區域包括複數個中央晶片區域和複數個周邊晶片區域；在該半導體結構的一表面上方形成複數個第一導電凸塊和複數個虛設導電凸塊；其中該些第一導電凸塊在該中央部分上方並電性連接至該半導體結構，該些虛設導電凸塊在該周邊部分上方並與該半導體結構電性絕緣，該些第一導電凸塊的每一個具有一第一厚度和一第一寬度，該些虛設導電凸塊的每一個具有一第二厚度和一第二寬度，該第二厚度小於該第一厚度，且該第二寬度大於該第一寬度，該些第一導電凸塊在該些中央晶片區域中，該些虛設導電凸塊在該些周邊晶片區域中；在複數個晶片上方形成複數個第二導電凸塊；透過該些晶片與該半導體結構之間的該些第二導電凸塊和該些第一導電凸塊將該些晶片接合至該半導體結構；以及沿該些預定的切割道將該半導體結構切割為個別之複數個中央晶片和複數個周邊晶片，以產生複數個晶片封裝體，該些晶片封裝體的每一個包括該些中央晶片的其中一個、該些晶片的其中一個以及在該些中央晶片的其中一個與該些晶片的其中一個之間的該些第二導電凸塊和該些第一導電凸塊。
  2. 如申請專利範圍第1項所述之半導體裝置結構的形成方法，其中該中央晶片的一第一頂表面上方的該些第一導電凸塊具有一第一總頂表面面積，該中央晶片具有一第一頂表面面積，該周邊晶片的一第二頂表面上方的該些虛設導電凸塊具有一第二總頂表面面積，該周邊晶片具有一第二頂表面面積，該第一總頂表面面積與該第一頂表面面積的一第一比率與該第二總頂表面面積與該第二頂表面面積的一第二比率之間的差異在約-0.1至約0.1的範圍內。
  3. 如申請專利範圍第1或2項所述之半導體裝置結構的形成方法，其中在該些周邊晶片區域的其中一個中的該些虛設導電凸塊的數量小於該些中央晶片區域的其中一個中的該些第一導電凸塊的數量。
  4. 如申請專利範圍第1或2項所述之半導體裝置結構的形成方法，其中該些周邊晶片區域的其中一個中的該些虛設導電凸塊之間的最小距離大於該些中央晶片區域的其中一個中的該些第一導電凸塊之間的最小距離。
  5. 如申請專利範圍第1或2項所述之半導體裝置結構的形成方法，其中該第一導電凸塊的一第一頂表面相對於該表面具有一第一高度，該虛設導電凸塊的一第二頂表面相對於該表面具有一第二高度，且該第二高度小於該第一高度。
  6. 如申請專利範圍第1項所述之半導體裝置結構的形成方法，其中該虛設導電凸塊與該半導體結構之間的接觸面積大於該第一導電凸塊與該半導體結構之間的接觸面積。
  7. 如申請專利範圍第1、2或6項所述之半導體裝置結構的形成方法，其中該虛設導電凸塊的一頂表面面積大於該第一導電凸塊的一頂表面面積。
  8. 如申請專利範圍第1、2或6項所述之半導體裝置結構的形成方法，其中該半導體結構包括一基底、複數個第一導電墊、複數個第二導電墊和一介電層，該些第一導電墊在該中央部分的該基底上方，該些第二導電墊在該周邊部分的該基底上方，該介電層在該基底上方並覆蓋整個該些第二導電墊，該些第一導電凸塊形成於該些第一導電墊上並電性連接至該些第一導電墊，且整個該些虛設導電凸塊形成於該介電層上並與該些第二導電墊電性絕緣。
  9. 一種半導體裝置結構的形成方法，包括：提供一半導體結構，其中該半導體結構具有一中央部分和圍繞該中央部分的一周邊部分，該半導體結構包括一基底、複數個第一導電墊、複數個第二導電墊和一介電層，該些第一導電墊在該中央部分的該基底上方，該些第二導電墊在該周邊部分的該基底上方，該介電層在該基底上方並覆蓋整個該些第二導電墊；以及在該半導體結構的一表面上方形成複數個第一導電凸塊和複數個虛設導電凸塊；其中該些第一導電凸塊在該中央部分上方並電性連接至該半導體結構，該些虛設導電凸塊在該周邊部分上方並與該半導體結構電性絕緣，該些第一導電凸塊的每一個具有一第一厚度，該些虛設導電凸塊的每一個具有一第二厚度，該第二厚度小於該第一厚度，該虛設導電凸塊的寬度大於該些第一導電凸塊的相鄰兩者之間的距離，該些第一導電凸塊形成於該些第一導電墊上並電性連接至該些第一導電墊，整個該些虛設導電凸塊形成於該介電層上並與該些第二導電墊電性絕緣，且該些虛設導電凸塊的其中一個覆蓋該些第二導電墊的多個部分。
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