TW201802963A - 封裝結構 - Google Patents

封裝結構 Download PDF

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Publication number
TW201802963A
TW201802963A TW105136101A TW105136101A TW201802963A TW 201802963 A TW201802963 A TW 201802963A TW 105136101 A TW105136101 A TW 105136101A TW 105136101 A TW105136101 A TW 105136101A TW 201802963 A TW201802963 A TW 201802963A
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Taiwan
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integrated circuit
circuit die
dummy
layer
redistribution
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TW105136101A
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English (en)
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陳潔
陳憲偉
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台灣積體電路製造股份有限公司
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Publication of TW201802963A publication Critical patent/TW201802963A/zh

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  • Condensed Matter Physics & Semiconductors (AREA)
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  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Semiconductor Integrated Circuits (AREA)

Abstract

本揭露提供封裝結構。封裝結構包含積體電路晶粒。封裝結構也包含環繞積體電路晶粒的封裝層。在積體電路晶粒與封裝層之間具有界面。封裝結構更包含位於封裝層與積體電路晶粒之下的重佈結構，重佈結構包含電性連接至積體電路晶粒的複數主動導線。重佈結構也包含位於複數主動導線之間的虛設導線，虛設導線延伸跨過界面。

Description

封裝結構
本揭露係有關於封裝結構，且特別是有關於具有重佈結構之封裝結構。
半導體裝置已運用在各種電子應用上，像是個人電腦、手機、數位相機以及其他的電子設備。半導體裝置的製造通常會依序將材料的各絕緣層或介電層、導電層、及半導體層沉積在半導體基板上，並且利用微影製程及蝕刻製程將各材料層圖案化以形成電路元件及構件在半導體基板上。通常在單一個半導體晶圓上製造許多積體電路，且藉由沿著切割線切割積體電路，以在晶圓上切割出各個晶粒。舉例而言，接著將個別的晶粒分別封裝在多晶片模組中或其它類型的封裝結構中。
半導體產業藉由持續地降低最小元件尺寸，不斷增加各種電子元件(例如：電晶體、二極體、電阻器、電容器等等)的積體密度，使得更多的元件可集中在一既定面積中。在一些應用中，這些較小型的電子元件也使用採用較小面積及/或較低高度的較小封裝體。
新的封裝技術已開始發展，例如堆疊式封裝(package on package；PoP)，此新的封裝技術將具有一裝置晶粒之一頂封裝體接合至具有另一裝置晶粒之一底封裝體。藉由採用新的封裝技術，將各種具有不同或相似功能的封裝體整合在 一起。這些相對新型的半導體裝置的封裝技術面臨製程上的挑戰，且這些技術並非全方面令人滿意。
根據一些實施例，提供封裝結構。封裝結構包含積體電路晶粒。封裝結構也包含環繞積體電路晶粒的封裝層，在積體電路晶粒與封裝層之間具有界面。封裝結構更包含位於封裝層與積體電路晶粒之下的重佈結構，重佈結構包含電性連接至積體電路晶粒的複數主動導線。重佈結構也包含位於複數主動導線之間的虛設導線，虛設導線延伸跨過界面。
根據一些實施例，提供封裝結構。封裝結構包含包括半導體基底的積體電路晶粒。封裝結構也包含直接接觸半導體基底的邊界的模塑成型化合物。封裝結構更包括位於積體電路晶粒及模塑成型化合物之下的鈍化層，鈍化層具有頂表面直接接觸模塑成型化合物。此外，封裝結構包含位於鈍化層中的第一重佈線，第一重佈線係電性連接至積體電路晶粒。封裝結構也包含位於鈍化層中的第二重佈線，第二重佈線係電性連接至第一重佈線，第一重佈線較第二重佈線更靠近鈍化層之頂表面。封裝結構更包含位於鈍化層中的虛設特徵部件，虛設特徵部件及第一重佈線係大致上位在同一層，虛設特徵部件重疊半導體基底的邊界且沿著交叉於邊界的方向延伸。
根據一些實施例，提供封裝結構。封裝結構包含模塑成型化合物。封裝結構也包含嵌入模塑成型化合物中的半導體基底，在模塑成型化合物與半導體基底之間具有界面。封裝結構更包含位於半導體基底與模塑成型化合物之下的鈍化 層，鈍化層具有直接接觸模塑成型化合物的頂表面及具有與頂表面相對的底表面。此外，封裝結構包含位於鈍化層中的不同層的複數重佈線，鈍化層之頂表面比鈍化層之底表面更靠近複數重佈線之中的最頂層重佈線。封裝結構也包含位於鈍化層中的虛設區段，虛設區段及最頂層重佈線大致上位在同一層，虛設區段位於界面之正下方。
100‧‧‧封裝結構
200‧‧‧積體電路晶粒
210‧‧‧半導體基底
212‧‧‧邊界
220、320‧‧‧鈍化層
230‧‧‧導電墊
240、290、330‧‧‧連接器
250‧‧‧保護層
260‧‧‧封裝層
270‧‧‧導電特徵部件
280‧‧‧構件
300‧‧‧重佈結構
301、302‧‧‧導電層
304、310‧‧‧主動導線
310S、320A、360S‧‧‧頂表面
320B‧‧‧底表面
340‧‧‧界面
360、370‧‧‧虛設特徵部件
362‧‧‧方向
380‧‧‧虛設區段
390‧‧‧陣列
P‧‧‧局部
W1、W2‧‧‧寬度
第1圖係繪示出根據一些實施例之封裝結構的剖面示意圖。
第2圖係繪示出根據一些實施例之封裝結構的平面示意圖。
第3圖係繪示出根據一些實施例之封裝結構的放大剖面示意圖。
第4圖係繪示出根據一些實施例之封裝結構的放大平面示意圖。
第5A至5C圖係繪示出根據一些實施例之封裝結構的放大平面示意圖。
以下的揭露內容提供許多不同的實施例或範例，以實施本發明的不同特徵。而本說明書以下的揭露內容是敘述各個構件及其排列方式的特定範例，以求簡化發明的說明。當然，這些特定的範例並非用以限定本發明。例如，若是本說明書以下的揭露內容敘述了將一第一特徵形成於一第二特徵之 上或上方，即表示其包含了所形成的上述第一特徵與上述第二特徵是直接接觸的實施例，亦包含了尚可將附加的特徵形成於上述第一特徵與上述第二特徵之間，而使上述第一特徵與上述第二特徵可能未直接接觸的實施例。另外，本發明的說明中不同範例可能使用重複的參考符號及/或用字。這些重複符號或用字係為了簡化與清晰的目的，並非用以限定各個實施例及/或所述外觀結構之間的關係。
再者，為了方便描述圖式中一元件或特徵部件與另一(複數)元件或(複數)特徵部件的關係，可使用空間相關用語，例如“在...之下”、“下方”、“下部”、“上方”、“上部”及類似的用語等。可以理解的是，除了圖式所繪示的方位之外，空間相關用語涵蓋使用或操作中的裝置的不同方位。所述裝置也可被另外定位(例如，旋轉90度或者位於其他方位)，並對應地解讀所使用的空間相關用語的描述。可以理解的是，在所述方法之前、期間及之後，可提供額外的操作步驟，且在某些方法實施例中，所述的某些操作步驟可被替代或省略。
以下描述封裝結構的一些實施例。第1圖係繪示出根據一些實施例之封裝結構的剖面示意圖。第2圖係繪示出根據一些實施例之封裝結構的平面示意圖。附加的特徵部件可加入至封裝結構中，以下描述的一些特徵部件可依照不同實施例被替換或消除。
根據一些實施例，如第1圖所示，封裝結構100包含多個積體電路晶粒200。積體電路晶粒200可為包含電晶體、二極體或其他適合的積體電路構件的裝置晶粒，裝置晶粒也可 包含電容器、電感器、電阻器、其他積體電路構件或前述的組合。在一些實施例中，積體電路晶粒200為感測晶粒、邏輯晶粒、中央處理器(central processing unit,CPU)晶粒、記憶體晶粒或其他適合的晶粒。
每個積體電路晶粒200可包含半導體基底210、鈍化層220、導電墊230、連接器240及保護層250。在一些實施例中，半導體基底210包含矽或其他元素半導體材料，例如鍺。在一些實施例中，半導體基底210包含化合物半導體，化合物半導體包含矽鍺、砷化鎵、碳化矽及其他適合的化合物半導體或前述的組合。
各種裝置構件可形成於半導體基底210之中或之上，裝置構件包含主動裝置及/或被動裝置。鈍化層220係連接至半導體基底210。導電墊230位在鈍化層220中且電性連接至裝置構件。保護層250係連接至鈍化層220。連接器240係內嵌於保護層250中且電性連接至導電墊230。
雖然第1圖繪示的封裝結構100包含多個積體電路晶粒200，但本揭露的實施例並不限於此。在一些其他實施例中，封裝結構100包含一個積體電路晶粒200。
根據一些實施例，如第1圖及第2圖所示，積體電路晶粒200係被封裝層260環繞。如第2圖所示，在封裝層260與每個積體電路晶粒200之間具有界面340。在一些實施例中，半導體基底210、鈍化層220及保護層250係內嵌於封裝層260中。在一些實施例中，半導體基底210具有直接接觸封裝層260的邊界212，邊界212與位於封裝層260及積體電路晶粒200之間的界 面340大致上共平面。
在一些實施例中，封裝層260包含聚合物材料。在一些實施例中，封裝層260包含模塑成型化合物(molding compound)，封裝層260的材料不同於半導體基底210的材料。在一些實施例中，封裝層260的材料不同於鈍化層220及/或保護層250的材料。
根據一些實施例，如第1圖所示，封裝層260更進一步環繞多個導電特徵部件270。在一些實施例中，導電特徵部件位於積體電路晶粒200的兩個相對側。在一些其他的實施例中，導電特徵部件270不連續地環繞積體電路晶粒200。
在一些實施例中，導電特徵部件270係導電柱或其他適合的結構，導電特徵部件270可被稱為中介穿孔(interposer vias,TIVs)。在一些實施例中，導電特徵部件270包含銅(Cu)、鋁(Al)、鎳(Ni)、鉑(Pt)、無鉛銲料(例如，錫銀(SnAg)、錫銅(SnCu)、錫銀銅(SnAgCu))及其他適合的導電材料或前述的組合。
可對本揭露的一些實施例作許多變動及修改。在一些其他實施例中，封裝結構100不包含導電特徵部件270。
如第1圖所示，根據一些實施例，封裝結構100也包含位於積體電路晶粒200及封裝層260之下的重佈結構300，重佈結構300係電性連接至積體電路晶粒200之連接器240及導電特徵部件270。在一些實施例中，積體電路晶粒200之前側/正面(主動面)面向重佈結構300。本揭露的實施例並不限於此，在一些其他實施例中，積體電路晶粒200之背側/背面(非主動面) 面向重佈結構300。
重佈結構300包含一層或多層導電層及一層或多層鈍化層，例如重佈結構300包含位於鈍化層320中的導電層301及導電層302。鈍化層320具有頂表面320A及底表面320B，頂表面320A比底表面320B更靠近積體電路晶粒200。在一些實施例中，頂表面320A係直接接觸封裝層260。鈍化層320可包含多層子層(sub-layer)。
在一些實施例中，鈍化層320係由聚苯噁唑(polybenzoxazole,PBO)、苯環丁烯(benzocyclobutene,BCB)、聚矽氧烷(silicone)、丙烯酸酯(acrylates)、矽氧烷(siloxane)、其他適合的材料或前述的組合製成。在一些其他實施例中，位於重佈結構300中的鈍化層320係由非有機材料製成，非有機材料包含氧化矽、未摻雜的矽酸鹽玻璃、氮氧化矽、阻焊劑(solder resist,SR)、氮化矽、碳化矽、六甲基二矽氮烷(hexamethyldisilazane,HMDS)、其他適合的材料或前述的組合。
導電層301及導電層302位於重佈結構300中的不同層，導電層301較導電層302更接近鈍化層320之頂表面320A。在一些實施例中，導電層301為重佈結構300中的最頂層導電層。在一些實施例中，在鈍化層320中具有與導電層301大致上位於同一層的虛設特徵部件(將於後續更詳細地描述)。
在一些實施例中，導電層301及導電層302係由金屬材料製成，金屬材料包含銅(Cu)、銅合金、鋁(Al)、鋁合金、鎢(W)、鎢合金、鈦(Ti)、鈦合金、鉭(Ta)、鉭合金、其他適合 的材料或前述的組合。
根據一些實施例，如第1圖所示，構件280係堆疊於積體電路晶粒200之上，構件280及重佈結構300位於積體電路晶粒200的兩個相對側，構件280係透過導電特徵部件270及重佈結構300電性連接至積體電路晶粒200。
在一些實施例中，構件280包含具有一個或多個積體電路晶粒的封裝結構，封裝結構可為記憶體封裝或其他適合的封裝結構。然而，本揭露的實施例並不限於此，在一些其他實施例中，構件280為積體電路晶粒，構件280可依據不同需求而改變。
在一些實施例中，如第1圖所示，一個或多個連接器290係被用來將構件280接合至積體電路晶粒200之上。連接器290包含銲料凸塊(solder bump)、金屬柱(metal pillar)、其他適合的連接器或前述的組合。
雖然第1圖繪示積體電路晶粒200之上具有一個構件280，但本揭露的實施例並不限於此，在一些其他的實施例中，積體電路晶粒200之上具有多個構件280。
可對本揭露的一些實施例作許多變動及修改。在一些其他實施例中，封裝結構100不包含構件280及連接器290。
根據一些實施例，如第1圖所示，封裝結構100更包含位於重佈結構300之下的多個連接器330。連接器330及積體電路晶粒200係位於重佈結構300的兩個相對側，連接器330係透過重佈結構300電性連接至積體電路晶粒200。在一些實施例中，連接器330包含銲料凸塊、金屬柱、其他適合的連接器 或前述的組合。
在一些實施例中，第1圖所示之封裝結構100進一步透過連接器330接合至基底，基底係為印刷電路板(printed circuit board)、其他封裝結構或其他適合的基底。
第3圖係繪示出根據一些實施例之封裝結構的放大剖面示意圖。第4圖係繪示出根據一些實施例之封裝結構的放大平面示意圖。在一些實施例中，第3圖及第4圖繪示出第1圖所示之封裝結構100的一部分。
根據一些實施例，如第3圖及第4圖所示，鈍化層320中的導電層301包含多個主動導線310。主動導線310係電性連接至積體電路晶粒200，主動導線310亦可被稱為主動重佈線。
如第3圖所示，鈍化層320之頂表面320A較鈍化層320之底表面320B更靠近導電層301之主動導線310。在一些實施例中，主動導線310係重佈結構300中的最頂層重佈線。
在一些實施例中，如第4圖所示，多個主動導線310的其中一個部分地重疊多個連接器240的其中一個且側向地延伸跨過封裝層260及積體電路晶粒200之間的界面340。在一些實施例中，多個主動導線310部分地重疊界面340且沿著與界面340交叉的方向362延伸。
在一些實施例中，主動導線310之寬度W1係介於從大約1μm至大約50μm的範圍。在一些實施例中，寬度W1係介於從大約1μm至大約20μm的範圍。在一些實施例中，主動導線310係由銅、鋁、鎢、鈦、鉭、其他適合的材料或前述的組合製成。
根據一些實施例，如第3圖所示，鈍化層320中具有虛設特徵部件360，虛設特徵部件360係與主動導線310及積體電路晶粒200電性絕緣。在一些實施例中，每個虛設特徵部件360為連續的線，虛設特徵部件360亦可被稱作為虛設重佈線。
根據一些實施例，如第3圖所示，虛設特徵部件360位於封裝層260及積體電路晶粒200之間的界面340之正下方。鈍化層320之頂表面320A較鈍化層320之底表面320B更靠近虛設特徵部件360。
在一些實施例中，虛設特徵部件360與主動導線310係大致上位於同一層，例如虛設特徵部件360與主動導線310係包含於導電層301中，虛設特徵部件360與主動導線310為重佈結構300中的最頂層重佈線。在一些實施例中，虛設特徵部件360具有與主動導線310之頂表面310S大致上共平面的頂表面360S。在一些實施例中，如第3圖所示，虛設特徵部件360部分地重疊包含在位於導電層301之下的導電層302中的多個主動導線304的其中一個。
可對本揭露的一些實施例作許多變動及修改。在一些其他實施例中，一個或多個虛設特徵部件360及主動導線310係位於不同層，例如一個或多個虛設特徵部件360係包含於導電層301之下的導電層302。
在一些實施例中，虛設特徵部件360並不延伸於連接器240及導電特徵部件270之正下方，結果連接器240縱向地重疊多個主動導線310的其中一個而不重疊虛設特徵部件 360，導電特徵部件270縱向地重疊多個主動導線310的其中一個而不重疊虛設特徵部件360。
根據一些實施例，如第4圖所示，虛設特徵部件360部分地重疊封裝層260與積體電路晶粒200之間的界面340。虛設特徵部件360沿著與界面340交叉的方向362延伸，結果虛設特徵部件360延伸跨過界面340。在一些實施例中，如第4圖所示，多個虛設特徵部件360係沿著界面340排列設置。
雖然第4圖繪示虛設特徵部件360部分地重疊積體電路晶粒200以及重疊封裝層260，但本揭露的實施例並不限於此。在一些其他實施例中，虛設特徵部件360部分地重疊積體電路晶粒200或重疊封裝層260而沒有延伸跨過界面340。
在一些實施例中，多個虛設特徵部件360的其中一個係位於多個主動導線340之間。在一些實施例中，多個主動導電層310的其中一個係位於多個虛設特徵部件360之間。在一些實施例中，如第4圖所示，一個或多個虛設特徵部件360係大致上平行於一個或多個主動導線310。可對本揭露的一些實施例作許多變動及修改，在一些其他實施例中，一個或多個虛設特徵部件360係傾斜於一個或多個主動導線310。
根據一些實施例，如第4圖所示，虛設特徵部件360為短於主動導線310之連續的線。在一些實施例中，虛設特徵部件360具有大於主動導線310之寬度W1的寬度。本揭露的實施例並不限於此，在一些其他實施例中，虛設特徵部件360之寬度係小於或大致上等於寬度W1。
在一些實施例中，多個虛設特徵部件360的其中一 個及多個主動導線310的其中一個具有不同的面積，這些面積沿著平行於積體電路晶粒200之主要表面的一平面而取得。雖然第4圖繪示多個虛設特徵部件360的其中一個之面積小於多個主動導線310的其中一個之面積，但本揭露的實施例並不限於此。在一些其他實施例中，從上視方向來看，虛設特徵部件360及主動導線310具有大致上相同的面積。
在一些實施例中，虛設特徵部件360係由金屬材料製成，金屬材料包含銅、鋁、鎢、鈦、鉭、其他適合的材料或前述的組合製成。在一些實施例中，虛設特徵部件360及主動導線310係由相同材料製成。
可對本揭露的一些實施例作許多變動及修改。在一些其他實施例中，虛設特徵部件360係由介電材料製成，介電材料係不同於重佈結構300中的鈍化層320的材料。
根據本揭露的一些實施例，在位於封裝層260及積體電路晶粒200之間的界面340之下具有虛設特徵部件360，結果分散了應力(此應力由異質(heterogeneous)材料所引起且從界面340擴及至重佈結構300中)，且可以避免由於應力的集中可能對重佈結構300中主動導線310造成的損害，例如減少或消除主動導線310中裂縫的形成，因此，封裝結構的可靠度可大幅提升。
根據一些實施例，環狀區(ring region)可被定義於封裝結構100中，從上視方向來看，環狀區延伸橫跨界面340且更進一步沿著界面340延伸。在一些實施例中，環狀區之邊界與界面340之間的距離係介於從大約50μm至大約100μm的範 圍。
根據一些實施例，如第4圖所示，環狀區中的重佈結構300具有局部P部分地重疊界面340。在一些實施例中，局部P的輪廓大致上為正方形，局部P的輪廓係沿著平行於積體電路晶粒200之主要表面的一平面而取得。在一些實施例中，局部P的寬度W2係介於大約5μm至大約10μm的範圍，但本揭露的實施例並不限於此。在一些其他實施例中，局部P並不重疊於界面340。
在一些實施例中，重佈結構300之局部P具有面積比(area ration)或線密度(line density)，面積比定義為局部P中主動導線310及/或虛設特徵部件360的總面積與局部P的面積之比例，上述面積沿著平行於積體電路晶粒200之主要表面的一平面而取得。在一些實施例中，局部P之面積比或線密度係介於從大約40%至大約70%的範圍，因此，可以確認的是從界面340擴及至重佈結構300中的應力係充分地分散且消除。
在一些情況下，局部P之面積比或線密度應為大致上等於或大於大約40%。若局部P之線密度小於大約40%，從界面340擴及至重佈結構300中的應力被集中，可能導致重佈結構300之主動導線中形成裂縫或斷裂。然而，本揭露的實施例並不限於此。在一些其他情況下，局部P之線密度可能小於大約40%。
在一些情況下，局部P之面積比或線密度應為大致上等於或小於大約70%。若局部P之線密度大於大約70%，可能引發一些問題，例如當重佈結構300中之導線之數量較多時可 能有短路的疑慮。另外，可能會導致較難實施圖案化或蝕刻導電材料以形成導線於重佈結構300中。另一方面，當導線之寬度較大時，重佈結構300中導線的佈局設計可能受限。然而，本揭露的實施例並不受限於此。在其他一些實施例中，局部P之線密度可能大於大約70%。
雖然第4圖繪示主動導線310具有一致的寬度，但本揭露的實施例並不受限於此。在一些其他實施例中，從上視方向來看，多個主動導線310的其中一個具有較大的寬度或具有較寬的部分，結果局部P之面積比或線密度增加，因此，從界面340擴及至重佈結構300中的應力係更進一步消減。從上視方向來看，主動導線310中較寬的部分可能或可能不延伸跨過界面340。
可對本揭露的一些實施例作許多變動及/或修改。在一些其他實施例中，第5A至5C圖係繪示出根據一些實施例之封裝結構的放大平面示意圖。在一些實施例中，第5A至5C圖繪示出第1圖所示之封裝結構100之一部分，第5A至5C圖繪示出主動導線310、積體電路晶粒200之連接器240及封裝層260而沒有繪示出封裝結構100中的其他特徵部件，以更佳了解結構。
根據一些實施例，如第5A圖所示，在多個主動導線310中的兩個之間具有多個虛設特徵部件360。在一些實施例中，多個虛設特徵部件360中的兩個係藉由一個虛設特徵部件370彼此連接，虛設特徵部件360為較導線370長的連續的線。
在一些實施例中，如第5A圖所示，導線370延伸跨 過界面340，因此，從界面340擴及至重佈結構300中的應力係被更進一步稀釋分散。在一些其他實施例中，從上視方向來看，導線370重疊積體電路晶粒200或封裝層260而不延伸跨過界面340。在一些實施例中，虛設特徵部件370的材料係大致上相同於虛設特徵部件360的材料。
本揭露的實施例並不限於此，在一些其他實施例中，多個虛設特徵部件360之間並沒有虛設特徵部件370。位於多個主動導線310中的兩個之間的多個虛設特徵部件360係彼此隔離。
根據一些實施例，如第5B圖所示，一個或多個虛設特徵部件360為不連續的線且包含多個分離的虛設區段380。在一些實施例中，虛設區段380中的兩個係分布於界面340的兩個相對側。在一些實施例中，多個虛設區段380的其中一個係部分地重疊界面340。
在一些實施例中，如第5B圖所示，多個虛設區段380沿著主動導線310排列設置。在一些實施例中，一個或多個主動導線310係位於多個虛設區段380中的兩個之間。在一些實施例中，可能沒有主動導線310位於多個虛設區段380中的兩個之間。
在一些實施例中，如第5B圖所示，多個虛設區段380的其中一個重疊界面340且比不重疊也未對準於界面340的其他虛設區段380具有較大的面積，因此，從界面340擴及至重佈結構300中的應力係被更進一步分散。在一些其他實施例中，從上視方向來看，多個虛設區段380中的兩個具有大致上 相同的面積。虛設區段380的輪廓可包含正方形、三角形、近似圓形、橢圓形或其他適合的形狀。
本揭露的實施例並不限於此，在一些其他實施例中，如第5C圖所示，多個虛設區段380係排列設置成一個或多個陣列390。在一些實施例中，多個陣列390的其中一個位於多個主動導線310中的兩個之間。在一些實施例中，多個主動導線310的其中一個延伸於多個陣列390中的兩個之間。
可對本揭露的一些實施例作許多變動及/或修改。在一些其他實施例中，例如，雖然繪示於第1圖的實施例提供具有扇出(fan-out)的特徵之封裝結構100，但本揭露的實施例並不限於此。在本揭露的其他一些實施例包含具有扇入(fan-in)的特徵之封裝結構。
可對本揭露的一些實施例作許多變動及/或修改。在一些其他實施例中，例如，雖然繪示於第1圖的實施例提供堆疊式封裝(package on package；PoP)結構，但本揭露的實施例並不限於此。本揭露的其他一些實施例包含堆疊晶片封裝(chip on package)結構或其他適合的封裝結構。
本揭露的實施例提供封裝結構，封裝結構包含內嵌於封裝層內的積體電路晶粒以及位於積體電路晶粒及封裝層之下的重佈結構。重佈結構包含主動重佈線及虛設重佈線，虛設重佈線係位於積體電路晶粒與封裝層之間的界面之正下方，結果從界面傳遞至重佈結構內的應力被分散或減輕，因此，可以避免由於應力集中可能對主動重佈線造成的損害，因此封裝結構的可靠度可以顯著地提升。
根據一些實施例，本揭露的一些實施例應用於包含重佈結構的封裝結構，從上視方向來看，重佈結構延伸跨過積體電路晶粒與封裝層之間的界面。可對本揭露的一些實施例作許多變動及/或修改。在一些其他實施例中，本揭露可應用於任何適合的結構，其包含延伸跨過以不同材料製成的特徵部件之間的界面的導線。
本揭露根據一些實施例提供封裝結構。封裝結構包含積體電路晶粒。封裝結構也包含環繞積體電路晶粒的封裝層，在積體電路晶粒與封裝層之間具有界面。封裝結構更包含位於封裝層與積體電路晶粒之下的重佈結構，重佈結構包含電性連接至積體電路晶粒的複數主動導線。重佈結構也包含位於複數主動導線之間的虛設導線，虛設導線延伸跨過積體電路晶粒與封裝層之間的界面。
本揭露根據一些實施例提供封裝結構。封裝結構包含包括半導體基底的積體電路晶粒。封裝結構也包含直接接觸半導體基底的邊界的模塑成型化合物。封裝結構更包括位於積體電路晶粒及模塑成型化合物之下的鈍化層，鈍化層具有頂表面直接接觸模塑成型化合物。此外，封裝結構包含位於鈍化層中的第一重佈線，第一重佈線係電性連接至積體電路晶粒。封裝結構也包含位於鈍化層中的第二重佈線，第二重佈線係電性連接至第一重佈線，第一重佈線較第二重佈線更靠近鈍化層之頂表面。封裝結構更包含位於鈍化層中的虛設特徵部件，虛設特徵部件及第一重佈線係大致上位在同一層，虛設特徵部件重疊半導體基底的邊界且沿著交叉於邊界的方向延伸。
本揭露根據一些實施例提供封裝結構。封裝結構包含模塑成型化合物。封裝結構也包含嵌入模塑成型化合物中的半導體基底，在模塑成型化合物與半導體基底之間具有界面。封裝結構更包含位於半導體基底與模塑成型化合物之下的鈍化層，鈍化層具有直接接觸模塑成型化合物的頂表面及具有與頂表面相對的底表面。此外，封裝結構包含位於鈍化層中的不同層的複數重佈線，鈍化層之頂表面比鈍化層之底表面更靠近複數重佈線之中的最頂層重佈線。封裝結構也包含位於鈍化層中的虛設區段，虛設區段及最頂層重佈線大致上位在同一層，虛設區段位於界面之正下方。
以上概略說明了本發明數個實施例的特徵，使所屬技術領域中具有通常知識者對於後續本發明的詳細說明可更為容易理解。任何所屬技術領域中具有通常知識者應瞭解到本說明書可輕易作為其它結構或製程的變更或設計基礎，以進行相同於本發明實施例的目的及/或獲得相同的優點。任何所屬技術領域中具有通常知識者也可理解與上述等同的結構或製程並未脫離本發明之精神和保護範圍內，且可在不脫離本發明之精神和範圍內，當可作更動、替代與潤飾。
200‧‧‧積體電路晶粒
240‧‧‧連接器
260‧‧‧封裝層
301‧‧‧導電層
310‧‧‧主動導線
340‧‧‧界面
360‧‧‧虛設特徵部件
362‧‧‧方向
P‧‧‧局部
W1、W2‧‧‧寬度

Claims (1)

  1. 一種封裝結構，包括：一積體電路晶粒；一封裝層，環繞該積體電路晶粒，其中在該積體電路晶粒與該封裝層之間具有一界面；以及一重佈結構，位於該積體電路晶粒與該封裝層之下，其中該重佈結構包括：複數主動導線，電性連接至該積體電路晶粒；以及一虛設導線，位於該些主動導線之間，其中該虛設導線延伸跨過該界面。
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US10163800B2 (en) 2018-12-25
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