TWI442524B - 覆晶封裝以及半導體晶片 - Google Patents

覆晶封裝以及半導體晶片 Download PDF

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Publication number
TWI442524B
TWI442524B TW100128220A TW100128220A TWI442524B TW I442524 B TWI442524 B TW I442524B TW 100128220 A TW100128220 A TW 100128220A TW 100128220 A TW100128220 A TW 100128220A TW I442524 B TWI442524 B TW I442524B
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Taiwan
Prior art keywords
layer
bump
wafer
copper
chip package
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TW100128220A
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English (en)
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TW201208005A (en
Inventor
Tzu Hung Lin
Thomas Matthew Gregorich
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Mediatek Inc
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Publication of TW201208005A publication Critical patent/TW201208005A/zh
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Publication of TWI442524B publication Critical patent/TWI442524B/zh

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Description

覆晶封裝以及半導體晶片
本發明係關於一種覆晶封裝(flip chip package)，特別是關於一種覆晶封裝以及半導體晶片(semiconductor die)。
為了持續地微型化(miniaturization)電子產品及通訊裝置，並同時確保其具備之多功能性(multi-functionality)，半導體封裝(semiconductor package)必須符合尺寸小、連接腳數多、運作快速以及功能性多的特性。而為了同時增加輸入輸出(input-output,I/O)連接腳數以及提升積體電路(integrated circuit,IC)的效能，因此發展出覆晶封裝技術。
覆晶封裝技術係利用設置於晶片上的凸塊(bump)，內連接於封裝媒介，例如封裝基板(package substrate)。且覆晶係以面朝下之方式，透過最短之路徑連接於封裝基板。該技術不僅適用於單晶片封裝，也適用於結構更複雜的多晶片封裝，多晶片封裝可在單位面積內容納更多晶片，因此具備更優異之效能。面積陣列覆晶技術之優點在於可提升裝置的內連線(interconnection)密度，並且降低封裝體內之內連線所產生的電感(inductance)。
第1圖所顯示的是習知覆晶封裝的部分結構剖面示意圖。如第1圖所示，習知的覆晶封裝1是利用凸塊連接墊(bump-on-pad,BOC)內連線方法。封裝基板2的晶片安置面上設置至少兩相鄰之連接墊(capture pad)21a、21b以及金屬導線(metal trace)22。焊錫遮罩(solder cap)26覆蓋住封裝基板2的晶片安置面。焊錫遮罩26具有銲錫遮罩定義(solder mask defined,SMD)的開孔，該些開孔對應於連接墊21a、21b，用以限制在內連線過程中焊錫的流動(flow of solder)範圍。
設置於晶片3主動面(active side)之內連線焊錫凸塊31a、31b係用來分別連接暴露出的連接墊21a、21b。執行內連線焊錫凸塊31a、31b的回焊(reflow)過程後，填充一底膠物質(underfill material)4至基板2及晶片3間的間隙(gap)，以機械性固定(stabilize)內連線結構，其中，此間隙的間隙高度(stand-off height)為h。
然而，上述習知技術之缺點在於許多位於封裝基板2頂層上的配線空間(routing space)會被浪費。此可歸因於一般連接墊之寬度或是直徑通常與焊錫球(ball)(或凸塊)之直徑相等，且其寬度會達到導線(或接腳)寬度的2至4倍。上述習知技術之另一缺點在於晶片和封裝基板之間間隙高度不足，因此限制了在覆晶裝配流程(assembly flow)中執行底膠填入時的製程能力(process window)、可靠度(reliability)以及產率(throughput)。
有鑑於此，本發明之目的在於提供一覆晶封裝以及半導體晶片。
本發明提供一種覆晶封裝，包含有：一基板，具有一晶片安置面；以及一晶片，設於該晶片安置面上，該晶片具有一朝向該基板之主動面，其中該晶片係透過複數個銅柱凸塊內連接至該基板，其中該複數個銅柱凸塊位於該主動面上，且該複數個銅柱凸塊之至少一者其凸塊寬度小於或等於一導線之一線寬，其中該導線位於該基板之該晶片安置面上。
本發明還提供一種半導體晶片，包含有：一基底；一最上層金屬層，位於該基底上；一應力緩衝層，設於該最上層金屬層上，其中該應力緩衝層具有一開孔，顯露出至少一部分的該最上層金屬層；以及一銅柱凸塊，經由該開孔耦接與連接該最上層金屬層。
本發明提供的覆晶封裝以及半導體晶片能有效的抵擋製程應力、獲得更佳配線能力或更利於填膠程序，較習知技術具有顯著進步。
於下文中，係加以陳述本發明之具體實施方式，該些具體實施方式可參考相對應的圖式，俾使該些圖式構成實施方式之一部分。同時也藉由說明，揭露本發明可據以施行之方式。於下文中，將清楚地描述該些實施例之細節，俾使該技術領域中具有通常技術者可據以實施本發明。在不違背於本發明宗旨之前提下，相關之具體實施例亦可被加以施行，且對於其結構上、邏輯上以及電性上所做之改變仍屬本發明所涵蓋之範疇。另外，本案中所稱覆晶封裝，亦可稱為覆晶封裝結構或覆晶封裝單元。
請參照第2圖以及第3圖。第2圖所繪示的是根據本發明之一實施例之部分覆晶封裝俯視示意圖。而第3圖所繪示的是沿著第2圖I-I’切線的部分結構剖面示意圖。如第2圖及第3圖所示，覆晶封裝10包含有一封裝基板20，封裝基板20具有一晶片安置面20a。複數條導線210a、210b、220a及220b設置於封裝基板20的晶片安置面20a上，並以虛線的方式表示於第2圖中。根據本發明之具體實施例，210a、210b、220a及220b中的至少一導線的線寬W介於10μm至40μm之間，例如25μm，以及其導線間距(trace pitch)P介於30μm至70μm之間，例如50μm。根據本發明之實施例，介於兩相鄰導線之間距(space)S係介於10μm至40μm之間，例如25μm。
晶片安置面20a能被焊錫遮罩260覆蓋住。根據本發明之實施例，焊錫遮罩260可由光敏物質(photosensitive material)構成且可以藉由曝光顯影(photolithographic)製程以部分地暴露出導線210a、210b、220a及220b以及部分的晶片安置面20a。舉例而言，一位於預設開孔區的焊錫遮罩260係位於晶片30之正下方，且可移除焊錫遮罩260，俾以形成一具有開孔之焊錫遮罩或打開的防焊阻劑(resist)結構，使導線210a、210b、220a及220b暴露於預設開孔區。
如第3圖所示，封裝基板20之晶片安置面20a上附著(mount)一半導體晶片或晶片30，且晶片30之主動面係朝向封裝基板20。晶片30的電路係透過新穎的導線凸塊導線(trace bump trace,TBT)方式，內連結於封裝基板20內之電路。TBT內連線方式之特徵在於複數個細長之銅柱凸塊310a、310b係設置於晶片30之主動面。至少一銅柱凸塊310a、310b係由金屬堆疊結構所構成，且該金屬堆疊結構可包含凸塊底金層(under bump metallurgy,UBM)，例如，一濺鍍之UBM層(圖未示)、一銅層312，例如，電鍍銅層、以及一焊錫蓋層314。銅柱凸塊310a、310b之細部結構將於下文討論之。
根據此實施例，如同第2圖所示，銅柱凸塊310a、310b之俯視形狀為卵形(oval-shaped)。根據此實施例，銅柱凸塊310a、310b中的至少一個之俯視形狀呈現圓滑且稍微延長(elongate)之外觀，並沿著細微導線延伸。根據此具體實施例，至少一銅柱凸塊(例如銅柱凸塊310b)之凸塊寬度Wb小於或等於位於封裝基板20上之導線(例如導線210b)線寬W。根據本發明之一實施例，至少一銅柱凸塊(例如銅柱凸塊310b)之凸塊長度Lb可至少兩倍長於導線線寬W。舉例來說，銅柱凸塊310a、310b中的至少一個可具有一凸塊寬度Wb以及一凸塊長度Lb。其中凸塊寬度Wb數值介於10μm至40μm之間，例如25μm。凸塊長度Lb數值介於40μm至80μm之間，例如60μm。根據本發明之實施例，晶片30的凸塊間距介於120μm至180μm之間，例如150μm。
請參考第3圖，銅柱凸塊310a、310b各別對應至晶片安置面20a上的導線210a、210b。在覆晶組裝的過程中，舉例來說，銅柱凸塊310a、310b會分別連接至導線210a、210b。因為銅柱凸塊310a、310b具有較小之尺寸，因此可以降低產生的應力(stress)增加凸塊至導線之間距並且有效避免凸塊至導線之橋接(bridging)。進一步來說，也能獲得更多的配線空間。經過回焊的過程後，可填充底膠材料或底膠40至晶片30與封裝基板20之間，此空間具有較高的間隙高度H。較高的間隙高度H意味著有利於填膠的程序。根據此較佳實施例，底膠40可以是毛細型底膠(capillary underfill,CUF)、模塑型底膠(molded underfill,MUF)或上述組合。
第4圖所繪示的是根據本發明之一較佳實施例之銅柱凸塊310的結構之剖面示意圖，且此銅柱凸塊位於晶片主動面上。其中，銅柱凸塊的剖面圖係沿著銅柱凸塊的縱長(lengthwise)方向所繪示。如第4圖所示，晶片30可包含有一基底(base)320、一第一保護層(passivation layer)322、一最上層金屬層(topmost metal layer) 323、一第二保護層324以及一應力緩衝層(stress buffering layer) 326。其中，該第一保護層322位於基底320上，該最上層金屬層(topmost metal layer) 323位於第一保護層322上，該第二保護層324位於最上層金屬層323以及第一保護層322上，以及該應力緩衝層(stress buffering layer) 326位於第二保護層324之上。於此所述之「位於…上」係可表示於空間中「上面」之意。根據此較佳實施例，基底320可包含半導體基板、設置於半導機基板主要面(main surface)之電路元件、層間介電層(inter-layer dielectric,ILD)以及內連線。第一保護層322可為氮化矽(silicon nitride)、氧化矽(silicon oxide)、氧氮化矽(silicon oxynitride)或上述之組合。第二保護層324可為氮化矽、氧化矽、氧氮化矽或上述之組合。應力緩衝層326可為聚亞醯胺(polyimide)、聚苯并噁唑(polybenzoazole,PBO)或上述之組合。最上層金屬層323可為鋁、銅或兩者之合金。其中，應力緩衝層326也可包含第二保護層324。
開孔326a可形成於應力緩衝層326內，以暴露出至少一部分之最上層金屬層323。且開孔326a可以呈現任何形狀。根據本發明之實施例，應力緩衝層326可以是呈現細長狀、卵形的開孔，沿著銅柱凸塊的縱長方向做延伸。UBM層311可形成於暴露出於開孔326a內之最上層金屬層323之上。UBM層311也可以向外延伸至應力緩衝層326之上表面。根據本實施例，UBM層311可藉由濺鍍之方法形成，且其成分可為鈦(titanium)、銅或其結合。舉例而言，UBM 311可包含一鈦層以及一銅層，其中，該鈦層厚度介於500埃(angstroms)至1500埃，例如1000埃，該銅層厚度介於3000埃至5000埃，例如5000埃。銅層312(例如電鍍銅層)可形成於UBM層311之上。根據本實施例，銅層312的厚度介於30μm至60μm之間，例如45μm。銅層312及UBM層311可填入應力緩衝層326，並且位於應力緩衝層326內之銅層312及UBM層311可形成一體成形之插塞(integral plug)312a，以使銅柱凸塊310電耦合於其下之最上層金屬層323。焊錫遮罩層314的厚度介於10μm至40μm之間，例如25μm，且焊錫遮罩層314可形成於銅層312之上。鎳層313的厚度介於1μm至5μm之間，例如3μm，且鎳層可形成於銅層312以及焊錫遮罩314之間。銅層(例如銅層312)可以是部分的重分配層(re-distribution layer,RDL)或是與RDL一同形成。
第5圖所繪示的是根據本發明之另一較佳實施例之位於晶片主動面上之銅柱凸塊310a結構之剖面示意圖。同樣地，銅柱凸塊的剖面圖係沿著銅柱凸塊的縱長方向所繪示。如第5圖所示，晶片30a可包含有一基底320、一第一保護層322、一最上層金屬層323、一第二保護層324以及一應力緩衝層326。其中，該第一保護層322位於基底320上，該最上層金屬層323位於第一保護層322上，該第二保護層324位於最上層金屬層323以及第一保護層322上以及該應力緩衝層326位於第二保護層324上。根據此較佳實施例，基底320可包含半導體基板、設置於半導機基板主要面之電路元件、層間介電層以及內連線。兩個開孔326b、326c可形成於應力緩衝層326內，以暴露出部分之最上層金屬層323。開孔326b、326c可以呈現任何形狀。UBM層311可形成於暴露出於開孔326b、326c之最上層金屬層323之上。UBM層311可填入開孔326b、326c，且UBM層311可向外延伸至應力緩衝層326之上表面。根據本實施例，UBM層311可藉由濺鍍之方法形成，且其成分可為鈦、銅或其結合。UBM層311可包含一鈦層以及一銅層，其中，該鈦層厚度介於500埃至1500埃，例如1000埃，以及該銅層厚度介於3000埃至7000埃，例如5000埃。一銅層312(例如電鍍銅層)可形成於UBM層311之上。至少位於開孔326b、326c內之UBM層311可形成雙體成形之插塞(dual integral plug)312b、312c，俾使銅柱凸塊310a電耦合於其下之最上層金屬層323。焊錫遮罩層314可形成於銅層312之上。鎳層313可形成於銅層312以及焊錫遮罩層314之間。
本發明之另一項特徵是凸塊長軸之走向(orientation)。第6圖所繪示的是根據本發明之另一較佳實施例之位於晶片主動面上之銅柱凸塊(310b)結構俯視圖。而第7圖所繪示的是沿著第6圖II-II’切線之銅柱凸塊剖面示意圖，其中相同的元件符號代表類似的區域、層或元件。為了使本發明清晰易懂，第6圖僅繪示出部分之晶片角落區域，且僅繪示出一凸塊。如第6圖所示，銅柱凸塊310b之俯視形狀為卵形，且呈現圓滑且稍微延長之外觀，並沿著銅柱凸塊的縱長方向延伸。在本實施例中，銅柱凸塊310b之縱長方向，意即凸塊長軸走向，係指向晶片30b之中心。根據本具體實施例，銅柱凸塊310b沿著凸塊縱長方向具有不對稱之插塞結構(asymm-etric plug configuration)。且更精確而言，插塞312c係置於低應力區(lower stress side)，此低應力區由箭頭所標示出，然而，在遠離晶片中心之高應力區則並未設置有任何插塞。
第7圖繪示的是設置於晶片30b上之不對稱結構之銅柱凸塊310b。如第7圖所示，同樣地，晶片30b可包含有一基底320、一第一保護層322位於基底320上、一最上層金屬層323位於第一保護層322上、一第二保護層324位於最上層金屬層323以及第一保護層322上以及一應力緩衝層326位於第二保護層324上。根據此較佳實施例，基底320可包含半導體基板、設置於半導機基板主要面之電路元件、層間介電層以及內連線，但不限於此。開孔326c形成於應力緩衝層326內之低應力區，亦即形成於較靠近晶片中心之區域，並暴露出部分之最上層金屬層323。開孔326c可呈現任何形狀。可於暴露出於開孔326c之最上層金屬層323之上形成一UBM層311，且UBM層311可填入於開孔326c中。UBM層311可向外延伸至應力緩衝層326之上表面。根據本實施例，UBM層311可藉由濺鍍方法形成，且其成分包含鈦、銅或其結合。UBM層311可包含一厚度介於500埃至1500埃之鈦層，例如1000埃，以及一厚度介於3000埃至7000埃之銅層，例如5000埃。一銅層312，例如電鍍銅，可形成於UBM層311之上。至少位於開孔326c內之UBM層311可形成一體成形之插塞312c，俾使銅柱凸塊310b電耦合於其下之最上層金屬層323。焊錫遮罩層314可形成於銅層312之上。而鎳層313可形成於基板312以及焊錫遮罩層314之間。由於在高應力區之應力緩衝層326，亦即遠離晶片中心之區域的完整性(integrity)，其並未被插塞和介層開孔破壞，因此位於基底320內的低介電常數(extra-low k,ELK)介電層或超低介電常數(ultra-low k,ULK)介電層能有效的抵擋住製程之應力，例如，熱膨脹(thermal expansion)或晶片翹曲(wafer warpage)所產生之應力。第6圖及第7圖的凸塊長軸走向的另一優點在於，可藉由此凸塊長軸走向而獲得較佳之配線能力。在此長軸走向配置下，兩鄰近凸塊的間距可得以增加，因此可於基板中容納更多之導線。
以上所述僅為本發明之較佳實施例，凡依本發明申請專利範圍所做之均等變化與修飾，皆應屬本發明之涵蓋範圍。
1．．．覆晶封裝
2．．．封裝基板
3．．．晶片
4．．．底膠物質
10．．．覆晶封裝
20．．．封裝基板
20a．．．晶片安置面
21a、21b．．．連接墊
22．．．金屬導線
26．．．焊錫遮罩
30、30a 30b．．．晶片
31a、31b．．．內連線焊錫凸塊
40．．．底膠
210a、210b 220a、220b．．．線導
260．．．焊錫遮罩
310a、310b．．．銅柱凸塊
311．．．凸塊底金層
312．．．銅層
312a、312b 312c．．．插塞
313．．．鎳層
314．．．焊錫蓋層
320．．．基底
322．．．第一保護層
323．．．最上層金屬層
324．．．第二保護層
326．．．應力緩衝層
326a、326b 326c‧‧‧開孔
h‧‧‧間隙高度
H‧‧‧間隙高度
Lb‧‧‧凸塊長度
P‧‧‧導線間距
S‧‧‧間距
Wb‧‧‧凸塊寬度
W‧‧‧線寬
I-I’‧‧‧切線
II-II’‧‧‧切線
下列圖式之目的在於使本發明能更容易地被理解，於本文中會詳加描述該些圖式，並構成具體實施例的一部份。透過本文中之具體實施例並參考相對應的圖式，俾以詳細解說本發明之具體實施例，並用以闡述發明之作用原理。
第1圖所繪示的是習知具有焊錫球之覆晶封裝之部分剖面圖。
第2圖所繪示的是根據本發明之一實施例之覆晶封裝之部分俯視圖。
第3圖所繪示的是沿著第2圖中I-I’切線的部分剖面圖。
第4圖所繪示的是根據本發明之一較佳實施例之位於晶片主動面上之銅柱凸塊結構之剖面示意圖。
第5圖所繪示的是根據本發明之另一較佳實施例之位於晶片主動面上之銅柱凸塊結構之剖面示意圖。
第6圖所繪示的是根據本發明之另一較佳實施例之位於晶片主動面上之銅柱凸塊結構之俯視圖。
第7圖所繪示的是沿著第6圖II-II’切線之銅柱凸塊剖面示意圖。
值得注意的是，所有的圖式僅作為示意之用途。為了達到解說之目的，繪製於圖式中之元件尺寸及比例可能被加以放大或縮小。在不同的具體實施例中，相同的元件符號會被用以代表相對應或相似的特徵。
10．．．覆晶封裝
20．．．封裝基板
20a．．．晶片安置面
30．．．晶片
210a、210b 220a、220b．．．導線
310a、310b．．．銅柱凸塊
Lb．．．凸塊長度
W．．．線寬
Wb．．．凸塊寬度
I-I’．．．切線

Claims (20)

  1. 一種覆晶封裝，包含有：一基板，具有一晶片安置面；以及一晶片，設於該晶片安置面上，該晶片具有一朝向該基板之主動面，其中該晶片係透過複數個銅柱凸塊內連結至該基板，其中該複數個銅柱凸塊位於該主動面，且該複數個銅柱凸塊之至少一者其凸塊寬度小於或等於該晶片安置面上之一導線之線寬，其中該導線位於該基板之該晶片安置面上。
  2. 如申請專利範圍第1項所述之覆晶封裝，其中該複數個銅柱凸塊之至少一者其凸塊長度為該導線之線寬的兩倍以上。
  3. 如申請專利範圍第1項所述之覆晶封裝，其中該複數個銅柱凸塊之至少一者其俯視形狀為卵形。
  4. 如申請專利範圍第1項所述之覆晶封裝，其中該複數個銅柱凸塊之至少一者係由金屬堆疊結構所構成，且該金屬堆疊結構包含有一凸塊底金層、一銅層以及一焊錫蓋層。
  5. 如申請專利範圍第4項所述之覆晶封裝，其中該銅層的厚度介於30μm至60μm。
  6. 如申請專利範圍第4項所述之覆晶封裝，其中該焊錫蓋層的厚度 介於10μm至40μm。
  7. 如申請專利範圍第4項所述之覆晶封裝，其中該複數個銅柱凸塊之至少一者另包含有一鎳層，該鎳層位於該銅層與該焊錫蓋層之間。
  8. 如申請專利範圍第1項所述之覆晶封裝，其中該導線之線寬介於10μm至40μm之間。
  9. 如申請專利範圍第1項所述之覆晶封裝，其中該晶片的凸塊間距介於120μm至180μm之間。
  10. 如申請專利範圍第1項所述之覆晶封裝，其中該複數個銅柱凸塊之至少一者其凸塊寬度介於10μm至40μm之間，而其凸塊長度介於40μm至80μm之間。
  11. 如申請專利範圍第1項所述之覆晶封裝，其中該複數個銅柱凸塊之至少一者其凸塊長軸走向係指向該晶片之一中心。
  12. 如申請專利範圍第1項所述之覆晶封裝，其中另包含一底膠，該底膠位於該晶片與該基板之間。
  13. 如申請專利範圍第12項所述之覆晶封裝，其中該底膠包含有毛細型底膠(capillary underfill,CUF)、模塑型底膠(molded underfill, MUF)或上述組合。
  14. 一種半導體晶片，包含有：一基底；一最上層金屬層，位於該基底上；一應力緩衝層，設於該最上層金屬層上，其中該應力緩衝層具有一開孔，顯露出至少部分的該最上層金屬層；以及一銅柱凸塊，經由該開孔耦接該最上層金屬層；其中，該半導體晶片用于設于一基板的晶片安置面上，該半導體晶片透過該銅柱凸塊內連結至該基板，且其中，該銅柱凸塊之凸塊寬度小於或等於導線之線寬，其中該導線位於該基板之該晶片安置面上。
  15. 如申請專利範圍第14項所述之半導體晶片，其中該銅柱凸塊其俯視形狀為卵形。
  16. 如申請專利範圍第14項所述之半導體晶片，其中該銅柱凸塊係由金屬堆疊結構所構成，且該金屬堆疊結構包含有一凸塊底金層、一銅層以及一焊錫蓋層。
  17. 如申請專利範圍第16項所述之半導體晶片，其中銅層的一厚度介於30μm至60μm。
  18. 如申請專利範圍第16項所述之半導體晶片，其中該焊錫蓋層的一厚度介於10μm至40μm。
  19. 如申請專利範圍第14項所述之半導體晶片，其中該銅柱凸塊的一凸塊寬度介於10μm至40μm之間，該銅柱凸塊的一凸塊長度介於40μm至80μm之間。
  20. 如申請專利範圍第14項所述之半導體晶片，其中該銅柱凸塊之凸塊長軸走向係指向該半導體晶片之中心。
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