CN102376668B - 覆晶封装结构以及半导体芯片 - Google Patents

覆晶封装结构以及半导体芯片 Download PDF

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CN102376668B
CN102376668B CN2011102206594A CN201110220659A CN102376668B CN 102376668 B CN102376668 B CN 102376668B CN 2011102206594 A CN2011102206594 A CN 2011102206594A CN 201110220659 A CN201110220659 A CN 201110220659A CN 102376668 B CN102376668 B CN 102376668B
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chip
copper post
projection
layer
substrate
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CN102376668A (zh
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林子闳
童耿直
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MediaTek Inc
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MediaTek Inc
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Abstract

本发明提供一种覆晶封装结构以及半导体芯片，其中，覆晶封装结构包括基底；最上层金属层，位于该基底上；应力缓冲层，设于该最上层金属层上，其中该应力缓冲层具有开孔，以显露出至少一部分的该最上层金属层；以及铜柱凸块，通过该开孔耦接该最上层金属层。本发明提供的覆晶封装结构以及半导体芯片可有效的抵挡制程应力、获得更佳布线能力或更利于填胶程序，较传统技术具有显著进步。

Description

覆晶封装结构以及半导体芯片
技术领域
本发明关于一种覆晶封装结构(flip chip package)，特别是关于一种覆晶封装结构以及半导体芯片(semiconductor die)。
背景技术
为了持续地微型化(miniaturization)电子产品及通信设备，并同时确保其具备的多功能性(multi-functionality)，半导体封装(semiconductor package)必须符合尺寸小、连接脚数多、运作快速以及功能性多的特性。而为了同时增加输入输出(Input-Output，I/O)连接脚数以及提升集成电路(Intergrated Circuit，IC)的性能，因此发展出覆晶封装技术。
覆晶封装技术是利用设置于芯片上的凸块(bump)内连线于封装介质，例如封装基板(package substrate)。且覆晶芯片是以面朝下的方式，透过最短路径连接于封装基板。该技术不仅适用于单芯片封装，也适用于结构更复杂的多芯片封装，多芯片封装可在单位面积内容纳更多芯片，因此具备更优异的性能。面积数组倒装芯片技术的优点在于可提升设备的内连线(interconnection)密度，并且降低封装体内的内连线所产生的电感(inductance)。
图1是传统覆晶封装结构的部分结构剖面示意图。如图1所示，传统的覆晶封装结构1是利用凸块连接垫(bump-on-pad，BOC)内连线方法。封装基板2的芯片安置面上设置至少两相邻的连接垫(capture pad)21a、21b以及金属导线(metal trace)22。焊锡盖(solder cap)26覆盖住封装基板2的芯片安置面。焊锡盖26具有焊锡盖定义(solder mask defined，SMD)的开孔，该些开孔对应于连接垫21a、21b，用于限制在内连线过程中焊锡的流动(flow of solder)范围。
设置于芯片3有效面(active side)的内连线焊锡凸块31a、31b用来分别连接露出的连接垫21a、21b。执行内连线焊锡凸块31a、31b的回焊(reflow)过程后，填充底充胶物质(underfill material)4至基板2及芯片3间的间隙(gap)，以机械性固定(stabilize)内连线结构，其中，此间隙的间隙高度(stand-off height)为h。
然而，上述传统技术的缺点在于许多位于封装基板2顶层上的布线空间(routing space)会被浪费。此可归因于一般连接垫的宽度或是直径通常与焊锡球(ball)(或凸块)的直径相等，且其宽度会达到导线(或接脚)宽度的2至4倍。上述传统技术的另一缺点在于芯片和封装基板之间间隙高度不足，因此限制了在倒装芯片装配流程(assembly flow)中执行底充胶填入时的制程能力(processwindow)、可靠度(relaibility)以及产率(throughput)。
发明内容
有鉴于此，本发明提供一种覆晶封装结构以及半导体芯片。
本发明提供一种覆晶封装结构，包括：基板，具有芯片安置面；以及芯片，设于该芯片安置面上，该芯片具有朝向该基板的有效面，其中该芯片为透过多个铜柱凸块内连线至该基板，其中该多个铜柱凸块位于该有效面上，且该多个铜柱凸块中的至少一个的凸块宽度小于或等于导线的线宽，其中该导线位于该基板的该芯片安置面上。
本发明还提供一种半导体芯片，包括：基底；最上层金属层，位于该基底上；应力缓冲层，设于该最上层金属层上，其中该应力缓冲层具有开孔，以显露出至少一部分的该最上层金属层；以及铜柱凸块，通过该开孔耦接该最上层金属层。
本发明提供的覆晶封装结构以及半导体芯片可有效的抵挡制程应力、获得更佳布线能力或更利于填胶程序，较传统技术具有显著进步。
附图说明
图1是传统覆晶封装结构的部分结构剖面示意图；
图2是根据本发明一个实施例的部分覆晶封装结构俯视示意图；
图3是沿着图2I-I’切线的部分结构剖面示意图；
图4是根据本发明一个较佳实施例的铜柱凸块310的结构剖面示意图；
图5是根据本发明另一个较佳实施例的位于芯片有效面上的铜柱凸块310a的结构剖面示意图；
图6是根据本发明另一个较佳实施例的位于芯片有效面上的铜柱凸块310b的结构俯视示意图；
图7是设置于芯片30b上的铜柱凸块310b的不对称塞棒结构的结构剖面示意图。
具体实施方式
下文中陈述本发明的具体实施方式，该些具体实施方式可参考相对应的图式，以使这些图式组成实施方式的一部分。同时也由此说明，揭露本发明可依据的施行方式。在下文中，将清楚地描述这些实施例的细节，以使所述领域的技术人员可据以实施本发明。在不违背于本发明宗旨之前提下，相关之具体实施例亦可被加以施行，且对于其结构上、逻辑上以及电性上所做的改变仍属本发明所涵盖的范围。另外，本案中所称覆晶封装结构，亦可称为覆晶封装体或覆晶封装单元。
请参照图2以及图3。图2是根据本发明一个实施例的部分覆晶封装结构俯视示意图。而图3是沿着图2I-I’切线的部分结构剖面示意图。如图2及图3所示，覆晶封装结构10包括封装基板20，封装基板20具有芯片安置面20a。复数条导线210a、210b、220a及220b设置于封装基板20的芯片安置面20a上，并以虚线的方式表示于图2中。根据本发明的具体实施例，210a、210b、220a及220b中的至少一条导线的线宽W介于10μm(微米)至40μm之间，例如25μm，以及其导线间距(trace pitch)P介于30μm至70μm之间，例如50μm。根据本发明的实施例，介于两相邻导线的间距(space)S系介于10μm至40μm间，例如25μm。
芯片安置面20a能被焊锡盖260覆盖住。根据本发明的实施例，焊锡盖260可由光敏物质(photosensitive material)组成且可以通过曝光显影(photolithographic)方法来部分地露出导线210a、210b、220a及220b以及部分的芯片安置面20a。举例而言，位于预设开孔区的焊锡盖260位于芯片30的正下方，且可移除焊锡盖260，以形成具有开孔的焊锡盖或打开的防焊阻剂(resist)结构，使导线210a、210b、220a及220b露出于预设开孔区。
如图3所示，封装基板20的芯片安置面20a上附着(mount)半导体芯片或芯片30，且芯片30的有效面朝向封装基板20。芯片30的电路透过新颖的导线凸块导线(trace bump trace，TBT)方式，内连线于封装基板20内的电路。TBT内连线方式的特征在于多个细长(lathy)的铜柱凸块310a、310b设置于芯片30的有效面。铜柱凸块310a、310b中的至少一个是由金属层叠(metal stack)结构所组成，且该金属层叠结构可包括凸块下金属层(underbump metallurgy，UBM)、铜层312以及焊锡盖层314，其中凸块下金属层可例如溅镀(sputtered)的UBM层(图未示)，铜层312可例如电镀铜层(electroplated copper layer)。铜柱凸块310a、310b的详细结构将在下文讨论。
根据此实施例，如图2所示，铜柱凸块310a、310b的俯视形状为椭圆形(oval-shaped)。根据此实施例，铜柱凸块310a、310b中的至少一个的俯视形状呈现圆滑且稍微延伸(elongate)的外观，并沿着细微导线延伸。根据此具体实施例，至少一个铜柱凸块(例如铜柱凸块310b)的凸块宽度Wb小于或等于位于封装基板20上的导线(例如导线210b)线宽W。根据本发明的一个实施例，至少一个铜柱凸块(例如铜柱凸块310b)的凸块长度Lb可至少两倍长于导线线宽W。举例来说，铜柱凸块310a、310b中的至少一个可具有凸块宽度Wb以及凸块长度Lb。其中凸块宽度Wb数值介于10μm至40μm之间，例如25μm。凸块长度Lb数值介于40μm至80μm之间，例如60μm。根据本发明的实施例，芯片30的凸块间距介于120μm至180μm之间，例如150μm。
请参考图3，铜柱凸块310a、310b各别对应至芯片安置面20a上的导线210a、210b。在倒装芯片组装的过程中，举例来说，铜柱凸块310a、310b会分别连接至导线210a、210b。因为铜柱凸块310a、310b具有较小的尺寸，因此可以降低产生的应力(stress)、增加凸块至导线的间距并且有效避免凸块至导线的桥接(bridging)。进一步来说，也能获得更多的布线空间。经过回焊过程后，可填充底充胶材料或底充胶40至芯片30与封装基板20之间，此空间具有较高的间隙高度H。较高的间隙高度H意味着有利于填胶的程序。根据此较佳实施例，底充胶40可以是毛细型底充胶(capillary underfill，CUF)、模塑型底充胶(moldedunderfill，MUF)或上述组合。
图4是根据本发明一个较佳实施例的铜柱凸块310的结构剖面示意图，且此铜柱凸块位于芯片有效面上。其中，铜柱凸块的剖面图为沿着铜柱凸块的纵长(lengthwise)方向。如图4所示，芯片30可包括基底(base)320、第一钝化层(passivation layer)322、最上层金属层(topmost metal layer)323、第二钝化层324以及应力缓冲层(stress buffering layer)326。其中，该第一钝化层322位于基底320上，该最上层金属层(topmost metal layer)323位于第一钝化层322上，该第二钝化层324位于最上层金属层323以及第一钝化层322上，以及该应力缓冲层(stress buffering layer)326位于第二钝化层324之上。在此所述的「位于…上」表示于空间中「上面」的意思。根据此较佳实施例，基底320可包括半导体基板、设置于半导机基板主要面(main surface)的电路元件、层间介电层(inter-layerdielectric，ILD)以及内连线。第一钝化层322可为氮化硅(silicon nitride)、氧化硅(silicon oxide)、氧氮化硅(silicon oxynitride)或上述的组合。第二钝化层324可为氮化硅、氧化硅、氧氮化硅或上述的组合。应力缓冲层326可为聚亚酰胺(polyimide)、聚苯并恶唑(polybenzoazole，PBO)或上述的组合。最上层金属层323可为铝、铜或两者的合金。其中，应力缓冲层326也可包括第二钝化层324。
开孔326a可形成于应力缓冲层326内，以露出至少一部分的最上层金属层323。且开孔326a可以呈现任何形状。根据本发明的实施例，应力缓冲层326可以是呈现细长状、椭圆形的开孔，沿着铜柱凸块的纵长方向延伸。UBM层311可形成于露出于开孔326a内的最上层金属层323之上。UBM层311也可以向外延伸至应力缓冲层326上表面。根据本实施例，UBM层311可由溅镀的方法形成，且其成分可为钛(titanium)、铜或其结合。举例而言，UBM层311可包括钛层以及铜层，其中，该钛层厚度介于500埃(angstroms)至1500埃之间，例如1000埃，该铜层厚度介于3000埃至5000埃之间，例如5000埃。铜层312(例如电镀铜层)可形成于UBM层311之上。根据本实施例，该铜层312的厚度介于30μm至60μm之间，例如45μm。铜层312及UBM层311可填入应力缓冲层326，并且位于应力缓冲层326内的铜层312及UBM层311可形成整体塞棒(integral plug)312a，以使铜柱凸块310电耦合于其下的最上层金属层323。焊锡盖层314的厚度介于10μm至40μm之间，例如25μm，且焊锡盖层314可形成于铜层312之上。镍层313的厚度介于1μm至5μm之间，例如3μm，且镍层可形成于铜层312以及焊锡盖314之间。铜层(例如铜层312)可以是部分的再分配层(re-distribution layer，RDL)或是与RDL一同形成。
图5是根据本发明另一个较佳实施例的位于芯片有效面上的铜柱凸块310a的结构剖面示意图。同样地，铜柱凸块的剖面图系沿着铜柱凸块的纵长方向所绘示。如图5所示，芯片30a可包括基底320、第一钝化层322、最上层金属层323、第二钝化层324以及应力缓冲层326。其中，该第一钝化层322位于基底320上，该最上层金属层323位于第一钝化层322上，该第二钝化层324位于最上层金属层323以及第一钝化层322上，以及该应力缓冲层326位于第二钝化层324上。根据此较佳实施例，基底320可包括半导体基板、设置于半导机基板主要面的电路元件、层间介电层以及内连线。两个开孔326b、326c可形成于应力缓冲层326内，以露出部分最上层金属层323。开孔326b、326c可以呈现任何形状。UBM层311可形成于露出于开孔326b、326c的最上层金属层323之上。UBM层311可填入开孔326b、326c，且UBM层311可向外延伸至应力缓冲层326的上表面。根据本实施例，UBM层311可由溅镀方法形成，且其成分可为钛、铜或其结合。UBM层311可包括钛层以及铜层，其中，该钛层厚度介于500埃至1500埃，例如1000埃，以及该铜层厚度介于3000埃至7000埃，例如5000埃。铜层312(例如电镀铜层)可形成于UBM层311之上。至少位于开孔326b、326c内的UBM层311可形成双整体塞棒(dual integral plug)312b、312c，以使铜柱凸块310a电耦合于其下的最上层金属层323。焊锡盖层314可形成于铜层312之上。镍层313可形成于铜层312以及焊锡盖层314之间。
本发明的另一项特征是凸块长轴走向(orientation)。图6是根据本发明另一个较佳实施例的位于芯片有效面上的铜柱凸块310b的结构俯视示意图。而图7是沿着图6II-II’切线的铜柱凸块剖面示意图，其中相同的元件符号代表类似的区域、层或元件。为了使本发明清晰易懂，图6仅显示部分芯片角落区域，且仅显示一个凸块。如图6所示，铜柱凸块310b的俯视形状为椭圆形，呈现圆滑且稍微延长的外观，并沿着铜柱凸块的纵长方向延伸。在本实施例中，铜柱凸块310b的纵长方向，即凸块310b的长轴走向，为指向芯片30b的中心。根据此实施例，铜柱凸块310b沿着凸块纵长方向具有不对称塞棒结构(asymmetricplug configuration)。更精确地，整体塞棒312c设置于低应力区(lower stress side)，此低应力区由箭头所标示，然而，在远离芯片中心的高应力区则并未设置有任何塞棒。
图7是设置于芯片30b上的铜柱凸块310b的不对称塞棒结构的结构剖面示意图。如图7所示，同样地，芯片30b可包括基底320、第一钝化层322、最上层金属层323、第二钝化层324以及应力缓冲层326。其中，该第一钝化层322位于基底320上，该最上层金属层323位于第一钝化层322上，该第二钝化层324位于最上层金属层323以及第一钝化层322上，以及该应力缓冲层326位于第二钝化层324上。根据此较佳实施例，基底320可包括半导体基板、设置于半导机基板主要面的电路元件、层间介电层以及内连线。开孔326c形成于应力缓冲层326内的低应力区，亦即形成于较靠近芯片中心的区域，以露出部分最上层金属层323。开孔326c可呈现任何形状。UBM层311可形成于露出于开孔326c内的最上层金属层323之上。且UBM层311可填入开孔326c，且UBM层311可向外延伸至应力缓冲层326的上表面。根据本实施例，UBM层311可由溅镀方法形成，且其成分可为钛、铜或其结合。UBM层311可包括钛层以及铜层，其中该钛层厚度介于500埃至1500埃，例如1000埃，以及该铜层厚度介于3000埃至7000埃，例如5000埃。铜层312(例如电镀铜层)可形成于UBM层311之上。至少位于开孔326c内的UBM层311可形成整体塞棒312c，以使铜柱凸块310b电耦合于其下的最上层金属层323。焊锡盖层314可形成于铜层312之上。而镍层313可形成于铜层312以及焊锡盖层314之间。由于在高应力区的应力缓冲层326，亦即远离芯片中心区域的完整性(integrity)，其并未被塞棒和通路孔(via opening)破坏，因此位于基底320内的低介电常数(extra-low k，ELK)介电层或超低介电常数(ultra-low k，ULK)介电层能有效的抵挡住制程的应力，例如，热膨胀(thermal expansion)或薄片弯曲(wafer warpage)所产生的应力。图6及图7的凸块长轴走向的另一优点在于，可由此凸块长轴走向而获得较佳的布线能力。在此长轴走向配置下，两邻近凸块的间距可得以增加，因此可于基板中容纳更多导线。
以上所述仅为本发明的较佳实施例，凡依本发明权利要求所做的均等变化与修饰，皆应属本发明的涵盖范围。

Claims (20)

1.一种覆晶封装结构，包括：
基板，具有芯片安置面；以及
芯片，设于该芯片安置面上，该芯片具有朝向该基板的有效面，其中该芯片为透过多个铜柱凸块内连线至该基板，其中该多个铜柱凸块位于该有效面上，且该多个铜柱凸块中的至少一个的凸块宽度小于或等于导线的线宽，其中该导线位于该基板的该芯片安置面上。
2.如权利要求1所述的覆晶封装结构，其特征在于，该多个铜柱凸块中的至少一个的凸块长度为该导线的该线宽的两倍以上。
3.如权利要求1所述的覆晶封装结构，其特征在于，该多个铜柱凸块中的至少一个其俯视形状为椭圆形。
4.如权利要求1所述的覆晶封装结构，其特征在于，该多个铜柱凸块中的至少一个是由金属层叠结构所组成，且该金属层叠结构包括凸块下金属层、铜层以及焊锡盖。
5.如权利要求4所述的覆晶封装结构，其特征在于，该铜层的厚度介于30μm至60μm之间。
6.如权利要求4所述的覆晶封装结构，其特征在于，该焊锡盖的厚度介于10μm至40μm之间。
7.如权利要求4所述的覆晶封装结构，其特征在于，该多个铜柱凸块中的至少一个另包括镍层，该镍层位于该铜层与该焊锡盖之间。
8.如权利要求1所述的覆晶封装结构，其特征在于，该导线的该线宽介于10μm至40μm之间。
9.如权利要求1所述的覆晶封装结构，其特征在于，该芯片的凸块间距介于120μm至180μm之间。
10.如权利要求1所述的覆晶封装结构，其特征在于，该多个铜柱凸块中的至少一个的凸块宽度介于10μm至40μm之间，而其凸块长度介于40μm至80μm之间。
11.如权利要求1所述的覆晶封装结构，其特征在于，该多个铜柱凸块中的至少一个的凸块长轴走向为指向该芯片的中心。
12.如权利要求1所述的覆晶封装结构，其特征在于，另包括底充胶，该底充胶位于该芯片与该基板之间。
13.如权利要求12所述的覆晶封装结构，其特征在于，该底充胶为毛细型底充胶、模塑型底充胶或上述的组合。
14.一种半导体芯片，包括：
基底；
最上层金属层，位于该基底上；
应力缓冲层，设于该最上层金属层上，其中该应力缓冲层具有开孔，以显露出至少一部分的该最上层金属层；以及
铜柱凸块，通过该开孔耦接该最上层金属层；
其中，该半导体芯片用于设于基板的芯片安置面上，该半导体芯片透过该铜柱凸块内连线至该基板，其中，且该铜柱凸块的凸块宽度小于或等于导线的线宽，其中该导线位于该基板的芯片安置面上。
15.如权利要求14所述的半导体芯片，其特征在于，该铜柱凸块其俯视形状为椭圆形。
16.如权利要求14所述的半导体芯片，其特征在于，该铜柱凸块是由金属层叠结构所组成，且该金属层叠结构包括凸块下金属层、铜层以及焊锡盖。
17.如权利要求16所述的半导体芯片，其特征在于，该铜层的厚度介于30μm至60μm之间。
18.如权利要求16所述的半导体芯片，其特征在于，该焊锡盖的厚度介于10μm至40μm之间。
19.如权利要求14所述的半导体芯片，其特征在于，该铜柱凸块的凸块宽度介于10μm至40μm之间，该铜柱凸块的凸块长度介于40μm至80μm之间。
20.如权利要求14所述的半导体芯片，其特征在于，该铜柱凸块其凸块长轴走向为指向该半导体芯片的中心。
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US20200294948A1 (en) 2020-09-17
TWI429032B (zh) 2014-03-01
US11121108B2 (en) 2021-09-14
CN102376668A (zh) 2012-03-14
US20130140694A1 (en) 2013-06-06
US20120032343A1 (en) 2012-02-09
TW201208005A (en) 2012-02-16
TW201212175A (en) 2012-03-16
US8390119B2 (en) 2013-03-05
CN102376681A (zh) 2012-03-14
US20120032322A1 (en) 2012-02-09
US20190295980A1 (en) 2019-09-26
US10707183B2 (en) 2020-07-07
US10354970B2 (en) 2019-07-16
US8502377B2 (en) 2013-08-06
TWI442524B (zh) 2014-06-21

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