TW200414460A - Method for fabricating a chip package - Google Patents

Abstract

A method for fabricating a chip package is to provide at least one chip having an active surface and a back surface thereon and a substrate having a support surface. To couple the active surface of the chip to the support surface of the substrate by the mean of flip chip attachment. Completely forming a compound on the support surface of the substrate and the compound even covers the back surface of the chip, then grinding the far portion of the compound opposite to the substrate until the back surface of the chip is exposed. The heat derives from the chip can be dissipated more quickly due to no compound covered the back surface of the chip. It also improves the heat dissipation of the chip package with a thermal conductive tape attached on the back surface of the chip and the surface of the compound.

Description

200414460

[Technical field to which the invention belongs] The present invention relates to a chip packaging process, and more particularly, to a chip packaging process applied to a flip-chip bonding type. [Previous technology] Flip Chip Interconnect Technology (FC) is an area array method in which multiple die pads are arranged on the active surface of a die. ), And bumps are formed on the wafer pad, and then the wafer is flipped (f 丨 ip), and then these bumps are used to electrically and mechanically connect the wafer pad of the wafer to the carrier. Contact (contact), so that the chip can be electrically connected to the carrier through the bump, and electrically connected to the external electronic device through the internal circuit of the carrier. It is worth noting that because the flip-chip bonding technology (FC) is applicable to jjigh pin count chip packaging structure 'and has many advantages such as reducing the chip packaging area and shortening the signal transmission path, so flip-chip Bonding technology has been widely used in the field of chip packaging. Flip Chip BaU GHd Array (FC / BGA) and flip-chip pin array array (FUp) Chip pin Grid Array 'FC / PGA) and other types of chip packaging structures. Figs. 1A to 1D are schematic cross-sectional views showing the conventional four kinds of wafer-on-ball array array-type wafer packaging structures. Please refer to FIG. 1A first. The chip package structure 100 includes a substrate 110, a plurality of bumps 120, a chip 130, and a plurality of solder balls 14. The substrate has a top surface 112 and an opposite surface.

200414460 V. Description of the invention (2) One of the bottom surfaces 1 1 4 and the substrate 1 1 0 further has a plurality of bump pads 1 1 6 a and a plurality of solder ball pads (ba 1 1 pad) 1 1 6 b. In addition, the chip 130 has an active surface 132 and a corresponding back surface 134 '. The active surface 132 of the chip 130 refers to the side of the chip 13 with an active device (not shown). Moreover, the wafer 130 further has a plurality of wafer pads 136 ′, which are arranged on the active surface 1 3 2 ′ of the wafer 130 and are used as electrical contacts for the signal input and output of the wafer 130. These bump pads 1 1 6 a The positions correspond to the positions of these wafer pads 1 3 6 respectively. In addition, the bumps 120 are electrically and mechanically connected to one of the wafers 136 and one of the bump pads 116 & respectively. In addition, the solder balls 140 are respectively disposed on these solder ball pads 16b, and are used to electrically and mechanically connect to external electronic devices. Please also refer to FIG. 1A, the underfill 150 is filled on the top surface I of the substrate ho in a filling manner? The space enclosed by the bump i20 and the active surface 132 of the wafer 130 is used to protect the exposed portions of the bump pad 116a, the wafer pad 136, and the bump 120, and buffering between the substrate 110 and the wafer 130 Produced when temperature changes

StreSS). The wafer 塾 1 3 6 due to the crystal 00 will be able to be electrically and mechanically connected to the bump 塾 1Ua through the bump 1 2 0, and then pass through the substrate U. Inside = f will;) solder balls 塾 丨 丨 "connected to the bottom surface 114 of the substrate 110, and finally electrically and mechanically connected to the outside through the solder balls 1 40 on the solder ball pad 1 1 6b

Home. | i A Please refer to Figure 1B. It is worth noting that the chip package structure ι〇2

10371twf.ptd Page 7 200414460 V. In the description of the invention (3), the mold undermolded (molded underf i 1 1) 152 completely covers the top surface 1 1 2 of the substrate 1 1 2 and the wafer 1 3 by injection molding. The back surface of 0 is 1 3 4 and part of the sealant 1 5 2 is filled in the space enclosed by the top surface of the substrate 1 1 0 1 2, the bumps 1 2 0 and the active surface 1 2 of the wafer 1 3 0, Used to protect the chip 130 from external forces. Since the material of the sealing compound 1 2 is a high molecular polymer, such as epoxy resin, it can protect the chip 130 after curing to prevent external moisture from entering the chip packaging structure 1 02 However, it is worth noting that although the material of the sealant 1 52 is usually a high thermal conductivity polymer, the thermal conductivity of the sealant 1 5 2 is still relatively poor compared to metal materials. Therefore, 'when the part of the sealant 1 5 2 thicker on the back surface 1 3 4 of the wafer 130 is thicker', the thermal resistance between the back surface 1 3 4 of the wafer 130 and the outer surface of the chip packaging structure 102 is relatively increased. In contrast, the thermal energy generated by the wafer during operation will be more difficult to dissipate to the external environment. Therefore, the thickness of the sealant 152 on the back surface 134 of the wafer 130 should be as small as possible. As a result, the thermal resistance generated by the sealant 152 is reduced. However, in order to prevent the wafer / 30 from being damaged during the sealing process, and the manufacturing molds and manufacturing processes are both a certain length, the sealing glue π on the back surface 134 of the wafer 130 is reserved to a safe thickness. In, main = Figure. In the chip package structure 104, the sealing method of the H-die is completely covered on the top surface U2a of the substrate 110a, and part of the seal * Z is inserted on the top surface 112 of the substrate U °. The space formed by the plurality of bumps 120 and the wafer is used to protect the wafer 130 from external forces. However, in order to reduce the thermal resistance of the wafer j 3 〇 photo taken from the main two · Moon 134 and Japanese-Japanese film coat, ~ structure 204 outside the surface, it is common practice to mold (not shown)

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(Shown) close to the backside of the wafer 130 and 34, and filling the uncured sealant 1 5 2 into the mold so that the sealant 1 5 2 does not remain on the backside 1 34 of the wafer 130, and then After the sealant 1 5 2 is cured, the mold is removed at this time to complete the production of the sealant 1 5 2. It is worth noting that, due to the fragile texture of the wafer 丨 3 0 itself, when the mold abuts on the back of the wafer 3 0 3 4, ^ the force of the mold against the wafer 1 3 0 is not properly controlled, This will cause the mold to crush the wafer 130, or cause the sealant 152 to fill the gap between the mold and the back surface 134 of the wafer 130. Please refer to FIG. 1D. In the chip package structure 106, in order to prevent the mold from directly abutting on the back surface 134 of the chip 130, a conventional technique is to attach a thermal conductive tape on the surface 134 of the chip 130. tape) 1 6 0, so that the mold can indirectly pass the heat-dissipating tape 丨 60, and abut against the back surface 1 34 of the wafer 130, so the uncured sealant 1 52 will not fill the mold and the wafer 1 3 0 The gap between the back 1 3 4. It is worth noting that although the thermal conductivity of the heat sink tape 1 60 is greater than the thermal conductivity of the sealant 15 2, compared to metal, the heat sink tape 1 60 will still generate thermal resistance to some extent and increase manufacturing cost. SUMMARY OF THE INVENTION Therefore, an object of the present invention is to provide a chip packaging process for reducing thermal resistance between a back surface of a chip and a surface of a package. In order to achieve the above-mentioned object of the present invention, the present invention proposes a wafer packaging process' firstly provides at least one wafer and a substrate, and the wafer has an active surface and a corresponding back surface, and the substrate has a bearing surface; Method, connecting the active surface of the wafer to the bearing surface of the substrate;

Page 9 l0371twf.ptd 200414460 V. Description of the invention (5) Then fully expose the crystal on the back of the wafer to achieve this process. First, the active surface and the load-bearing surface of the flip-chip bonding board are raised, and the rubber sheet is sealed. Part of these crystals, more than one of these crystals, so that, in order to remove can easily completely dissipate to the outside to remove the thickness of the chip, in order to make this obvious, the following detailed description is as follows [implementation please refer to the chip package Form one side; the most backside invention provides a plurality of corresponding ways; then cover it until the chip is packaged. The present invention is located on the back of the wafer exposed in a sealed environment and further thinly invents the encapsulation adhesive on the rear grinding surface and the above-mentioned wafer and a back surface, which is comprehensive in these fully exposed structures. outer. The above-mentioned internalized wafer is described above and a preferred figure 2A ~ 2E, the process flow chart of the substrate carrying surface, and the sealant covers the portion of the sealant away from the substrate. Until the end, the present invention proposes a chip package Make a substrate, and these wafers have one each, and the substrate has a bearing surface; then the active surfaces of the wafers are connected to the substrate to form a glue on the substrate to carry the back surface of the wafer; the sealant is ground away from the substrate. Up to the back of the chip, each of the packages can contain one or a feature of the packaging process. The part is sealed by grinding, so the back of the chip can make the heat generated by the chip fast. By grinding, in addition to the separable sealant, the overall thickness of the crystal packaging structure can be further thinned. Other objects, features, and advantages can make the embodiment clearer, and in conjunction with the accompanying drawings, it is shown in detail to illustrate one of the preferred embodiments of the present invention. As shown in Figure 2A, first provide multiple

10371twf, ptd p. 10 200414460

Wafer 2 3 0 (only the second one is shown) and a substrate 2 i 0. Wafer 2 30 has an active surface 23 2 and a corresponding back surface 234, and wafer 23 0 is a flip-chip bonding method. The active surface 232 is connected to the carrying surface 2 1 2 of the substrate 210. At the time of flip-chip bonding, the wafer 230 can be connected to the substrate 21 via a plurality of bumps 220, and then the bumps 220 are re-soldered (ref 10 w). The purpose of the re-soldering is to When the connection between the bump 22 and the substrate 21 is raised, and a bump 2 220 is formed, a flux (f lux) is usually added so that when the bump 22 and the substrate 21 are bonded, The oxide and impurities on the surface of the bump 22 0 can be precipitated by the flux, so that the adhesion between the bump 22 0 and the substrate 210 can be improved. Then, the flux (heart) is removed, and the manner of removing the flux is, for example, cleaning with a solvent, and after removing the flux, the plasma bearing (pl asma) can be used to clean the bearing surface of the substrate 21 212, wafer 230, and the surfaces exposed by these bumps 22 0, respectively, are used to remove the flux and 2 1 remaining on the bearing surface 21 2 of the substrate 2

Reference is made to FIG. 2B, and then a sealant 250 is formed on the substrate 21 °, a carrier surface 212, and a sealant 250 covers the back surface 2 of the wafer 23 °. The idea is that since the sealant 25 is formed on the substrate 1 by injection molding, the uncured sealant 25 must be injected into the mold (not shown) to cover the entire surface. The bearing surface 212 of the substrate 210, and the uncured part of the sealant 250 covers the back surface 234 of the wafer 230, and the uncured part of the sealant 250 will be filled in the wafer 23G, the substrate 21 () and the bump 22. 20% of the space is used to protect the wafer 230 from external forces. It is worth noting that before a comprehensive gel is formed,

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The sealant 2 5 0 cannot be fully filled in the space formed by the wafer 2 3 0, the substrate 2 0, and the bumps 220 to generate voids (or bubbles). Here, the primer 25 2 ( (As shown by the dotted line) in the space formed by the wafer 23 0, the substrate 210 and the bumps 2 2 0, and finally forming a sealant 2 5 0 on the periphery of the primer 2 5 2.

Next, please refer to FIG. 2C, the portion of the sealant 250 away from the substrate 210 'is completely exposed until the back surface 2 3 4 of the wafer 2 3 0 is completely exposed. The required flatness of the polished surface here does not need to be very high, and the error may be Reach about 3 m 丨 1. In this way, the sealant 2 50 does not remain on the back surface 234 of the wafer 230, so the thermal resistance value generated by the sealant 2 50 above the back surface 234 of the wafer 230 can be reduced. On the other hand, when the back surface 234 of the wafer 230 is ground, the back surface 2 3 4 of the wafer 230 and the surface of the sealant 250 are simultaneously ground to achieve the effect of thinning the wafer packaging structure 200. Please refer to FIG. 2D ′. A heat sink 260 can be attached to the back surface 2 3 4 of the chip 230 and the surface of the sealant 2 50 to improve the heat dissipation performance of the chip package structure 2000. Then, the ink or laser can be used to mark on the top surface of the chip packaging structure 2000, and the solder ball 240 or other types of contacts can be selectively connected to the bottom surface 214 of the substrate 21 .

Finally, please refer to FIG. 2E, the singuia chip 230 and the package structure described above are used to form a single chip package structure 200. It is worth noting that since the material of the heat sink 260 is metal or a harder material, it is also possible to attach a plurality of heat sinks 2 60 separately after the wafer 2 3 0 and the packaging structure described earlier. To the top surface of the chip packaging structure 2000, that is, the side of the sealing compound 2 50 that is farther away from the substrate 2 10 and the back surface of the chip 230

10371twf.ptd Page 12 200414460 V. Description of the invention (8) 2 34 ° In summary, the wafer packaging process of the present invention is to comprehensively form a piece of glue on the bearing surface of the substrate, and part of the glue is more covered. On the back of the wafer, and then grind the part of the sealant away from the substrate until the back of the wafer is completely exposed. Therefore, the wafer packaging process of the present invention has the following advantages: (1) As far as the wafer packaging process of the present invention is concerned, since the sealant is not covered on the back surface of the wafer, the back surface of the wafer and the outer surface of the chip packaging structure can be greatly reduced. Thermal resistance, the thermal energy generated by the chip can be quickly dissipated to the external environment. (2) As far as the wafer packaging process of the present invention is concerned, in addition to using a grinding method to remove part of the sealant located on the back of the wafer, the backside and sealant of the wafer can be further ground to achieve a thinner chip package structure. The effect. In addition, if the thickness of each wafer is different, the thickness can be made uniform by the grinding step, and the effect of thinning the entire chip packaging structure can also be achieved. (3) As far as the chip packaging process of the present invention is concerned, a heat sink can be attached to the back surface of the chip and the surface of the sealing compound to improve the heat dissipation performance of the chip packaging structure. (4) As far as the wafer packaging process of the present invention is concerned, the wafer packaging process of the present invention can also be applied to a multi-chip module (M u 11 i-C hi ρ Μ DU 1 e, MCM) or a system single package (System In-package (SIP) and other chip packaging structures make the signal transmission path between each chip of the multi-chip module shorter, so it can improve the electrical performance of the multi-chip module after packaging.

10371twf.ptd Page 13 200414460 V. Description of the Invention (9) Although the present invention has been disclosed as above with a preferred embodiment, it is not intended to limit the present invention. Any person skilled in the art will not depart from the spirit of the present invention and Within the scope, some modifications and retouching can be made, so the protection scope of the present invention shall be determined by the scope of the appended patent application. #

10371twf.ptd Page 14 200414460 Schematic illustrations 1A to 1D are schematic cross-sectional diagrams of four conventional flip chip ball grid array chip packaging structures; and FIGS. 2A to 2E show comparisons of the present invention. A schematic flowchart of a chip packaging process according to a preferred embodiment. Description of the diagram] 1 0 6 · Wafer package structure # 100, 102, 1 04 1 1 0: substrate 1 1 2: top surface 1 1 4: bottom surface 1 1 6a: bump pad 1 1 6b: solder ball pad 1 2 0: Bump 1 3 0 · Wafer 1 3 2: Active surface 1 3 4: Back surface 1 4 0: Solder ball 1 5 0: Primer 1 5 2: Sealant 1 6 0 · Thermally conductive patch 2 0 0 : Chip package structure 210: Substrate 2 1 2: Bearing surface 2 1 4: Bottom surface

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Claims (1)

200414460 VI. Scope of patent application '___ 1 · A chip packaging process, including the following steps: (a) Provide at least one wafer and a substrate, the active surface in # and a corresponding back surface, and the substrate has a load meter, a (b) connecting the main and the wafers to the bearing surface of the substrate by flip chip bonding; the cut surface is connected with (c) to form a glue on the substrate to cover the sealing material more completely On the back surface of the wafer; and the surface, and (d) grinding the part of the sealant away from the substrate until the back surface of the wafer is exposed. Yuan Wang Bao 2. The chip packaging process described in item 丨 of the scope of patent application includes attaching a heat sink to the surface of the sealant and the package of the chip 3. If the scope of patent application is the first! The wafer package described in item 1. At step (c), the process of forming the sealant includes: forming a two-step sealant on the bearing surface of the substrate, and uncured sealant; and the far side of the wafer is the surface, and then cured. The sealant. Set the edge at 4. The process of chip packaging as described in item 丨 of the scope of the patent application (time b). The process of connecting the chip to the board in a flip-chip bonding method includes: passing the chip through a plurality of After the bumps are connected to A ', the bottom-filler is then filled in the space formed by the crystal #, the substrate, and the plate. Λ Two bumps constitute 5 · As mentioned in the above, the wafer is sealed as described in item 4 of the patent scope. At the same time, the process of forming the sealant includes: shape: step sealant on the bearing surface of the substrate, "cured the dagger, the edge of the wafer is the surface, and then cure the sealant. Set now at 200414460 6. Application for Patent Scope 6 · A kind of wafer packaging process, including the following steps: (a) providing a plurality of wafers and a substrate, wherein the wafers each have an active surface and a corresponding back surface, and the substrate has a bearing Surface; (b) connecting the active surfaces of the wafers to the carrying surface of the substrate in a flip-chip bonding manner; (c) forming a comprehensive adhesive on the carrying surface of the substrate, and the sealing The glue covers the back surface of the wafers; (d) grinding the portion of the sealant away from the substrate until the back surface of the wafers is completely exposed; and (e) the packaging structure of the wafers is singulated . 7. According to the chip packaging process described in item 6 of the patent application scope, after step (d) and before step (e), the method further includes attaching a heat sink to the surface of the sealant and the wafers. back. 8. According to the wafer packaging process described in the sixth item of the patent application scope, at the step (c), the process of forming the sealant includes forming an uncured sealant on the bearing surface of the substrate, and The cured sealant covers the back of the wafers, and then the sealant is cured. 9. According to the chip packaging process described in item 6 of the patent application scope, at step (b), the process of connecting the wafers to the substrate by flip-chip bonding includes: passing the wafers through a plurality of After the bumps are connected to the substrate, a primer is filled in the space formed by the wafers, the substrate and the bumps. 10. The chip packaging process described in item 9 of the scope of patent application, in step 10371twf.ptd Page 18 200414460 10371twf.ptd Page 19