CN115312406A - Chip packaging structure and preparation method - Google Patents
Chip packaging structure and preparation method Download PDFInfo
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- CN115312406A CN115312406A CN202211195764.1A CN202211195764A CN115312406A CN 115312406 A CN115312406 A CN 115312406A CN 202211195764 A CN202211195764 A CN 202211195764A CN 115312406 A CN115312406 A CN 115312406A
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Images
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
- H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
- H01L21/568—Temporary substrate used as encapsulation process aid
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
- H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
- H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
- H01L23/36—Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks
- H01L23/367—Cooling facilitated by shape of device
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
- H01L23/36—Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks
- H01L23/367—Cooling facilitated by shape of device
- H01L23/3672—Foil-like cooling fins or heat sinks
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
- H01L23/36—Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks
- H01L23/367—Cooling facilitated by shape of device
- H01L23/3675—Cooling facilitated by shape of device characterised by the shape of the housing
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
- H01L23/36—Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks
- H01L23/373—Cooling facilitated by selection of materials for the device or materials for thermal expansion adaptation, e.g. carbon
- H01L23/3736—Metallic materials
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- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Chemical & Material Sciences (AREA)
- Materials Engineering (AREA)
- Manufacturing & Machinery (AREA)
- Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
Abstract
The chip packaging structure and the preparation method thereof of the invention, the chip packaging structure comprises: a substrate; rewiring layers; a chip; a plastic packaging layer; the groove is positioned in the plastic packaging layer and exposes the chip; the liquid heat-conducting metal is filled in the groove; and the heat dissipation cover plate is fixedly connected with the substrate and forms a sealing structure with the groove. The groove for exposing the chip is formed on the plastic packaging layer, and the liquid heat-conducting metal with high heat conductivity coefficient is introduced into the groove, so that the liquid heat-conducting metal is in direct contact with the chip to serve as a heat diffusion material, the liquid heat-conducting metal can be prevented from overflowing in the packaging process, the heat dissipation performance of the chip can be improved, the probability of electrical performance reduction of the packaging structure is reduced, the packaging thermal resistance can be effectively reduced, the heat diffusion efficiency in the packaging process is greatly improved, and the chip packaging structure with good heat dissipation performance is formed.
Description
Technical Field
The invention relates to the field of semiconductor packaging, in particular to a chip packaging structure and a preparation method thereof.
Background
The semiconductor Integrated Circuit (IC) industry has rapidly developed, and a Package (Package) as a critical part of the IC fabrication has an important influence on the performance and performance of the chip itself, and not only plays a role in mounting, fixing, sealing, protecting the chip and enhancing the electrothermal performance, but also plays a role in electrically connecting the bonding point in the IC chip with the outside.
With the continuous development of advanced packaging technology, the power of high-end servers is continuously increased, and GPUs are even increased to over 1000W, which is particularly important for heat dissipation of chips in the current situation. The conventional heat dissipation technology is to stick a heat dissipation cover plate on the chip or fill silicone grease and other common heat conducting agents to dissipate heat generated by the chip to the outside, and the heat conductivity of the silicone grease is low, so that the heat dissipation effect of the package structure is poor.
Disclosure of Invention
In view of the above drawbacks of the prior art, an object of the present invention is to provide a chip package structure and a method for manufacturing the same, which are used to solve the problem of performance degradation of the package structure due to poor heat dissipation effect of the semiconductor package structure in the prior art.
In order to achieve the above object, the present invention provides a method for manufacturing a chip package structure, including the steps of:
providing a first temporary slide, and forming a release layer on the first temporary slide;
forming a rewiring layer on the release layer, wherein the rewiring layer comprises a first surface and an opposite second surface connected with the release layer, and the rewiring layer comprises a dielectric layer and a laminated metal wiring layer;
bonding a chip on the first surface of the rewiring layer, the chip being electrically connected to the rewiring layer;
forming a plastic packaging layer on the rewiring layer, wherein the plastic packaging layer covers the rewiring layer and the chip;
forming an adhesive layer and a second temporary carrier on the plastic packaging layer;
removing the first temporary slide and the release layer, and exposing the second surface of the rewiring layer;
forming a solder bump on a second surface of the rewiring layer, the solder bump being electrically connected to the rewiring layer;
providing a substrate, wherein the rewiring layer is electrically connected with the substrate through the solder bumps;
removing the bonding layer and the second temporary carrier and forming a groove in the plastic packaging layer, wherein the groove exposes the chip;
filling liquid heat-conducting metal in the groove;
and forming a heat dissipation cover plate on the substrate and sealing the groove.
Optionally, the method of forming the groove comprises one or a combination of mechanical grooving, laser grooving, chemical etching grooving and plasma etching grooving.
Optionally, after filling the liquid heat-conducting metal and before forming the heat-dissipating cover plate, a step of forming a heat-conducting adhesive layer on the surfaces of the molding layer and the liquid heat-conducting metal is included.
Optionally, the heat conductive sealant layer covers the liquid heat conductive metal.
Optionally, the heat dissipation cover plate has a cavity therein, which is disposed corresponding to the groove.
Optionally, a heat conduction member is further formed on the first surface of the redistribution layer, and the groove exposes the heat conduction member.
Optionally, the heat conductivity coefficient of the liquid heat-conducting metal is 20W/mK-100W/mK; the liquid thermally conductive metal includes one or a combination of gallium, indium, or tin.
The invention also provides a chip packaging structure, which comprises: a substrate; the rewiring layer comprises a first surface and an opposite second surface, and the rewiring layer comprises a dielectric layer and a laminated metal wiring layer; a solder bump between the second side of the redistribution layer and the substrate, the solder bump being electrically connected to the redistribution layer and the substrate; a chip located on a first face of the rewiring layer and electrically connected to the rewiring layer; the plastic packaging layer is positioned on the first surface of the rewiring layer and covers the rewiring layer and the chip; the groove is positioned in the plastic packaging layer and exposes the chip; the liquid heat-conducting metal is filled in the groove; and the heat dissipation cover plate is fixedly connected with the substrate and seals the groove.
Optionally, a thermal conduction member is further included on the first side of the redistribution layer, and the groove exposes the thermal conduction member.
Optionally, the heat dissipation cover plate comprises one of a planar heat dissipation cover plate with a planar top surface or a finned heat dissipation cover plate with fins; and the heat dissipation cover plate is internally provided with a cavity which is correspondingly arranged with the groove.
As described above, the chip package structure and the manufacturing method of the invention have the following beneficial effects: the groove for exposing the chip is formed on the plastic packaging layer, and the liquid heat-conducting metal with high heat conductivity coefficient is introduced into the groove, so that the liquid heat-conducting metal is in direct contact with the chip to serve as a heat diffusion material, the liquid heat-conducting metal can be prevented from overflowing in the packaging process, the heat dissipation performance of the chip can be improved, the probability of electrical performance reduction of the packaging structure is reduced, the packaging thermal resistance can be effectively reduced, the heat diffusion efficiency in the packaging process is greatly improved, and the chip packaging structure with good heat dissipation performance is formed.
Drawings
Fig. 1 is a flowchart illustrating a method for manufacturing a chip package structure according to an embodiment of the invention.
Fig. 2 is a schematic cross-sectional view of a first temporary carrier and a release layer provided in an embodiment of the invention.
Fig. 3 is a schematic cross-sectional view of a rewiring layer formed according to an embodiment of the present invention.
Fig. 4 is a schematic cross-sectional view of a bonded chip provided in an embodiment of the present invention.
Fig. 5 is a schematic cross-sectional view illustrating the formation of a molding layer according to an embodiment of the present invention.
Fig. 6 is a schematic cross-sectional view of a second temporary carrier sheet and an adhesive layer formed according to an embodiment of the invention.
Fig. 7 is a schematic cross-sectional view of the embodiment of the invention showing the first temporary carrier and the release layer removed and the second side of the redistribution layer exposed.
Fig. 8 is a schematic cross-sectional view after forming a solder bump according to an embodiment of the present invention.
Fig. 9 is a schematic cross-sectional view of a bonded substrate according to an embodiment of the present invention.
Fig. 10 is a schematic cross-sectional view of the groove formed according to the embodiment of the present invention.
Fig. 11 is a schematic cross-sectional view illustrating the groove filled with liquid heat-conducting metal according to an embodiment of the invention.
Fig. 12 is a schematic cross-sectional view illustrating a heat conductive adhesive according to an embodiment of the invention.
Fig. 13 is a schematic cross-sectional view illustrating a heat dissipation cover plate according to an embodiment of the invention.
Fig. 14 is a schematic structural diagram of another chip package structure according to an embodiment of the invention.
Fig. 15 is a schematic structural diagram illustrating another chip package structure according to an embodiment of the invention.
Fig. 16 is a schematic structural diagram illustrating a cavity formed in a heat-dissipating cover plate according to an embodiment of the present invention.
Fig. 17 is a schematic structural diagram of another chip package structure according to an embodiment of the invention.
Description of the element reference numerals
101: first temporary slide, 102: release layer, 103: rewiring layer, 1031: first face, 1032: second side, 104: chip, 105: plastic sealing layer, 106: adhesive layer, 107: second temporary slide, 108: solder bump, 109: substrate, 110: groove, 111: liquid heat conductive metal, 112: connecting member, 113: heat-dissipating cover plate, 114: heat-conductive adhesive, 115: heat-conductive member, 116: fin, 117: a cavity, S1-S11: and (5) carrying out the following steps.
Detailed Description
The embodiments of the present invention are described below with reference to specific embodiments, and other advantages and effects of the present invention will be easily understood by those skilled in the art from the disclosure of the present specification. The invention is capable of other and different embodiments and of being practiced or of being carried out in various ways, and its several details are capable of modification in various respects, all without departing from the spirit and scope of the present invention.
For convenience in description, spatial relational terms such as "below," "beneath," "below," "under," "over," "upper," and the like may be used herein to describe one element or feature's relationship to another element or feature as illustrated in the figures. It will be understood that these terms of spatial relationship are intended to encompass other orientations of the device in use or operation in addition to the orientation depicted in the figures. Further, when a layer is referred to as being "between" two layers, it can be the only layer between the two layers, or one or more intervening layers may also be present.
Please refer to fig. 1 to 16. It should be noted that the drawings provided in the present embodiment are only for illustrating the basic idea of the present invention, and the drawings only show the components related to the present invention rather than being drawn according to the number, shape and size of the components in actual implementation, and the type, quantity and proportion of each component in actual implementation may be changed arbitrarily, and the layout of the components may be more complicated.
Example one
Referring to fig. 1 to 17, the present invention provides a method for manufacturing a chip package structure, including the following steps:
s1: providing a first temporary slide 101, forming a release layer 102 on the first temporary slide 101;
s2: forming a redistribution layer 103 on the release layer 102, where the redistribution layer 103 includes a first surface 1031 and an opposite second surface 1032 connected to the release layer 102, and the redistribution layer includes a dielectric layer and stacked metal routing layers;
s3: bonding a chip 104 on the first surface 1031 of the redistribution layer, wherein the chip 104 is electrically connected to the redistribution layer 103;
s4: forming a molding layer 105 on the redistribution layer 103, wherein the molding layer 105 covers the redistribution layer 103 and the chip 104;
s5: forming an adhesive layer 106 and a second temporary carrier sheet 107 on the plastic packaging layer 105;
s6: removing the first temporary carrier sheet 101 and the release layer 102, revealing a second side 1032 of the re-routing layer;
s7: forming a solder bump 108 on a second surface 1032 of the redistribution layer, the solder bump 108 being electrically connected to the redistribution layer 103;
s8: providing a substrate 109, wherein the rewiring layer 103 is electrically connected with the substrate 109 through the solder bumps 108;
s9: removing the adhesive layer 106 and the second temporary carrier sheet 107 and forming a groove 110 in the molding layer 105, wherein the groove 110 exposes the chip 104;
s10: filling a liquid heat-conducting metal 111 in the groove 110;
s11: a heat-dissipating cover plate 113 is formed on the substrate 109 and seals the groove 110.
The following further introduces the manufacturing method of the chip package structure with reference to the drawings, which is as follows:
in step S1, referring to fig. 1 and 2, a first temporary carrier 101 is provided, and a release layer 102 is formed on the first temporary carrier 101.
Optionally, the first temporary carrier 101 includes one of a glass carrier, a ceramic carrier, a metal carrier, and a polymer carrier, and may have a shape of a wafer, a panel, or any other desired shape, and a surface area suitable for supporting a subsequent package structure.
Specifically, in this embodiment, the first temporary carrier 101 is a glass carrier, the glass substrate has a low cost, and the release layer 102 is easily formed on the surface of the glass substrate, so that the difficulty of the subsequent removal process is reduced.
Optionally, the release layer 102 may comprise a polymer layer or a tape-like adhesive layer.
Specifically, the material of the release layer 102 may be selected from an adhesive tape (e.g., a die attach film or a non-conductive film, etc.) having two sides with adhesive properties, an adhesive glue made by a spin coating process, and the like; preferably, in the present embodiment, the release layer 102 is preferably a UV tape having a characteristic of easily undergoing a denaturation and peeling after UV light (ultraviolet light) irradiation; of course, in other examples, the release layer 102 may also be made of other material layers formed by a physical vapor deposition method or a chemical vapor deposition method, such as epoxy resin, silicon rubber, polyimide, and the like, and when the first temporary carrier 101 is subsequently separated, the release layer 102 may be removed by wet etching, chemical mechanical polishing, and the like.
In step S2, referring to fig. 1 and fig. 3, a redistribution layer 103 is formed on the release layer 102, where the redistribution layer 103 includes a first surface 1031 and an opposite second surface 1032 connected to the release layer 102, and the redistribution layer 103 includes a dielectric layer and stacked metal routing layers.
Alternatively, the material of the metal wiring layer may include one material or a combination of two or more materials of copper, aluminum, nickel, gold, silver, and titanium.
In step S3, please refer to fig. 1 and 4, a chip 104 is bonded on the first surface 1031 of the redistribution layer, and the chip 104 is electrically connected to the redistribution layer 103.
Alternatively, as shown in fig. 4, the chip 104 may be any conventional semiconductor chip suitable for packaging, may be a plurality of chips of the same type or different types, and may be, for example, a System On Chip (SOC) device, or may be a memory chip, such as an HBM, without limitation. In addition, based on the requirements of packaging efficiency, packaging size, and the like, a plurality of the chips 104 are generally packaged at the same time, and the number of the chips 104 is shown as 2 in the present embodiment, but the number of the chips 104 is not limited thereto, and the number of the chips 104 may be greater than or equal to 2, such as 3, 4, or more, as required. The electrical connection between the chip 104 and the redistribution layer 103 may be solder ball bumps (not shown), and the solder ball bumps may be formed on the surface of the chip 104 or on the surface of the redistribution layer 103, which is not limited herein.
As shown in fig. 14, in other embodiments, a step of forming a thermal conduction member 115 on the first surface 1031 of the redistribution layer may be further included, and the thermal conduction member 115 is preferably symmetrically distributed on two sides of the chip 104 and fixedly connected to the first surface 1031 of the redistribution layer, so as to further enhance the heat dissipation capability of the package structure through the thermal conduction member 115, wherein the thermal conduction member 115 is fixedly connected to the first surface 1031 of the redistribution layer, the connection manner is not limited to glue, and the step of forming the thermal conduction member 115 may be formed on the first surface 1031 of the redistribution layer before, after, or simultaneously with the chip 104, and is not limited herein, when the chip 104 is formed.
Optionally, the heat conducting member 115 includes one of high thermal conductive composite materials such as graphite, alumina, ceramic, thermal conductive metal particles, and the like.
In step S4, referring to fig. 1 and fig. 5, a molding compound layer 105 is formed on the redistribution layer 103, and the molding compound layer 105 covers the redistribution layer 103 and the chip 104.
Alternatively, but not limited to, a molding underfill process, an imprint molding process, a transfer molding process, a liquid encapsulation process, a vacuum lamination process, or a spin coating process may be used to form the molding layer 105 on the redistribution layer 103; preferably, in this embodiment, a molding underfill process is adopted to form the molding layer 105 on the first surface 1031 of the redistribution layer. The plastic-sealed layer 105 is formed by adopting a molding underfill process, the plastic-sealed layer 105 can smoothly and rapidly fill the gaps among the chip 104, the heat-conducting piece 115 and the rewiring layer 103, and interface delamination can be effectively avoided; and the molding bottom filling process greatly reduces the process difficulty, can be used for smaller connecting gaps and is more suitable for a stacked structure.
Alternatively, the material of the molding layer 105 may include, but is not limited to, a polymer-based material, a resin-based material, polyimide, silicone, epoxy resin, or the like.
Optionally, as shown in fig. 5, the height of the molding layer 105 is higher than the height of the chip 104.
In step S5, referring to fig. 1 and fig. 6, an adhesive layer 106 and a second temporary carrier 107 are formed on the molding layer 105.
Optionally, the preparation, material, and the like of the second temporary carrier sheet 107 and the adhesive layer 106 may refer to the formation process of the first temporary carrier sheet 101 and the release layer 102, which is not described herein again.
Specifically, the second temporary carrier sheet 107 and the adhesive layer 106 function to support the encapsulation structure and are removed in a subsequent process.
In step S6, referring to fig. 1 and 7, the first temporary carrier 101 and the release layer 102 are removed, and the second side 1032 of the redistribution layer 103 is exposed.
Optionally, a grinding process, a thinning process or a tearing process may be used to remove the first temporary carrier sheet 101 and the release layer 102, and preferably, in this embodiment, the first temporary carrier sheet 101 is removed by tearing the release layer 102.
Specifically, as shown in fig. 7, the first temporary carrier sheet 101 and the release layer 102 are removed, and the plastic-encapsulated chip 104 and the first redistribution layer 103 are removed from the first temporary carrier sheet 101 and flipped to expose the second surface 1032 of the first redistribution layer.
In step S7, referring to fig. 1 and 8, a solder bump 108 is formed on the second surface 1032 of the redistribution layer, and the solder bump 108 is electrically connected to the redistribution layer 103.
Alternatively, the material of the solder bump 108 may include at least one of copper and tin.
Specifically, the solder bumps 108 are electrically connected to the metal wiring layer in the redistribution layer 103. The specific process of forming the solder bump 108 is known to those skilled in the art and will not be described again.
In step S8, referring to fig. 1 and 9, a substrate 109 is provided, and the redistribution layer 103 is electrically connected to the substrate 109 through the solder bump 108.
Optionally, the substrate 109 comprises a wafer-level substrate.
Alternatively, the substrate 109 may include one of a silicon oxide substrate, a glass substrate, a ceramic substrate, and an organic substrate, and may have a circular shape, a square shape, or any other desired shape.
Optionally, the substrate 109 is electrically connected to the redistribution layer 103 through the solder bumps 108, and a gap between the substrate 109 and the redistribution layer 103 may be formed by a molding underfill process to form a dielectric layer (not shown) to achieve electrical isolation between adjacent solder bumps 108, thereby improving the packaging yield.
In step S9, referring to fig. 1 and fig. 10, the adhesive layer 106 and the second temporary carrier 107 are removed, and a groove 110 is formed in the molding layer 105, where the groove 110 exposes the chip 104.
Optionally, the method of forming the groove 110 includes one or a combination of mechanical grooving, laser grooving, chemical etching grooving, and plasma etching grooving.
Specifically, in this embodiment, a laser grooving process is selected to perform grooving on the molding layer 105 to form the groove 110 exposing the chip, the laser grooving process has high accuracy and controllability, and the groove 110 can be accurately formed without affecting other structures.
Alternatively, as shown in fig. 14, in other embodiments, when the heat conducting member 115 is provided, the groove 110 may also expose the heat conducting member 115, so as to further improve the heat dissipation effect.
In step S10, referring to fig. 1 and fig. 11, a liquid thermal conductive metal 111 is filled in the groove 110.
Optionally, the thermal conductivity of the liquid heat-conducting metal 111 is 20W/mK to 100W/mK; the liquid thermally conductive metal 111 includes one or a combination of gallium, indium, or tin.
Specifically, gallium, indium or tin is used as common liquid heat-conducting metal, the heat conductivity coefficient of the liquid heat-conducting metal is generally 20W/m.K-100W/m.K, the value of the heat conductivity coefficient is higher than that of conventional silicone grease with the heat conductivity coefficient of 11W/m.K, the liquid heat-conducting metal has lower contact thermal resistance and certain fluidity, and the liquid heat-conducting metal 111 can reduce the packaging thermal resistance, so that the heat diffusion efficiency in the packaging process is greatly improved, and the packaging quality is improved.
In step S11, referring to fig. 1 and 13, a heat dissipation cover 113 is formed on the substrate 109 and the groove 110 is sealed.
Optionally, as shown in fig. 12, after filling the liquid heat conductive metal 111 and before forming the heat dissipation cover plate 113, a step of forming a heat conductive adhesive layer 114 on the surfaces of the molding layer 105 and the liquid heat conductive metal 111 is included.
Optionally, the heat conductive sealant layer 114 covers the liquid heat conductive metal 111.
Optionally, as shown in fig. 14 and fig. 15, the heat dissipation cover plate 113 includes one of a planar heat dissipation cover plate with a planar top surface or a finned heat dissipation cover plate with fins 116, where the heat dissipation cover plate 113 is fixedly connected to the liquid heat-conducting metal 111 in a sealing manner so as to seal the groove 110, or a heat-conducting adhesive layer 114 is disposed above the liquid heat-conducting metal 111, and the heat dissipation cover plate 113 is fixedly connected to the liquid heat-conducting metal 111 in a sealing manner through the heat-conducting adhesive layer 114 so as to seal the groove 110.
Specifically, in this embodiment, as shown in fig. 14, the heat dissipation cover plate 113 is directly and fixedly connected to the liquid heat conducting metal 111 in a sealing manner, or, as shown in fig. 15, a heat conducting adhesive layer 114 is disposed above the liquid heat conducting metal 111, the heat dissipation cover plate 113 is fixedly connected to the liquid heat conducting metal 111 in a sealing manner through the heat conducting adhesive layer 114, and the heat conducting adhesive layer 114 may be an ultraviolet curing adhesive layer, but is not limited thereto, and other adhesive layers may also be used.
Optionally, as shown in fig. 16 and 17, the heat-dissipating cover plate 113 has a cavity 117 therein corresponding to the groove 110 to accommodate more liquid heat-conducting metal 111. When the cavity 117 is disposed in the heat-dissipating cover plate 113, at this time, an injection hole (not shown) for the liquid heat-conducting metal 111 needs to be reserved on the cover plate 113.
Optionally, the heat dissipation cover plate 113 is mechanically connected to the substrate 109 through a connection member 112, and the connection member 112 may include an adhesive glue or the like, which is not limited herein.
Example two
As shown in fig. 13, the present embodiment provides a chip package structure, including:
a substrate 109;
a rewiring layer 103, wherein the rewiring layer 103 includes a first surface 1031 and an opposite second surface 1032, and the rewiring layer 103 includes a dielectric layer and a laminated metal wiring layer;
a solder bump 108, the solder bump 108 being located between the second side 1032 of the redistribution layer and the substrate 109, and the solder bump 108 being electrically connected to the redistribution layer 103 and the substrate 109;
a chip 104, wherein the chip 104 is located on the first surface 1031 of the redistribution layer and electrically connected to the redistribution layer 103;
a molding layer 105, wherein the molding layer 105 is located on the first surface 1031 of the redistribution layer and covers the redistribution layer 103 and the chip 104;
a groove 110, wherein the groove 110 is located in the molding layer 105 and exposes the chip 104;
the liquid heat conducting metal 111 is filled in the groove 110;
and the heat radiating cover plate 113 is fixedly connected with the substrate 109 and seals the groove 110.
For the preparation of the chip package structure, reference may be made to the above preparation method, but not limited thereto, in this embodiment, the chip package structure is prepared by using the above preparation method, so as to refer to the first embodiment for the preparation of the chip package structure, the selection of materials and the like, and details are not described here.
Optionally, as shown in fig. 14 and 15, a thermal conduction member 115 is further included on the first surface 1031 of the redistribution layer, and the groove 110 exposes the thermal conduction member 115.
Alternatively, as shown in fig. 14 and 15, the heat dissipation cover plate 113 includes one of a planar heat dissipation cover plate with a planar top surface or a finned heat dissipation cover plate with fins 116; as shown in fig. 16, the heat-dissipating cover plate 113 has a cavity 117 therein, which is disposed corresponding to the groove 110.
In summary, the present invention provides a chip package structure and a manufacturing method thereof, wherein the chip package structure includes: a substrate; the rewiring layer comprises a first surface and an opposite second surface, and the rewiring layer comprises a dielectric layer and a laminated metal wiring layer; a solder bump between the second side of the redistribution layer and the substrate, the solder bump being electrically connected to the redistribution layer and the substrate; a chip located on a first face of the rewiring layer and electrically connected to the rewiring layer; the plastic packaging layer is positioned on the first surface of the rewiring layer and covers the rewiring layer and the chip; the groove is positioned in the plastic packaging layer and exposes the chip; the liquid heat-conducting metal is filled in the groove; and the heat dissipation cover plate is fixedly connected with the substrate and seals the groove. The grooves exposing the chips are formed in the plastic packaging layer, and the liquid heat-conducting metal with high heat conductivity coefficient is introduced into the grooves, so that the liquid heat-conducting metal is in direct contact with the chips to serve as a heat diffusion material, the liquid heat-conducting metal can be prevented from overflowing in the packaging process, the heat dissipation performance of the chips can be improved, the probability of electrical performance reduction of the packaging structure is reduced, the packaging thermal resistance can be effectively reduced, the heat diffusion efficiency in the packaging process is greatly improved, and the chip packaging structure with good heat dissipation performance is formed. Therefore, the invention effectively overcomes various defects in the prior art and has high industrial utilization value.
The foregoing embodiments are merely illustrative of the principles and utilities of the present invention and are not intended to limit the invention. Any person skilled in the art can modify or change the above-mentioned embodiments without departing from the spirit and scope of the present invention. Accordingly, it is intended that all equivalent modifications or changes which can be made by those skilled in the art without departing from the spirit and technical spirit of the present invention be covered by the claims of the present invention.
Claims (10)
1. The preparation method of the chip packaging structure is characterized by comprising the following steps of:
providing a first temporary slide, and forming a release layer on the first temporary slide;
forming a rewiring layer on the release layer, wherein the rewiring layer comprises a first surface and an opposite second surface connected with the release layer, and the rewiring layer comprises a dielectric layer and a laminated metal wiring layer;
bonding a chip on the first surface of the rewiring layer, the chip being electrically connected to the rewiring layer;
forming a plastic packaging layer on the rewiring layer, wherein the plastic packaging layer covers the rewiring layer and the chip;
forming an adhesive layer and a second temporary carrier on the plastic packaging layer;
removing the first temporary slide and the release layer, and exposing the second surface of the rewiring layer;
forming a solder bump on a second surface of the rewiring layer, the solder bump being electrically connected to the rewiring layer;
providing a substrate, wherein the rewiring layer is electrically connected with the substrate through the solder bumps;
removing the bonding layer and the second temporary carrier and forming a groove in the plastic packaging layer, wherein the chip is exposed out of the groove;
filling liquid heat-conducting metal in the groove;
and forming a heat dissipation cover plate on the substrate and sealing the groove.
2. The method of claim 1, wherein: the method for forming the groove comprises one or combination of mechanical grooving, laser grooving, chemical etching grooving and plasma etching grooving.
3. The method of claim 1, wherein: after the liquid heat-conducting metal is filled and before the heat-radiating cover plate is formed, a step of forming a heat-conducting adhesive layer on the surfaces of the plastic packaging layer and the liquid heat-conducting metal is included.
4. The production method according to claim 3, characterized in that: the heat conduction adhesive layer covers the liquid heat conduction metal.
5. The method of claim 1, wherein: and the heat dissipation cover plate is internally provided with a cavity which is correspondingly arranged with the groove.
6. The production method according to claim 1, characterized in that: a heat conduction member is further formed on the first surface of the rewiring layer, and the groove exposes the heat conduction member.
7. The production method according to claim 1, characterized in that: the heat conductivity coefficient of the liquid heat-conducting metal is 20W/mK-100W/mK; the liquid thermally conductive metal includes one or a combination of gallium, indium, or tin.
8. A chip package structure, the chip package structure comprising:
a substrate;
the rewiring layer comprises a first surface and an opposite second surface, and the rewiring layer comprises a dielectric layer and a laminated metal wiring layer;
a solder bump between the second side of the redistribution layer and the substrate, the solder bump being electrically connected to the redistribution layer and the substrate;
a chip located on a first face of the rewiring layer and electrically connected to the rewiring layer;
the plastic packaging layer is positioned on the first surface of the rewiring layer and covers the rewiring layer and the chip;
the groove is positioned in the plastic packaging layer and exposes the chip;
the liquid heat-conducting metal is filled in the groove;
and the heat dissipation cover plate is fixedly connected with the substrate and seals the groove.
9. The chip package structure according to claim 8, wherein: the first surface of the rewiring layer is provided with a groove, and the groove exposes the heat-conducting piece.
10. The chip package structure according to claim 8, wherein: the heat dissipation cover plate comprises one of a plane type heat dissipation cover plate with a plane top surface or a finned heat dissipation cover plate with fins; and the heat dissipation cover plate is internally provided with a cavity which is correspondingly arranged with the groove.
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| CN202211195764.1A CN115312406A (en) | 2022-09-29 | 2022-09-29 | Chip packaging structure and preparation method |
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| Application Number | Priority Date | Filing Date | Title |
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| CN202211195764.1A CN115312406A (en) | 2022-09-29 | 2022-09-29 | Chip packaging structure and preparation method |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN116685044A (en) * | 2022-12-14 | 2023-09-01 | 荣耀终端有限公司 | Circuit board assembly, battery protection board and electronic equipment |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN212434602U (en) * | 2020-09-18 | 2021-01-29 | 中芯长电半导体（江阴）有限公司 | Packaging structure |
| CN112951815A (en) * | 2021-01-14 | 2021-06-11 | 日月光半导体制造股份有限公司 | Semiconductor structure and manufacturing method thereof |
| CN114093772A (en) * | 2021-11-04 | 2022-02-25 | 盛合晶微半导体(江阴)有限公司 | Fan-out type packaging structure and packaging method |
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Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN212434602U (en) * | 2020-09-18 | 2021-01-29 | 中芯长电半导体（江阴）有限公司 | Packaging structure |
| CN112951815A (en) * | 2021-01-14 | 2021-06-11 | 日月光半导体制造股份有限公司 | Semiconductor structure and manufacturing method thereof |
| CN114093772A (en) * | 2021-11-04 | 2022-02-25 | 盛合晶微半导体(江阴)有限公司 | Fan-out type packaging structure and packaging method |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN116685044A (en) * | 2022-12-14 | 2023-09-01 | 荣耀终端有限公司 | Circuit board assembly, battery protection board and electronic equipment |
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