TWI447821B - 安裝基板及電子裝置 - Google Patents

安裝基板及電子裝置 Download PDF

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Publication number
TWI447821B
TWI447821B TW096149866A TW96149866A TWI447821B TW I447821 B TWI447821 B TW I447821B TW 096149866 A TW096149866 A TW 096149866A TW 96149866 A TW96149866 A TW 96149866A TW I447821 B TWI447821 B TW I447821B
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TW
Taiwan
Prior art keywords
mounting substrate
electrode
barrier member
mounting
region
Prior art date
Application number
TW096149866A
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English (en)
Other versions
TW200828461A (en
Inventor
Araki Yasushi
Original Assignee
Shinko Electric Ind Co
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Publication of TW200828461A publication Critical patent/TW200828461A/zh
Application granted granted Critical
Publication of TWI447821B publication Critical patent/TWI447821B/zh

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    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
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    • H01L21/563—Encapsulation of active face of flip-chip device, e.g. underfilling or underencapsulation of flip-chip, encapsulation preform on chip or mounting substrate
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Description

安裝基板及電子裝置
本揭示案係關於安裝基板及電子裝置，且更明確地說，係關於具有抑制底部填充材料(underfill material)之流動的障壁的安裝基板及電子裝置。
近來，經常使用覆晶安裝法作為將電子元件(諸如，半導體晶片)安裝於一安裝基板上之方法。覆晶安裝法為將凸塊形成於電子元件之安裝表面上且接著將電子元件面朝下地結合至形成於安裝基板上之電極的方法。
在此覆晶安裝法中，藉由凸塊與電極之間的結合力來結合電子元件與安裝基板。因此，一旦在電子元件與安裝基板之間產生應力，此應力便全部施加至凸塊與電極之間的結合位置。因此，在此覆晶安裝法中，通常將在電子元件與安裝基板之間填充底部填充樹脂(通常使用環氧樹脂)以達成應力鬆弛。
同時，在諸如半導體裝置或其類似物之電子裝置中，需要較高之封裝密度。作為滿足此較高封裝密度之封裝，很多關注集中於系統級封裝(SiP)。已提出各種不同的結構作為此SiP。作為此等結構之一種類型，存在層疊型封裝(PoP)，其藉由將封裝單個半導體晶片的封裝(半導體裝置)與堆疊複數個半導體晶片的封裝予以堆疊而實現SiP結構。
在具有此PoP結構之SiP之情況下，通常使用焊球將用作下層之封裝與用作上層之封裝相互結合。因此，在用作下層之封裝中，結合至焊球之電極必須形成於其上安裝有半導體晶片之安裝基板的上表面上。亦即，其上安裝有半導體晶片之晶片安裝區及形成有電極之電極形成區皆形成於安裝基板之上表面上，其構成用作下層之封裝。由於通常將電極配置成圍繞半導體晶片，故將電極形成區配置成圍繞晶片安裝區。
此處，當用作下層之封裝具有半導體晶片經覆晶安裝的結構時，如上所述，必須在半導體晶片與安裝基板之間填充底部填充樹脂以達成應力鬆弛。然而，由於在填充操作期間底部填充樹脂具有流動性，故有此底部填充樹脂會自晶片安裝區流出而進入電極形成區之虞。
為此，在相關技術中，在晶片安裝區與電極形成區之間提供障壁部件，其阻止底部填充樹脂自晶片安裝區流出而進入電極形成區(參見例如日本未審查專利公開案：JP－A－2005－276879)。
圖4A及圖4B展示相關技術中之具有障壁部件之安裝基板的實施例。圖4A為以放大方式展示安裝基板100之障壁部件105之形成位置及其附近的視圖，且圖4B為展示安裝基板100之障壁部件105之形成位置及其附近之剖面圖。
如上所述，障壁部件105係形成於其中形成有電極101之電極形成區103與其上安裝有半導體晶片(未圖示)之晶片安裝區102之間。在電極形成區103中，電極101自形成於阻焊劑104中之開口被暴露。再者，在安裝半導體晶片後，在晶片安裝區102中填充底部填充樹脂。
根據相關技術，障壁部件105經形成為像是框架形狀。再者，在過去當要求之封裝密度不如近年這般高時，相對遠地配置障壁部件105與電極101。
然而，近來趨勢為半導體晶片根據其較大功能性而尺寸增加，且因此端子之數目傾向於增加。相反，關於其上安裝有半導體晶片之安裝基板，需要較小面積來滿足對安裝於該安裝基板上之電子裝置之尺寸減小的需求。
因此，關於形成於安裝基板上之晶片安裝區102及電極形成區103，回應於半導體晶片尺寸之增加必須增加晶片安裝區102之面積，且回應於電極數目之增加亦必須增加電極形成區103之面積。另外，如上所述，必須整體減小安裝基板100之面積。
在相關技術中，存在此問題：安裝基板100不可同時滿足各別要求。再者，作為實現此等要求之方法，可認為應使障壁部件105之寬度變窄。然而，當障壁部件105之寬度變窄時，障壁部件105之結合至基板主體100a之結合區變窄且相應地機械強度降低。結果，在填充底部填充樹脂時會損害障壁部件105，且因此有不可有效地防止底部填充樹脂流出而進入電極形成區103之虞。
本發明係基於上述問題而達成，且本發明之目的為提供能夠達成電極形成區及安裝區之面積增加而同時維持障壁部件之強度的安裝基板及電子裝置。
為了解決上述問題，藉由如下各別方法來達成本發明。
根據本發明之第一態樣，一安裝基板包含：一安裝區，其上安裝有一電子元件；一電極形成區，其上形成有電極且其經形成以圍繞該安裝區；及一障壁部件，其形成於在該安裝區與該電極形成區之間的邊界上以阻止填充於該電子元件與該安裝基板之間的填充材料流出而進入該電極形成區，其中面向該等電極之凹陷部分形成於該障壁部件之外周邊表面上，及該等電極之一部分形成於該等凹陷部分內。
根據本發明之第二態樣，障壁部件在不同於形成有凹陷部分之位置的位置中的第一寬度尺寸可大於障壁部件在形成有凹陷部分之位置中的第二寬度尺寸。
根據本發明之第三態樣，阻焊劑可形成於安裝基板之基板主體上，且障壁部件可由與阻焊劑相同之材料形成。
根據本發明之第四態樣，在凹陷部分與電極面向彼此之區域內，凹陷部分與面向凹陷部分之電極之間的間隙經設定為分別相等。
根據本發明之第五態樣，障壁部件之面向安裝區之內周邊表面可形成為直線形狀。
根據本發明之第六態樣，填充材料可為底部填充樹脂。
根據本發明之第七態樣，一電子裝置包含：一電子元件；一安裝基板；及一填充材料，其填充於該電子元件與該安裝基板之間，其中該安裝基板包括：一安裝區，其上安裝有該電子元件；一電極形成區，其上形成有電極且其經形成以圍繞該安裝區；及一障壁部件，其形成於在該安裝區與該電極形成區之間的邊界上，以阻止該填充材料流出而進入該電極形成區，其中面向該等電極之凹陷部分形成於該障壁部件之外周邊表面上，及該等電極之一部分形成於該等凹陷部分內。
根據本發明，面向該等電極之凹陷部分形成於該障壁部件之外周邊表面上，且該等電極之一部分形成於該等凹陷部分內。因此，該障壁部件之一部分可經組態以硬擠進電極形成區，且可相應地增加該安裝區之面積。
接下來，在下文中將參考圖式來詳細地描述示範性具體例。
圖1為展示作為根據本發明之具體例之電子裝置的系統級封裝10的剖面圖。簡要地分類，圖1中所示之系統級封裝10係由下層封裝11及上層封裝12構成。
下層封裝11包括下層安裝基板14、焊球16、下電極17、上電極18、半導體晶片20，及其類似物。下層安裝基板14為多層佈線基板，且藉由使用電鍍法或其類似物在由絕緣樹脂製成之基板主體14a之上表面及下表面上形成佈線層(例如，Cu佈線層)、通道等。
上電極18形成於基板主體14a之最上層上，及下電極17形成於最下層上。再者，使用內部佈線19及通道29來連接下電極17及上電極18。
再者，下阻焊劑30形成於下層安裝基板14之下表面上，及上阻焊劑24形成於下層安裝基板14之上表面上。開口部分形成於上阻焊劑24中面向上電極18之位置中，及開口部分形成於下阻焊劑30中形成有下電極17之位置中。因此，各別電極17、18經構造以經由此等開口部分自阻焊劑24、30被暴露。
另外，用作系統級封裝10之外部連接端子的焊球16形成於下層安裝基板14之下表面上。焊球16形成於自形成於下阻焊劑30中之開口部分暴露的下電極17上。
如稍後所述，形成於下層安裝基板14之上表面上的上電極18為堆疊焊球21所結合至之電極。上電極18經形成以圍繞提供半導體晶片之區域(下文中稱作「晶片安裝區27」)。此處，上電極18形成於下層安裝基板14上所在之區域在下文中被稱作電極形成區28。
半導體晶片20為例如邏輯IC且係藉由覆晶結合法安裝於下層安裝基板14上。具體地，在半導體晶片20上提供凸塊22，且將凸塊22覆晶結合至形成於下層安裝基板14之上表面上之上佈線19。因此，將半導體晶片20安裝於下層安裝基板14上。再者，在半導體晶片20與下層安裝基板14之間提供底部填充樹脂23以增強結合可靠性。在晶片安裝區27中填充此底部填充樹脂23。
再者，障壁部件50形成於下層安裝基板14之上表面上。障壁部件50阻止底部填充樹脂23自晶片安裝區27流出而流至電極形成區28。為便於描述，稍後將描述障壁部件50。
與之對比，上層封裝12包括上層安裝基板15、半導體晶片40、41、下電極37、上電極38、密封樹脂49，及其類似物。上層安裝基板15為類似於上述下層安裝基板14的多層佈線基板。上電極38形成於上層安裝基板15之上表面上，且下電極37形成於上層安裝基板15之下表面上。各別電極37、38係藉由內部佈線39及其類似物相互連接。
再者，下阻焊劑60形成於上層安裝基板15之下表面上，且上阻焊劑44形成於上層安裝基板15之上表面上。開口部分形成於上阻焊劑44中面向上電極38之各別位置中。開口部分形成於下阻焊劑60中形成有下電極37之各別位置中。因此，各別電極37、38經構造以經由該等開口部分而自各別阻焊劑44、60暴露。
半導體晶片40、41分別為例如記憶體IC且經由隔片48而堆疊於上層安裝基板15上。再者，半導體晶片40、41與形成於上層安裝基板15上之上電極38係藉由導線45、46電連接。
密封樹脂49為例如絕緣樹脂，諸如環氧樹脂或其類似物，且經形成以密封半導體晶片40、41及導線45、46。可使用例如轉移模製來形成此密封樹脂49。
如上所述，下層封裝11與上層封裝12經由堆疊焊球21得以相互結合以構成系統級封裝10。堆疊焊球21結合至下層安裝基板14之上電極18，且亦結合至上層安裝基板15之下電極37。因此，下層封裝11與上層封裝12係彼此電連接，且上層封裝12得到支撐以使得此封裝12堆疊於下層封裝11上。
隨後，將參考圖3A及圖3B來主要描述構成本發明之相關部分的障壁部件50。障壁部件50提供於下層安裝基板14上。此處，半導體晶片20係覆晶結合至下層安裝基板14，且堆疊焊球21所結合至之上電極18形成於下層安裝基板14之上表面上。
圖3A為展示障壁部件50在下層安裝基板14上之形成位置及其附近的視圖，且圖3B為其剖面圖。接下來，在下文中將參考圖2來描述圖3A及圖3B中所示之區域。
圖2為展示下層安裝基板14在上層封裝12堆疊於其上之前的平面圖。如圖2所示，半導體晶片20安裝於電極形成區28之中央部分中，電極形成區28位於下層安裝基板14內部。
再者，複數個上電極18形成於下層安裝基板14之在半導體晶片20外部的周邊位置上，以形成電極形成區28。障壁部件50形成於晶片安裝區27與電極形成區28之間的邊界上。
為了消除在半導體晶片20與下層安裝基板14之間引起的應力，在半導體晶片20與下層安裝基板14之間填充底部填充樹脂23。然而，因為底部填充樹脂23在填充時具有流動性，所以底部填充樹脂23之一部分流出至半導體晶片20之外周邊。
然而，向晶片安裝區27之外周邊邊緣提供障壁部件50以阻止進一步流出。因此，可防止底部填充樹脂23在電極形成區28中流動且因此電極形成區28由底部填充樹脂23覆蓋而造成連接故障的情形。圖3A及圖3B展示如上所構造之下層安裝基板14得自圖2中以箭頭A指示的區域之放大圖。
如上所述，障壁部件50形成於在晶片安裝區27與電極形成區28之間的邊界上。為了阻止底部填充樹脂23流出而進入電極形成區28，將此障壁部件50形成為像是框架形狀以圍繞晶片安裝區27。
此障壁部件50係與形成於下層安裝基板14之最上表面上之上阻焊劑24整體地形成。具體地，障壁部件50係藉由以下步驟所形成：在形成上阻焊劑24時塗佈阻焊劑材料直至障壁部件50所需之厚度(自基板表面開始之高度)，及接著自除了經由蝕刻或其類似物而形成障壁部件50之區域以外的區域移除阻焊劑材料。
結果，障壁部件50與上阻焊劑24形成為單片結構且自上阻焊劑24突出。再者，因為在形成上阻焊劑24時，同時形成障壁部件50，所以可容易地形成障壁部件50。
此處，在下文中將論述圖3A及圖3B中所示之障壁部件50之形狀。在本具體例中，凹陷部分51形成於障壁部件50之外周邊表面上。凹陷部分51形成於障壁部件50之面向電極形成區28的外周邊表面上。再者，凹陷部分51具有彎曲表面53，且上電極18之一部分位於凹陷部分51內。
根據此組態，障壁部件50之一部分經構造以進入電極形成區28中。因此，在不改變電極形成區28之面積或增加電極形成區28之面積的情況下，可增加晶片安裝區27之面積。再者，障壁構件50之面向晶片安裝區27之內周邊表面經形成為直線內周邊表面54。以此方式，因為對應於填充有底部填充樹脂23之側面的內周邊表面54經形成為直線形狀，所以可增強底部填充樹脂23之填充效率且可防止填充不均勻性之產生。
順便一提，因為以類似柵格方式來配置上電極18，所以可在上電極18之間的間隙位置中，亦即，在相鄰凹陷部分51之間的間隙位置中，放大障壁部件50之寬度。具體地，障壁部件50在不同於形成有凹陷部分51之位置的位置中的寬度尺寸(在下文中稱作「第一寬度尺寸W1」)可經形成為大於障壁部件50在形成有凹陷部分51之位置中的寬度尺寸(在下文中稱作「第二寬度尺寸W2」)(W1>W2)。在下文中，在障壁部件50中，寬度尺寸比在形成有凹陷部分51之位置中之寬度尺寸寬的部分被稱作錨定部分52。
因為第二寬度尺寸W2比錨定部分52之寬度尺寸窄，所以凹陷部分51與上阻焊劑24之間的結合力為弱的。然而，在錨定部分52中，可將第一寬度尺寸W1設定為較寬。再者，因為錨定部分52可經形成以進入相鄰上電極18中，所以產生增加第一寬度尺寸W1之裕度。
以此方式，可藉由增加第一寬度尺寸W1來增加錨定部分52之面積，且因此可增強對上阻焊劑24之結合力。因此，儘管將凹陷部分51形成於障壁部件50上以增加晶片安裝區27之面積並減小下層安裝基板14之面積，但凹陷部分51之兩側部分皆充當錨定部分52以增強對上阻焊劑24之結合力。因此，仍可維持障壁部件50之機械強度。結果，即使在凹陷部分51形成於障壁部件50上時，在填充底部填充樹脂23及其類似物時仍絕不會損害障壁部件50，且因此可增加下層安裝基板14之可靠性。
另外，在本具體例中，設定構成凹陷部分51之彎曲表面53之曲率，使得可始終保持自彎曲表面53至上電極18之外周邊的距離(在圖3A及圖3B中以箭頭L指示)為相同距離。藉由採用此組態，儘管在上電極18之形成位置及障壁部件50之形成位置方面引起一些誤差，但可有效地防止障壁部件50形成於上電極18上的情形。
在上述具體例中，雖然凹陷部分51經形成為具有彎曲表面53，但凹陷部分51之形狀不限於此形狀，且可根據上電極18之形狀，適當地改變凹陷部分51之形狀。
再者，在本具體例中，雖然本發明應用於半導體晶片20被安裝於下層安裝基板14上的示範性具體例，但本發明之應用不限於該等示範性具體例，且可採用各種應用。
另外，在本具體例中，雖然將底部填充樹脂23用作填充材料之實施例，但本發明亦可應用於要求高封裝密封之基板所需的其他填充材料(例如，焊料填充及其類似物)。
雖然已結合本發明之示範性具體例來描述，但熟習此項技術者顯而易見，在不脫離本發明之情況下可進行各種改變及修改。因此，目的是在所附申請專利範圍中涵蓋落入本發明之實際精神及範疇內的所有此等改變及修改。
10．．．系統級封裝
11．．．下層封裝
12．．．上層封裝
14．．．下層安裝基板
14a．．．基板主體
15．．．上層安裝基板
16．．．焊球
17．．．下電極
18．．．上電極
19．．．內部佈線
20．．．半導體晶片
21．．．堆疊焊球
22．．．凸塊
23．．．底部填充樹脂
24．．．阻焊劑
27．．．晶片安裝區
28．．．電極形成區
29．．．通道
30．．．阻焊劑
37．．．下電極
38．．．上電極
39．．．內部佈線
40．．．半導體晶片
41．．．半導體晶片
44．．．上阻焊劑
45．．．導線
46．．．導線
48．．．隔片
49．．．密封樹脂
50．．．障壁部件
51．．．凹陷部分
52．．．錨定部分
53．．．彎曲表面
54．．．直線內周邊表面
60．．．下阻焊劑
100．．．安裝基板
100a．．．基板主體
101．．．電極
102．．．晶片安裝區
103．．．電極形成區
104．．．阻焊劑
105．．．障壁部件
A．．．區域
L．．．距離
W1．．．第一寬度尺寸
W2．．．第二寬度尺寸
圖1為展示作為根據本發明之具體例之電子裝置的系統級封裝的剖面圖；圖2為根據本發明之具體例之安裝基板的平面圖；圖3A及圖3B為根據本發明之具體例之安裝基板的相關部分之放大圖；及圖4A及圖4B為說明根據相關技術中之實施例之安裝基板的視圖。
14．．．下層安裝基板
14a．．．基板主體
18．．．上電極
24．．．阻焊劑
27．．．晶片安裝區
28．．．電極形成區
50．．．障壁部件
51．．．凹陷部分
52．．．錨定部分
53．．．彎曲表面
54．．．直線內周邊表面
L．．．距離
W1．．．第一寬度尺寸
W2．．．第二寬度尺寸

Claims (7)

  1. 一種安裝基板，其係在基板主體上包含：安裝區，其安裝有電子元件；電極形成區，其形成有電極並且以圍繞上述安裝區而形成；及障壁部件，其形成於上述安裝區與上述電極形成區之間的邊界部分上，在上述安裝區阻止所填充於上述電子元件與上述基板主體之間的填充材料朝向上述電極形成區產生洩漏；如此之安裝基板其特徵為，以下列之方式加以構成：上述障壁部件之與上述電極對向之位置上，形成具有彎曲表面之凹陷部分，並且上述電極之一部分位於該凹陷部分之內部，且上述障壁部件之一部分進入至上述電極間。
  2. 如申請專利範圍第1項之安裝基板，其中，上述障壁部件，係在形成上述凹陷部分之位置以外之位置的寬度尺寸，即第一寬度尺寸，為大於在形成上述凹陷部分之位置之寬度尺寸，即第二寬度尺寸。
  3. 如申請專利範圍第1或2項之安裝基板，其中，上述基板主體係形成有阻焊劑，且上述障壁部件係由與該阻焊劑相同之材料所形成。
  4. 如申請專利範圍第1或2項之安裝基板，其中，在上述凹陷部分與上述電極之對向範圍中，以上述凹陷部分與上述電極之分隔距離成為相等之方式加以構成。
  5. 如申請專利範圍第1或2項之安裝基板，其中， 上述障壁部件之上述安裝區側係為直線形狀。
  6. 如申請專利範圍第1或2項之安裝基板，其中，上述填充材料係為底部填充樹脂。
  7. 一種電子裝置，其特徵在於包含：電子元件；及申請專利範圍第1或2項所記載之安裝基板；且構成於上述障壁部件內之上述電子元件與上述基板主體之間填充有填充材料。
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