TWI745162B - 半導體封裝結構 - Google Patents

半導體封裝結構 Download PDF

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Publication number
TWI745162B
TWI745162B TW109139600A TW109139600A TWI745162B TW I745162 B TWI745162 B TW I745162B TW 109139600 A TW109139600 A TW 109139600A TW 109139600 A TW109139600 A TW 109139600A TW I745162 B TWI745162 B TW I745162B
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Taiwan
Prior art keywords
chip
pads
substrate
layer
semiconductor package
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TW109139600A
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English (en)
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TW202220120A (zh
Inventor
蘇志彥
林俊德
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力成科技股份有限公司
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Priority to TW109139600A priority Critical patent/TWI745162B/zh
Priority to US17/198,653 priority patent/US11694950B2/en
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Publication of TWI745162B publication Critical patent/TWI745162B/zh
Publication of TW202220120A publication Critical patent/TW202220120A/zh

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  • Engineering & Computer Science (AREA)
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  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
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Abstract

本發明係一種半導體封裝結構，係包含一基板、一晶片及一封膠體；該基板包含有一介電層、一銅線層及一阻焊層，其中該銅線層係形成於該介電層上，並被該阻焊層所覆蓋，該阻焊層包含一晶片區並形成一圍繞該晶片區外的環狀開口，使該銅線層部分外露；該晶片係設置於該晶片區，並由該封膠體所包覆；因此，本發明係於該阻焊層的該晶片區外形成該環狀開口，藉由該環狀開口使該阻焊層不連續，降低於熱循環測試期間因為該封膠體形變所集中於該基板靠近該晶片邊緣附近的應力，避免該基板於該阻焊層或該銅線層產生裂痕。

Description

半導體封裝結構
本發明係關於一種半導體封裝結構，尤指一種低應力集中的半導體封裝結構。
熱循環測試(TCT，thermal-cycle test)是半導體封裝結構進行可靠度測試時常進行的測試，其係透過不斷的的變化環境溫度模擬出嚴苛的條件，藉此了解半導體封裝結構可能產生的潛在性問題以及失效的原因；因此，半導體封裝結構於熱循環測試中，必須承受很大溫度變化。
如圖4A所示，係現有技術之一半導體封裝結構70，其包含一基板71，一晶片72以及一封膠體73，對該半導體封裝結構70進行多次的熱循環測試之後，於該基板71靠近該晶片72邊緣部分的一阻焊層711產生一裂痕712，再如圖4B所示，該裂痕712也可能進一步延伸至該基板71內部的一銅線層713之中，故該裂痕712的產生，除了導致該半導體封裝結構70的可靠度下降之外，若該裂痕712延伸至該銅線層713之中，將導致該阻焊層711的絕緣效果不佳，使該晶片72的接墊721直接與該銅線層713短路而失效。
究其原因係該基板71的熱膨脹係數與該封膠體73的熱膨脹係數不同，於溫度變化時該封膠體73的形變量大於該基板71，又因為該晶片72較硬不容易形變，所以該封膠體73形變所產生的應力集中於該基板71靠近該晶片72邊緣，導致該裂痕712的產生；因此，有必要進一步改良現有之半導體封裝結構70。
有鑑於上述半導體封裝結構的問題，本發明的主要目的係提供一種改良的半導體封裝結構。
欲達上述發明之目的所使用的主要技術手段係令該半導體封裝結構包含： 一基板，係包含一介電層、一銅線層及一阻焊層，該銅線層係形成於該介電層的一第一表面上，該阻焊層係覆蓋該銅線層，其中該阻焊層包含一晶片區及一圍繞在該晶片區周圍的外圍區，於該外圍區上形成一環狀開口，使對應該該環狀開口的該銅線層部分外露； 一第一晶片，係設置於該阻焊層的該晶片區，並與該基板電連接；以及 一封膠體，係形成於該基板上的該晶片區及該外圍區，並包覆該第一晶片。
由上述的說明可知，本發明係於該基板的該阻焊層的該外圍區形成該環狀開口，藉由該環狀開口使該阻焊層不連續，降低集中於該基板靠近該晶片邊緣附近的應力，避免該基板於該阻焊層或該銅線層產生裂痕。
本發明係針對半導體封裝結構進行改良，並以多個實施例配合圖式詳細說明本發明技術內容。
首先請參閱圖1A所示，係本發明半導體封裝結構10的第一實施例，其包含有一基板20、一第一晶片30及一封膠體40，其中該第一晶片30係設置於該基板20上，且與該基板20電連接，並被該封膠體40所包覆；於本實施例，該半導體封裝結構10係一覆晶封裝結構。
上述基板20係包含一介電層21、一銅線層22及一阻焊層23、多個內接墊24及多個外接墊25，其中該介電層21包含相對的一第一表面211和一第二表面212，該銅線層22及該些內接墊24係形成於該介電層21的該第一表面211上，且該些內接墊24係與對應的銅線層22連接，即該些內接墊24係直接與對應的銅線層22電連接，該阻焊層23係形成在該介電層21的該第一表面211以覆蓋該銅線層22，但不覆蓋該些內接墊24，即該些內接墊24外露於該阻焊層23；於本實施例，如圖1A所示，該阻焊層23係包含一晶片區231及一外圍區232，該些內接墊24均位在該晶片區231內，而該外圍區232係圍繞該晶片區231，並於該外圍區232形成一環狀開口233，使對應該環狀開口233的該銅線層22的部分外露；該些外接墊25係形成於該介電層21的該第二表面212，且與對應的銅線層22電連接，並分別形成一錫球251。較佳地，該環狀開口233可再靠近該晶片區231。
於本實施例，如圖2A所示，該環狀開口233的寬度為D1；於另一實施例，如圖2B所示，該環狀開口233對應該晶片區231角落部分的開口233’的寬度加大為D2；較佳地，該環狀開口233的寬度D1、D2大小係介於50um至300um之間。
上述第一晶片30係包含一第一主動面31及一相對該第一主動面31的第一背面32，其中該第一主動面31係固定於該阻焊層23的該晶片區231；於本實施例，如圖1A所示，該第一晶片30係於該第一主動面31形成對應該些內接墊24的多個第一接墊33，且各該第一接墊33係直接電連接對應的該內接墊24，因此該第一主動面31與該阻焊層23之間保持一間隙，故可進一步對該間隙填充一底膠311，保護該些第一接墊33及該些內接墊24。
上述封膠體40係形成於該基板20上，以包覆該第一晶片30；於本實施例，如圖1A所示，該封膠體40係形成於該基板20的該晶片區231及該外圍區232，即該封膠體40的四側與該基板20四側齊平；於本實施例，該封膠體40可進一步一併填充該環狀開口233。
請參閱圖1B所示，係本發明半導體封裝結構10a的第二實施例；本實施例之半導體封裝結構10a與圖1A所示之半導體封裝結構10大致相同，惟該環狀開口233係填入一填充物質233a，其中該填充物質233a的楊式係數(Young's modulus)高於該封膠體40的楊式係數；於本實施例，由於該底膠311的楊式係數高於該封膠體40的楊式係數，故可於該第一主動面31與該基板20的該阻焊層23之間填充該底膠311時，一併於該環狀該口233填入該底膠311，即以該底膠311作為該填充物質233a。於另一實施例，可於該環狀開口233填入一環氧成型模料(Epoxy Molding Compound；EMC)作為該填充物質233a。
再請參閱圖3所示，係本發明半導體封裝結構10b的第四實施例，其與本發明半導體封裝結構10大致相同，同樣包含有一基板20’、一第一晶片50及一封膠體40，惟該半導體封裝結構10b係一打線封裝結構。
上述基板20’係於該阻焊層23的該外圍區232形成多個內接墊24’及一環狀開口233；於本實施例，該環狀開口233較該些內接墊24’更靠近該晶片區231。再如圖2A所示，該環狀開口233的寬度為D1；於另一實施例，如圖2B所示，該環狀開口233對應該晶片區231角落部分的開口233’的寬度加大為D2；較佳地，該環狀開口233的寬度D1、D2大小係介於50um至300um之間。
上述第一晶片50係包含一第一主動面51及一相對該第一主動面51的第一背面52，其中該第一晶片50係經由一第一黏膠層53將該第一背面52黏著於該基板20’的該阻焊層23的該晶片區231上，並於該第一主動面51形成多個第一接墊54，各該第一接墊54係與該基板20上對應的該內接墊24’以一第一導線55電連接。此外，於另一實施例，可進一步包含一第二晶片60，該第二晶片60包含一第二主動面61及一相對該第二主動面61的一第二背面62，其中該第二晶片60係經由一第二黏膠層63將該第二背面62黏著於該第一晶片50的該第一主動面51上，但不覆蓋該些第一接墊54，並於該第二主動面61形成多個第二接墊64，各該第二接墊64係與該基板20’上對應的該內接墊24’以一第二導線65電連接。因此，本發明可堆疊多顆晶片，不以二顆為限。
上述封膠體40係形成於該基板20’，以包覆該第一晶片50及該第二晶片60，並可進一步一併填充該環狀開口233，也可如圖1B所示，以楊式係數高於該封膠體40的該填充物質233a填充該環狀開口233，其中該填充物質233a可以是一底膠或一環氧成型模料。
綜上所述，本發明係於該基板的該阻焊層的該外圍區形成該環狀開口，藉由該環狀開口使該阻焊層不連續，降低集中於該基板靠近該晶片邊緣附近的應力，避免該基板於該阻焊層或該銅線層產生裂痕；再者，本發明可進一步加大對應該晶片區角落部分的該環狀開口的寬度，進一步減少該基板角落所受到較大的應力。本發明於該環狀開口進一步填入該填充物質，也可更進一步抵抗該封膠體形變所造成的應力；因此，本發明的半導體封裝結構可避免該基板於晶片周圍產生裂痕。
以上所述僅是本發明的實施例而已，並非對本發明做任何形式上的限制，雖然本發明已以實施例揭露如上，然而並非用以限定本發明，任何所屬技術領域中具有通常知識者，在不脫離本發明技術方案的範圍內，當可利用上述揭示的技術內容作出些許更動或修飾為等同變化的等效實施例，但凡是未脫離本發明技術方案的內容，依據本發明的技術實質對以上實施例所作的任何簡單修改、等同變化與修飾，均仍屬於本發明技術方案的範圍內。
10:半導體封裝結構 10a:半導體封裝結構 10b:半導體封裝結構 20:基板 20’:基板 21:介電層 211:第一表面 212:第二表面 22:銅線層 23:阻焊層 231:晶片區 232:外圍區 233:環狀開口 233’:角落部分開口 233a:填充物質 24:內接墊 24’:內接墊 25:外接墊 251:錫球 30:第一晶片 31:第一主動面 311:底膠 32:第一背面 33:第一接墊 40:封膠體 50:第一晶片 51:第一主動面 52:第一背面 53:第一黏膠層 54:第一接墊 55:第一導線 60:第二晶片 61:第二主動面 62:第二背面 63:第二黏膠層 64:第二接墊 65:第二導線 70:半導體封裝結構 71:基板 711:阻焊層 712:裂痕 713:銅線層 72:晶片 721:接墊 73:封膠體
圖1A：本發明半導體封裝結構之第一實施例的剖面圖。 圖1B：本發明半導體封裝結構之第二實施例的剖面圖。 圖2A：本發明半導體封裝結構之第一實施例的俯視圖。 圖2B：本發明半導體封裝結構之第三實施例的俯視圖。 圖3：本發明半導體封裝結構之第四實施例的剖面圖。 圖4A：現有技術之半導體封裝結構的剖面圖。 圖4B：圖4A之局部放大圖。
10:半導體封裝結構
20:基板
21:介電層
211:第一表面
212:第二表面
22:銅線層
23:阻焊層
231:晶片區
232:外圍區
233:環狀開口
24:內接墊
25:外接墊
251:錫球
30:第一晶片
31:第一主動面
311:底膠
32:第一背面
33:第一接墊
40:封膠體

Claims (10)

  1. 一種半導體封裝結構，包含： 一基板，係包含一介電層、一銅線層及一阻焊層，該銅線層係形成於該介電層的一第一表面上，該阻焊層係覆蓋該銅線層，其中該阻焊層包含一晶片區及一圍繞在該晶片區周圍的外圍區，於該外圍區上形成一環狀開口，使對應該環狀開口的該銅線層部分外露； 一第一晶片，係設置於該阻焊層的該晶片區，並與該基板電連接；以及 一封膠體，係形成於該基板上的該晶片區及該外圍區，並包覆該第一晶片。
  2. 如請求項1所述之半導體封裝結構，其中： 該基板係進一步包含多個內接墊及多個外接墊，該些內接墊係形成在該介電層的該第一表面上，並與對應的該銅線層電連接，且外露於該阻焊層的該晶片區，該些外接墊係形成在該介電層的一第二表面上，並與對應的該銅線層電連接；以及 該第一晶片係進一步包含一朝向該基板的第一主動面，並於該第一主動面形成多個第一接墊，其中該些第一接墊係分別與該基板對應的該內接墊電連接。
  3. 如請求項2所述之半導體封裝結構，其中該第一晶片的第一主動面與該基板之阻焊層間的間隙內填充一底膠。
  4. 如請求項1所述之半導體封裝結構，其中： 該基板係進一步包含多個內接墊及多個外接墊，該些內接墊係形成在該介電層的第一表面上，並與對應的該銅線層電連接，且外露於該阻焊層的該外圍區，其中該環狀開口較該些內接墊靠近該晶片區；該些外接墊係形成在該介電層的一第二表面上，並與對應的該銅線層電連接；以及 該第一晶片係進一步包含一遠離該基板的第一主動面及一相對該第一主動面的第一背面，該第一背面係固定在該阻焊層的該晶片區上，並於該第一主動面形成多個第一接墊，其中該些第一接墊係分別與該基板對應的該內接墊以打線方式電連接。
  5. 如請求項4所述之半導體封裝結構，係進一步於該第一晶片上疊合一第二晶片，其中該第二晶片包含： 一第二主動面，係遠離該第一晶片且形成多個第二接墊，其中該些第二接墊係分別與該基板對應的該內接墊以打線方式電連接；以及 一第二背面，係相對該第二主動面，且該第二背面係固定在該第一晶片的該第一主動面上。
  6. 如請求項1至5中任一項所述之半導體封裝結構，係進一步於該環狀開口填入該封膠體或一填充物質，其中該填充物質的楊式係數高於該封膠體的楊式係數。
  7. 如請求項6所述之半導體封裝結構，其中該填充物質係一環氧成型模料或一底膠。
  8. 如請求項1至5中任一項所述之半導體封裝結構，其中該環狀開口對應該晶片區角落部分的開口寬度大於該環狀開口其他部分的開口寬度。
  9. 如請求項8所述之半導體封裝結構，係進一步於該環狀開口填入該封膠體或一填充物質，其中該填充物質的楊式係數高於該封膠體的楊式係數。
  10. 如請求項9所述之半導體封裝結構，其中該填充物質係一環氧成型模料或一底膠。
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