TWM524553U - 半導體封裝結構 - Google Patents

半導體封裝結構 Download PDF

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Publication number
TWM524553U
TWM524553U TW105203912U TW105203912U TWM524553U TW M524553 U TWM524553 U TW M524553U TW 105203912 U TW105203912 U TW 105203912U TW 105203912 U TW105203912 U TW 105203912U TW M524553 U TWM524553 U TW M524553U
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Taiwan
Prior art keywords
semiconductor package
layer
package structure
semiconductor
solder resist
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TW105203912U
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English (en)
Inventor
Lee-Sheng Yen
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Team Expert Man Consulting Service Ltd
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Application filed by Team Expert Man Consulting Service Ltd filed Critical Team Expert Man Consulting Service Ltd
Priority to TW105203912U priority Critical patent/TWM524553U/zh
Priority to CN201620275866.8U priority patent/CN205542765U/zh
Publication of TWM524553U publication Critical patent/TWM524553U/zh
Priority to US15/357,252 priority patent/US20170271267A1/en

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    • H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
    • H01L23/5389—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates the chips being integrally enclosed by the interconnect and support structures
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Description

半導體封裝結構
本創作係有關一種半導體封裝結構，尤指一種薄型化半導體封裝結構。
隨著半導體封裝技術的演進，半導體裝置(Semiconductor device)已開發出不同的封裝型態。其中，球柵陣列式(Ball grid array，簡稱BGA)，例如PBGA、EBGA、FCBGA等，為一種先進的半導體封裝技術，其特點在於採用一封裝基板來安置半導體元件，並於該封裝基板背面植置多數個成柵狀陣列排列之錫球(Solder ball)，使相同單位面積之承載件上可容納更多輸入/輸出連接端(I/O connection)以符合高度集積化(Integration)之半導體晶片之需求，並藉該些錫球將整個封裝單元焊結並電性連接至外部電子裝置。
再者，為了符合半導體封裝件輕薄短小、多功能、高速度及高頻化的開發方向，半導體晶片封裝用之電路板(或封裝基板)已朝向細線路及小孔徑發展。現有電路板製程從傳統100微米之線路尺寸，如導線寬度(Line width)、線路間距(Space)及深寬比(Aspect ratio)等，已縮減至20微米，並持續朝向更小的線路精度進行研發。
如第1圖所示，習知半導體封裝件1係包括一基板結構10、設於基板結構10上之一半導體晶片11、包覆該半導體晶片11之封裝膠體12、以及設於該基板結構10底側之複數焊球13。
具體地，該基板結構10係由複數介電層100構成主體，且各該介電層100上設有線路層101，並於各該線路層101之間以複數導電盲孔102作層間電性連接，又該焊球13電性連接該線路層101。該基板結構10亦可為兩層線路之封裝基板、或具有核心板之封裝基板等。
再者，該半導體晶片11係具有相對之作用面11a與非作用面11b，該作用面11a上具有複數電極墊110，以藉由該導電盲孔102電性連接該電極墊110與該線路層101。
惟，習知半導體封裝件1中，用以承載半導體晶片11之基板結構10係為多層線路之封裝基板、或具有核心板之封裝基板，致使該半導體封裝件1之厚度較厚，因而難以符合薄化之需求。
因此，如何克服習知技術中之問題，實已成目前亟欲解決的課題。
鑑於上述習知技術之缺失，本創作提供一種半導體封裝結構，係包括：防焊層；一線路層，係埋設於該防焊層中且部分外露於該防焊層；半導體元件，係設於該防焊層上，且具有相對之作用面與非作用面，其中，該半導體元件係藉其作用面電性連接該線路層；以及介電體，係形成 於該防焊層上以包覆該半導體元件。
前述之半導體封裝結構中，該防焊層形成有複數開孔，以令部分該線路層外露於該些開孔。
前述之半導體封裝結構中，該半導體元件之作用面具有複數電性連接該線路層之電極墊。例如，該些電極墊藉由導電體電性連接該線路層，其中，該導電體係為銀膠、紫外線硬化膠、異方性導電膜、焊料合金、無鉛焊料或錫金共晶焊料。
前述之半導體封裝結構中，該半導體元件之非作用面外露於該介電體之表面。
前述之半導體封裝結構中，該半導體元件之非作用面上形成有金屬層。
前述之半導體封裝結構中，形成該介電體之材質係包含浸玻璃纖維織布。
前述之半導體封裝結構中，該介電體中形成有至少一貫穿該介電體之導電柱，以電性連接該線路層。
另外，前述之半導體封裝結構中，該介電體上形成有佈線層。
由上可知，本創作之半導體封裝結構，主要藉由防焊層之設計以取代習知多層線路之基板或具核心層之基板，即以防焊層取代習知介電層或習知核心板，能降低該半導體封裝結構之厚度。
1‧‧‧半導體封裝件
10‧‧‧基板結構
100‧‧‧介電層
101,201‧‧‧線路層
102‧‧‧導電盲孔
11‧‧‧半導體晶片
11a,21a‧‧‧作用面
11b,21b‧‧‧非作用面
110,210‧‧‧電極墊
12‧‧‧封裝膠體
13‧‧‧焊球
2,3a,3b,3c‧‧‧半導體封裝結構
20‧‧‧防焊層
200,200’,300‧‧‧開孔
201a‧‧‧電性接觸墊
21‧‧‧半導體元件
22‧‧‧介電體
22a‧‧‧第一表面
22b,22b’‧‧‧第二表面
23‧‧‧導電元件
24‧‧‧導電體
25‧‧‧表面處理層
26‧‧‧金屬層
34‧‧‧導電柱
35‧‧‧佈線層
第1圖係為習知半導體封裝件之剖面示意圖； 第2圖係為本創作半導體封裝結構之剖面示意圖；以及第3A至3C圖係為本創作半導體封裝結構之其它不同實施例的剖面示意圖。
以下藉由特定的具體實施例說明本創作之實施方式，熟悉此技藝之人士可由本說明書所揭示之內容輕易地瞭解本創作之其他優點及功效。
須知，本說明書所附圖式所繪示之結構、比例、大小等，均僅用以配合說明書所揭示之內容，以供熟悉此技藝之人士之瞭解與閱讀，並非用以限定本創作可實施之限定條件，故不具技術上之實質意義，任何結構之修飾、比例關係之改變或大小之調整，在不影響本創作所能產生之功效及所能達成之目的下，均應仍落在本創作所揭示之技術內容得能涵蓋之範圍內。同時，本說明書中所引用之如“上”、“第一”、“第二”及“一”等之用語，亦僅為便於敘述之明瞭，而非用以限定本創作可實施之範圍，其相對關係之改變或調整，在無實質變更技術內容下，當亦視為本創作可實施之範疇。
第2圖係為本創作之半導體封裝結構2之剖面示意圖。如第2圖所示，該半導體封裝結構2係包括：一埋設有一線路層201之防焊層20、一半導體元件21、以及一介電體22。
所述之防焊層20係於其上側形成有複數開孔200，以 令該線路層201之部分表面外露於該些開孔200。
於本實施例中，該線路層201係以電鍍銅方式製作，且具有複數電性接觸墊201a，使該些電性接觸墊201a外露於各該開孔200。
再者，該防焊層20下側亦可形成有複數開孔200’，以令該線路層201之部分表面外露於該些開孔200’，俾供結合如焊球之導電元件23。
所述之半導體元件21係設於該防焊層20上並電性連接該線路層201，且該半導體元件21係具有相對之作用面21a與非作用面21b，該作用面21a上具有複數電極墊210。
於本實施例中，該半導體元件21可為主動元件、被動元件或其二者之組合。具體地，該主動元件係例如半導體晶片，而該被動元件係例如電阻、電容及電感。
再者，可於該開孔200中形成導電體24，使該半導體元件21之電極墊210藉由該導電體24結合並電性連接於各該電性接觸墊201a上。具體地，該導電體24係例如銀膠、紫外線硬化膠(俗稱UV膠)、異方性導電膜(Anisotropic Conductive Film，簡稱ACF)、焊料合金、無鉛焊料或錫金共晶焊料。
又，可於各該電性接觸墊201a上形成表面處理層25，以利於形成該導電體24。
所述之介電體22係設於該防焊層20上並包覆該半導體元件21。
於本實施例中，該介電體22係具有相對之第一表面 22a與第二表面22b，且該介電體22以其第一表面22a與該防焊層20相壓合。
再者，該介電體22係為膠含浸玻璃纖維織布(prepreg)，其由多層介電片所構成，且至少一層介電片可具有開口以容置該半導體元件21，使該半導體元件21嵌埋於該介電體22中。
因此，於製作該半導體封裝結構2時，例如，先將該線路層201形成於該防焊層20中，再設置該半導體元件21於該防焊層20上，之後壓合該介電體22與該防焊層20，使該介電體22包覆該半導體元件21。
第3A至3C圖係為本創作半導體封裝結構3a,3b,3c之其它不同實施例的剖面示意圖。
如第3A圖所示，於該半導體封裝結構3a中，可藉由移除該介電體22之第二表面22b之部分材質，使該半導體元件21之非作用面21b外露於該介電體22之第二表面22b’，以利於該半導體元件21之散熱。
於本實施例中，該半導體元件21之非作用面21b齊平該介電體22之第二表面22b。
如第3B圖所示，該半導體封裝結構3b復包括一金屬層26，係形成於該半導體元件21之非作用面21b上，且外露於該介電體22之第二表面22b(例如，該金屬層26之外露表面齊平該介電體22之第二表面22b)，以令該金屬層26作為散熱層、應力層或屏蔽層。
如第3C圖所示，於該半導體封裝結構3c中，藉由該 介電體20取代習知封裝膠體，該介電體22可形成有複數連通該第一與第二表面22a,22b之導電柱34，以電性連接該線路層201。
於本實施例中，該介電體22之第二表面22b上形成有一佈線層35，且該佈線層35藉由該些導電柱34電性連接該線路層201。
再者，該防焊層20係於其上側形成有複數另一開孔300，以令該線路層201之部分表面外露於該些開孔300，俾供結合及電性連接該導電柱34。
又，該佈線層35係可依需求設計為散熱層、線路層、應力層或屏蔽層等。
另外，藉由該介電體20取代習知封裝膠體，可於該介電體20之第二表面20b上選擇性設計，例如，可依需求設有線路增層結構(圖略)或堆疊其它如封裝件、晶片等之電子裝置(圖略)。
綜上所述，本創作之半導體封裝結構2,3a,3b,3c，主要藉由該防焊層20具有單一線路層201之設計以取代習知多層線路之基板或具核心層之基板，以降低該半導體封裝結構2,3a,3b,3c之厚度。
上述實施例係用以例示性說明本創作之原理及其功效，而非用於限制本創作。任何熟習此項技藝之人士均可在不違背本創作之精神及範疇下，對上述實施例進行修改。因此本創作之權利保護範圍，應如後述之申請專利範圍所列。
2‧‧‧半導體封裝結構
20‧‧‧防焊層
200,200’‧‧‧開孔
201‧‧‧線路層
201a‧‧‧電性接觸墊
21‧‧‧半導體元件
21a‧‧‧作用面
21b‧‧‧非作用面
210‧‧‧電極墊
22‧‧‧介電體
22a‧‧‧第一表面
22b‧‧‧第二表面
23‧‧‧導電元件
24‧‧‧導電體
25‧‧‧表面處理層

Claims (10)

  1. 一種半導體封裝結構，係包括：防焊層；線路層，係埋設於該防焊層中且部分外露於該防焊層；半導體元件，係設於該防焊層上，且具有相對之作用面與非作用面，其中，該半導體元件係藉其作用面電性連接外露於該防焊層之該線路層；以及介電體，係形成於該防焊層上以包覆該半導體元件。
  2. 如申請專利範圍第1項所述之半導體封裝結構，其中，該防焊層形成有複數開孔，以令部分該線路層外露於該些開孔。
  3. 如申請專利範圍第1項所述之半導體封裝結構，其中，該半導體元件之作用面具有複數電性連接該線路層之電極墊。
  4. 如申請專利範圍第3項所述之半導體封裝結構，其中，該些電極墊藉由導電體電性連接該線路層。
  5. 如申請專利範圍第4項所述之半導體封裝結構，其中，該導電體係為銀膠、紫外線硬化膠、異方性導電膜、焊料合金、無鉛焊料或錫金共晶焊料。
  6. 如申請專利範圍第1項所述之半導體封裝結構，其中，該半導體元件之非作用面外露於該介電體。
  7. 如申請專利範圍第1項所述之半導體封裝結構，其中， 該半導體元件之非作用面上形成有金屬層。
  8. 如申請專利範圍第1項所述之半導體封裝結構，其中，形成該介電體之材質係包含浸玻璃纖維織布。
  9. 如申請專利範圍第1項所述之半導體封裝結構，其中，該介電體中形成有至少一貫穿該介電體之導電柱，以電性連接該線路層。
  10. 如申請專利範圍第1項所述之半導體封裝結構，其中，該介電體上形成有佈線層。
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