TW201401451A - 半導體封裝結構 - Google Patents

半導體封裝結構 Download PDF

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TW201401451A
TW201401451A TW101128004A TW101128004A TW201401451A TW 201401451 A TW201401451 A TW 201401451A TW 101128004 A TW101128004 A TW 101128004A TW 101128004 A TW101128004 A TW 101128004A TW 201401451 A TW201401451 A TW 201401451A
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semiconductor
package structure
package substrate
semiconductor package
upper cover
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Po-Chun Lin
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Nanya Technology Corp
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    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
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    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
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    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/4824—Connecting between the body and an opposite side of the item with respect to the body
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    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
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    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
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    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49811—Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads
    • H01L23/49816—Spherical bumps on the substrate for external connection, e.g. ball grid arrays [BGA]
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Abstract

一種半導體封裝結構，包含有一封裝基板，具有一第一表面、一相對於該第一表面的第二表面，以及一介於該第一表面與該第二表面之間的側壁表面；一半導體元件，固定在該第一表面上；以及一上蓋膜封材，封包住至少該半導體元件，其中該上蓋膜封材包含一垂直延伸部，覆蓋住該側壁表面，以及一水平延伸部，扣住該封裝基板的該第二表面的一錫球植入區之邊緣。

Description

半導體封裝結構
本發明係有關於一種封裝結構技術，特別是有關於一種能降低翹曲(warpage)及避免脫層(delamination)之半導體封裝結構。
如熟習該項技藝者所知，半導體積體電路係利用薄膜沈積、離子佈植、蝕刻及光學微影等製程步驟製作在半導體晶圓上。完成晶圓上的積體電路後，接著進行晶圓測試及切割，其中晶圓切割通常是以切割刀進行。晶圓被切割成單獨的晶片，再與封裝基板或晶圓載板封裝成封裝體。封裝過程中，通常僅以模塑高分子樹脂封蓋住封裝基板的上表面及固定在上表面的晶片。
然而，過去作法其缺點在於封裝體的內部脫層問題。嚴重者可能導致較大的裂縫發生，容易使污染物侵入，危及晶片的可靠度。容易發生脫層問題的位置是在封裝基板與模塑樹脂之間的介面，可能是因為封裝基板與模塑樹脂之間的結合力不足所導致，或者因為熱膨脹係數不匹配所致，也有可能是因為切割過程中產生的應力。先前技術的另一問題是封裝體的翹曲現象，主要是熱應力及封裝結構的不平衡所導致。
本發明之主要目的提供改良的半導體封裝結構，以解決上述先前技藝之不足與缺點。
本發明之一實施例提供一種半導體封裝結構，包含有一封裝基板，具有一第一表面、一相對於該第一表面的第二表面，以及一介於該第一表面與該第二表面之間的側壁表面；一半導體元件，固定在該第一表面上；以及一上蓋膜封材，封包住至少該半導體元件，其中該上蓋膜封材包含一垂直延伸部，覆蓋住該側壁表面，以及一水平延伸部，扣住該封裝基板的該第二表面的一錫球植入區之邊緣。
為讓本發明之上述目的、特徵及優點能更明顯易懂，下文特舉較佳實施方式，並配合所附圖式，作詳細說明如下。然而如下之較佳實施方式與圖式僅供參考與說明用，並非用來對本發明加以限制者。
在下文中，將參照附圖說明本發明實施細節，該些附圖中之內容構成說明書一部份，並以可實行該實施例之特例描述方式繪示。下文實施例已揭露足夠的細節俾使該領域之一般技藝人士得以具以實施。當然，本發明中亦可採行其他的實施例，或是在不悖離文中所述實施例的前提下作出任何結構性、邏輯性、及電性上的改變。因 此，下文之細節描述將不欲被視為是一種限定，反之，其中所包含的實施例將由隨附的申請專利範圍來加以界定。
第1圖為依據本發明一實施例所繪示的半導體封裝結構之剖面示意圖。如第1圖所示，半導體封裝結構1a包含有一封裝基板10，具有一第一表面10a、一相對於第一表面10a的第二表面10c，以及一介於第一表面10a與第二表面10c之間的側壁表面10b。其中，側壁表面10b本質上垂直於第一表面10a與第二表面10c。封裝基板10可以是塑膠基板，其具有一絕緣核心層，例如，玻纖材料等，以及複數層導線及介電層。前述之複數層導線可以透過電鍍通孔彼此電性連結。另外，可以在第一表面10a與第二表面10c上形成防焊層(圖未示)，以保護最上層之導線。熟習該項技藝者應理解封裝基板10也可以是其它型式的基材，例如模塑化合物或環氧樹脂基材，而前述之防焊層亦可省略。
根據本發明之實施例，半導體元件20，例如半導體積體電路晶片，係固定在第一表面10a上的預定晶片安置區。半導體元件20可以利用一黏著層22固定在第一表面10a。根據本發明之實施例，半導體元件20包含一主動面20a，其上具有複數個接合墊202，這些接合墊202係經由複數條打線32與封裝基板10的第一表面10a上的金手指112電性連結。在其它實施例中，半導體元件20也可以採覆晶封裝方式，也就是將主動面20a翻轉朝下，利用凸塊等方式固定在第一表面10a。在封裝基板10的第二表面10c上則設有錫球植入區 200，在此錫球植入區200中設有複數個錫球40，分別形成在銲墊114上。
根據本發明之實施例，半導體元件20、打線32及至少部分的封裝基板10的第一表面10a係被一上蓋膜封材(mold cap)30封包住。此外，上蓋膜封材30還延伸到第二表面10c，並且包覆住前述錫球植入區200的周緣。在另一實施例中，前述之黏著層22可以被上蓋膜封材30取代。如第1圖所示，上蓋膜封材30包含一垂直延伸部30a，覆蓋住整個側壁表面10b，以及一水平延伸部30b，扣住封裝基板10底部邊緣，故可以抵抗封裝體翹曲應力。垂直延伸部30a連接上蓋膜封材30之本體與水平延伸部30b。由於垂直延伸部30a覆蓋住整個側壁表面10b，故可以避免脫層現象發生。
第2圖為依據本發明另一實施例所繪示的半導體封裝結構之剖面示意圖，其中仍沿用相同符號來表示相同的區域或元件。如第2圖所示，半導體封裝結構1b包含有一封裝基板10，具有一中央開口102。半導體元件20，例如DDR DRAM晶片，係面朝下固定在封裝基板10的第一表面10a。半導體元件20的主動面20a係經由複數條穿過中央開口102的打線32與封裝基板10的第二表面10a電性連結。同樣的，半導體元件20、打線32及至少部分的封裝基板10的第一表面10a係被一上蓋膜封材30封包住。上蓋膜封材30填滿中央開口102並形成突出部230。此外，上蓋膜封材30還延伸到第二表面10c，並且包覆住前述錫球植入區200的周緣。上蓋膜封材30包含 一垂直延伸部30a，覆蓋住整個側壁表面10b，以及一水平延伸部30b，扣住封裝基板10底部邊緣，故可以抵抗封裝體翹曲應力。垂直延伸部30a連接上蓋膜封材30之本體與水平延伸部30b。由於垂直延伸部30a覆蓋住整個側壁表面10b，故可以避免脫層現象發生。
以上所述僅為本發明之較佳實施例，凡依本發明申請專利範圍所做之均等變化與修飾，皆應屬本發明之涵蓋範圍。
1a‧‧‧半導體封裝結構
1b‧‧‧半導體封裝結構
10‧‧‧封裝基板
10a‧‧‧第一表面
10b‧‧‧側壁表面
10c‧‧‧第二表面
20‧‧‧半導體元件
20a‧‧‧主動面
22‧‧‧黏著層
30‧‧‧上蓋膜封材
30a‧‧‧垂直延伸部
30b‧‧‧水平延伸部
32‧‧‧打線
40‧‧‧錫球
102‧‧‧中央開口
112‧‧‧金手指
114‧‧‧銲墊
200‧‧‧錫球植入區
202‧‧‧接合墊
230‧‧‧突出部
第1圖為依據本發明一實施例所繪示的半導體封裝結構之剖面示意圖。
第2圖為依據本發明另一實施例所繪示的半導體封裝結構之剖面示意圖。
1a‧‧‧半導體封裝結構
10‧‧‧封裝基板
10a‧‧‧第一表面
10b‧‧‧側壁表面
10c‧‧‧第二表面
20‧‧‧半導體元件
20a‧‧‧主動面
22‧‧‧黏著層
30‧‧‧上蓋膜封材
30a‧‧‧垂直延伸部
30b‧‧‧水平延伸部
32‧‧‧打線
40‧‧‧錫球
112‧‧‧金手指
114‧‧‧銲墊
200‧‧‧錫球植入區
202‧‧‧接合墊

Claims (7)

  1. 一種半導體封裝結構，包含有：一封裝基板，具有一第一表面、一相對於該第一表面的第二表面，以及一介於該第一表面與該第二表面之間的側壁表面；一半導體元件，固定在該第一表面上；以及一上蓋膜封材，封包住至少該半導體元件，其中該上蓋膜封材包含一垂直延伸部，覆蓋住該側壁表面，以及一水平延伸部，扣住該封裝基板的該第二表面的一錫球植入區之邊緣。
  2. 如申請專利範圍第1項所述之半導體封裝結構，其中該垂直延伸部連接該上蓋膜封材之本體與該水平延伸部。
  3. 如申請專利範圍第1項所述之半導體封裝結構，其中該封裝基板包含有一開口。
  4. 如申請專利範圍第3項所述之半導體封裝結構，其中另包含複數條打線，將該半導體元件電性連結至該封裝基板。
  5. 如申請專利範圍第4項所述之半導體封裝結構，其中該打線穿過該開口。
  6. 如申請專利範圍第1項所述之半導體封裝結構，其中另包含一黏 著層，將該半導體元件固著於該封裝基板的該第一表面。
  7. 如申請專利範圍第1項所述之半導體封裝結構，其中另包含一防焊層，覆蓋住該第一表面或該第二表面。
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