CN103515333A - 半导体封装结构 - Google Patents

半导体封装结构 Download PDF

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CN103515333A
CN103515333A CN201210438441.0A CN201210438441A CN103515333A CN 103515333 A CN103515333 A CN 103515333A CN 201210438441 A CN201210438441 A CN 201210438441A CN 103515333 A CN103515333 A CN 103515333A
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林柏均
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Nanya Technology Corp
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Abstract

本发明公开了一种半导体封装结构，包含有一封装基板，具有一第一表面、一相对于所述第一表面的第二表面，以及一介于所述第一表面与所述第二表面之间的侧壁表面；一半导体器件，固定在所述第一表面上；以及一上盖膜封材，至少封住所述半导体器件，其中所述上盖膜封材包含一垂直延伸部，覆盖住所述侧壁表面，以及一水平延伸部，扣住所述封装基板第二表面的一植球区的边缘。

Description

半导体封装结构
技术领域
本发明涉及一种封装结构技术，特别是涉及一种能降低翘曲(warpage)及避免脱层(delamination)的半导体封装结构。
背景技术
如本领域技术的一般技术人员所知，半导体集成电路是利用薄膜沉积、离子注入、刻蚀及光刻等工艺步骤制作在半导体晶圆上。完成晶圆上的集成电路后，接着进行晶圆测试及切割，其中晶圆切割通常是以切割刀进行。晶圆被切割成单独的芯片，再与封装基板或晶圆载板封装成封装体。封装过程中，通常仅以模塑高分子树脂封盖住封装基板的上表面及固定在上表面的芯片。
然而，过去作法其缺点在于封装体的内部脱层(delamination)问题。严重者可能导致较大的裂缝发生，容易使污染物侵入，危及芯片的可靠度。容易发生脱层问题的位置是在封装基板与模塑树脂之间的界面，可能是因为封装基板与模塑树脂之间的结合力不足所导致，或者因为热膨胀系数不匹配所致，也有可能是因为切割过程中产生的应力。先前技术的另一问题是封装体的翘曲现象，主要是热应力及封装结构的不平衡所导致。
发明内容
本发明的主要目的为提供一种改良的半导体封装结构，以解决上述现有技术的不足与缺点。
本发明的一实施例提供一种半导体封装结构，包含有一封装基板，具有一第一表面、一相对于所述第一表面的第二表面，以及一介于所述第一表面与所述第二表面之间的侧壁表面；一半导体器件，固定在所述第一表面上；以及一上盖膜封材，至少封住所述半导体器件，其中所述上盖膜封材包含一垂直延伸部，覆盖住所述侧壁表面，以及一水平延伸部，扣住所述封装基板第二表面的一植球区的边缘。
为让本发明的上述目的、特征及优点能更明显易懂，下文特举优选实施方式并配合所附图式作详细说明如下。然而下文中的优选实施方式与图式仅供参考与说明用，并非用来对本发明加以限制。
附图说明
图1为依据本发明一实施例所绘示的半导体封装结构的横断面示意图。
第2图为依据本发明另一实施例所绘示的半导体封装结构的横断面示意图。
其中，附图标记说明如下：
1a    半导体封装结构    30a    垂直延伸部
1b    半导体封装结构    30b    水平延伸部
10    封装基板          32     焊线
10a   第一表面          40     锡球
10b   侧壁表面          102    中央开口
10c   第二表面          112    金手指
20    半导体器件        114    焊垫
20a   有源面            200    植球区
22    黏着层            202    接合垫
30    上盖膜封材        230    突出部
具体实施方式
下文中将参照附图来说明本发明实施细节，该些附图中的内容构成说明书一部份，并以可实行该实施例的特例描述方式绘示。下文实施例已揭露足够的细节可使所属技术领域的一般技术人员得以具以实施。当然，本发明中也可实行其它的实施例，或是在不悖离文中所述实施例的前提下作出任何结构性、逻辑性、及电性上的改变。因此，下文的细节描述将不欲被视为是一种限定，反之，其中所包含的实施例将由权利要求书来加以界定。
图1为依据本发明一实施例所绘示的半导体封装结构的横断面示意图。如图1所示，半导体封装结构1a包含有一封装基板10，具有一第一表面10a、一相对于第一表面10a的第二表面10c，以及一介于第一表面10a与第二表面10c之间的侧壁表面10b。其中，侧壁表面10b本质上垂直于第一表面10a与第二表面10c。封装基板10可以是塑料基板，其具有一绝缘核心层，例如，玻璃纤维材料等，以及多层导线及介电层。前述的多层导线可以通过电镀通孔彼此电性连结。另外，可以在第一表面10a与第二表面10c上形成防焊层(未示于图中)，以保护最上层的导线。本项技艺的一般技术人员应能理解封装基板10也可以是其它型式的基材，例如模塑化合物或环氧树脂基材，而前述的防焊层也可省略。
根据本发明的实施例，半导体器件20，例如半导体集成电路芯片，是固定在第一表面10a上的预定芯片安置区。半导体器件20可以利用一黏着层22固定在第一表面10a。根据本发明的实施例，半导体器件20包含一有源面20a，其上具有多个接合垫202，这些接合垫202是经由多条焊线32与封装基板10的第一表面10a上的金手指112电性连结。在其它实施例中，半导体器件20也可以采倒装芯片(flip chip)封装方式，也就是将有源面20a翻转朝下，利用凸块等方式固定在第一表面10a。在封装基板10的第二表面10c上则设有植球区200，在此植球区200中设有多个锡球40，分别形成在焊垫114上。
根据本发明的实施例，半导体器件20、焊线32及至少部分的封装基板10的第一表面10a被一上盖膜封材(mold cap)30封住。此外，上盖膜封材30还延伸到第二表面10c，并且包覆住前述植球区200的周缘。在另一实施例中，前述的黏着层22可以被上盖膜封材30取代。如图1所示，上盖膜封材30包含一垂直延伸部30a，覆盖住整个侧壁表面10b，以及一水平延伸部30b，扣住封装基板10底部边缘，故可以抵抗封装体的翘曲应力。垂直延伸部30a连接上盖膜封材30的本体与水平延伸部30b。由于垂直延伸部30a覆盖住整个侧壁表面10b，故可以避免脱层现象发生。
图2为依据本发明另一实施例所绘示的半导体封装结构的横断面示意图，其中仍沿用相同的组件符号来表示相同的区域或组件。如图2所示，半导体封装结构1b包含有一封装基板10，具有一中央开口102。半导体器件20，例如DDR DRAM芯片，是以面朝下方式固定在封装基板10的第一表面10a。半导体器件20的有源面20a经由多条穿过中央开口102的焊线32与封装基板10的第二表面10a电性连结。同样的，半导体器件20、焊线32及至少部分的封装基板10的第一表面10a被一上盖膜封材30封住。上盖膜封材30填满中央开口102并形成突出部230。此外，上盖膜封材30还延伸到第二表面10c，并且包覆住前述植球区200的周缘。上盖膜封材30包含一垂直延伸部30a，覆盖住整个侧壁表面10b，以及一水平延伸部30b，扣住封装基板10底部边缘，故可以抵抗封装体的翘曲应力。垂直延伸部30a连接上盖膜封材30的本体与水平延伸部30b。由于垂直延伸部30a覆盖住整个侧壁表面10b，故可以避免脱层现象发生。
以上所述仅为本发明的优选实施例而已，并不用于限制本发明，对于本领域的技术人员来说，本发明可以有各种更改和变化。凡在本发明的精神和原则之内，所作的任何修改、等同替换、改进等，均应包含在本发明的保护范围之内。

Claims (7)

1.一种半导体封装结构，其特征在于，包含：
一封装基板，具有一第一表面、一相对于所述第一表面的第二表面，以及一介于所述第一表面与所述第二表面之间的侧壁表面；
一半导体器件，固定在所述第一表面上；以及
一上盖膜封材，至少封住所述半导体器件，其中所述上盖膜封材包含一垂直延伸部，覆盖住所述侧壁表面，以及一水平延伸部，扣住所述封装基板的第二表面的一植球区的边缘。
2.根据权利要求1所述的半导体封装结构，其特征在于，所述垂直延伸部连接所述上盖膜封材的本体与所述水平延伸部。
3.根据权利要求1所述的半导体封装结构，其特征在于，所述封装基板包含有一开口。
4.根据权利要求3所述的半导体封装结构，其特征在于，另包含多条焊线，将所述半导体器件电性连结至所述封装基板。
5.根据权利要求4所述的半导体封装结构，其特征在于，所述焊线穿过所述开口。
6.根据权利要求1所述的半导体封装结构，其特征在于，另包含一黏着层，将所述半导体器件固着在所述封装基板的第一表面。
7.根据权利要求1所述的半导体封装结构，其特征在于，另包含一防焊层，覆盖住所述第一表面或所述第二表面。
CN201210438441.0A 2012-06-25 2012-11-06 半导体封装结构 Pending CN103515333A (zh)

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Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN104617077A (zh) * 2015-01-26 2015-05-13 华为技术有限公司 封装基板和集成电路芯片
CN105789146A (zh) * 2014-12-16 2016-07-20 中芯国际集成电路制造(上海)有限公司 一种堆叠式芯片封装结构
CN107895716A (zh) * 2017-10-30 2018-04-10 睿力集成电路有限公司 用于制造半导体芯片的方法及半导体封装构造
CN109524365A (zh) * 2017-09-18 2019-03-26 台湾积体电路制造股份有限公司 半导体结构及其制作方法

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CN105789146A (zh) * 2014-12-16 2016-07-20 中芯国际集成电路制造(上海)有限公司 一种堆叠式芯片封装结构
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CN109524365A (zh) * 2017-09-18 2019-03-26 台湾积体电路制造股份有限公司 半导体结构及其制作方法
CN109524365B (zh) * 2017-09-18 2022-06-14 台湾积体电路制造股份有限公司 半导体结构及其制作方法
CN107895716A (zh) * 2017-10-30 2018-04-10 睿力集成电路有限公司 用于制造半导体芯片的方法及半导体封装构造
CN107895716B (zh) * 2017-10-30 2019-01-15 长鑫存储技术有限公司 用于制造半导体芯片的方法及半导体封装构造

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