CN106935559A - 半导体封装 - Google Patents

半导体封装 Download PDF

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Publication number
CN106935559A
CN106935559A CN201611252323.5A CN201611252323A CN106935559A CN 106935559 A CN106935559 A CN 106935559A CN 201611252323 A CN201611252323 A CN 201611252323A CN 106935559 A CN106935559 A CN 106935559A
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semiconductor chip
mark
encapsulation
lower semiconductor
molding layer
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Application number
CN201611252323.5A
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CN106935559B (zh
Inventor
权兴奎
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Samsung Electronics Co Ltd
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Samsung Electronics Co Ltd
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  • Engineering & Computer Science (AREA)
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  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Manufacturing & Machinery (AREA)
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Abstract

提供一种层叠封装型半导体封装及其制造方法。所述半导体封装包括：上部封装，叠加在下部封装上；以及导通结构，设置在所述下部封装与所述上部封装之间，以将所述下部封装与所述上部封装彼此电连接。所述下部封装包括：下部封装基板；下部半导体芯片，安装在所述下部封装基板上；以及下部模塑层，囊封所述下部半导体芯片并包括对准标记。所述下部模塑层包括标记区，所述标记区设置在所述导通结构及所述下部半导体芯片之间，且在所述标记区上设置有所述对准标记。

Description

半导体封装
相关申请的交叉参考
在2015年12月31日在韩国知识产权局提出申请且标题为“层叠封装型半导体封装及其制造方法”的韩国专利申请第10-2015-0190833号全文并入本文供参考。
技术领域
本发明涉及一种半导体装置，且具体地说，涉及一种层叠封装型(package-on-package type)半导体封装及其制造方法。
背景技术
通常在覆盖半导体芯片的模塑层上执行用于在半导体封装上作出对准标记的激光标记工艺。激光的使用可能导致半导体芯片的损坏。可以通过在激光标记工艺中降低激光束的强度来防止半导体芯片的这种损坏，但这种方法可导致在封装叠加工艺中标记的可见性降低且良率降低。
发明内容
根据某些实施例，一种半导体封装可包括：上部封装，叠加在下部封装上；以及导通结构(via)，设置在所述下部封装与所述上部封装之间，以将所述下部封装与所述上部封装彼此电连接。所述下部封装可包括：下部封装基板；下部半导体芯片，安装在所述下部封装基板上；以及下部模塑层，囊封所述下部半导体芯片且包括对准标记。所述下部模塑层可包括标记区，所述标记区设置在所述导通结构与所述下部半导体芯片之间，且在所述标记区上设置有所述对准标记。
根据某些实施例，一种半导体封装可包括：下部封装，包括安装在下部封装基板上的且被下部模塑层囊封的至少一个下部半导体芯片；上部封装，包括安装在上部封装基板上的且被上部模塑层囊封的至少一个上部半导体芯片；以及导通结构，将所述下部封装电连接至所述上部封装。所述下部模塑层可包括设置在所述导通结构与所述下部半导体芯片之间的标记区。此处，所述标记区可包括：旋转对准标记，被配置成使所述下部封装与所述上部封装具有相同的取向(orientation)；以及垂直对准标记，被配置成使所述下部封装的中心与所述上部封装的中心彼此对准。
根据某些实施例，一种半导体封装可包括：下部封装，包括安装在下部封装基板上的下部半导体芯片；及下部模塑层，被设置成囊封所述下部半导体芯片；以及上部封装，垂直地叠加在所述下部封装上并经由垂直地穿过所述下部模塑层的多个导通结构电连接至所述下部封装。所述下部模塑层可包括顶表面，所述顶表面面对所述上部封装且具有至少一个辨认标记，所述辨认标记可设置在所述下部模塑层的一部分上，且所述下部模塑层的所述部分可设置在所述下部半导体芯片与所述导通结构之间以覆盖所述下部半导体芯片的侧表面。
根据某些实施例，一种制造半导体封装的方法可包括：设置下部封装；在所述下部封装上设置上部封装；以及将所述下部封装电连接至所述上部封装。设置所述下部封装可包括：在下部封装基板上设置下部半导体芯片及与所述下部半导体芯片间隔开的下部端子；在所述下部封装基板上设置囊封所述下部半导体芯片及所述下部端子的下部模塑层；将第一激光照射至所述下部模塑层上以形成暴露出所述下部端子的导通孔；以及将第二激光照射至所述下部模塑层上以形成激光标记。所述激光标记可形成在激光标记区上，所述激光标记区是所述下部模塑层的位于所述导通孔与所述下部半导体芯片之间的部分。
根据某些实施例，一种制造半导体封装的方法可包括：设置下部封装；在所述下部封装上设置上部封装；以及将所述下部封装与所述上部封装彼此电连接。设置所述下部封装可包括：在下部封装基板上设置下部半导体芯片及与所述下部半导体芯片间隔开的下部端子；在所述下部封装基板上设置下部模塑层以囊封所述下部半导体芯片及所述下部端子；移除所述下部模塑层的一部分以形成暴露出所述下部端子的导通孔；以及移除所述下部模塑层的另一部分以在所述下部半导体芯片与所述导通孔之间形成辨认标记。所述导通孔及所述辨认标记可在单个工艺中在原处形成。
根据某些实施例，一种制造半导体封装的方法可包括：设置下部封装；在所述下部封装上设置上部封装；以及将所述下部封装电连接至所述上部封装。设置所述下部封装可包括：在下部封装基板上设置下部半导体芯片及与所述下部半导体芯片间隔开的下部端子；在所述下部封装基板上设置下部模塑层以囊封所述下部半导体芯片及所述下部端子；将激光照射至覆盖所述下部端子的所述下部模塑层的第一部分上，以形成暴露出所述下部端子的导通孔；以及将激光照射至所述下部模塑层的位于所述下部端子与所述下部半导体芯片之间的第二部分上以形成辨认标记。所述导通孔及所述辨认标记可通过在同一设备中利用相同的激光所执行的单个工艺来形成。
根据某些实施例，一种半导体封装可包括：上部封装，叠加在下部封装上；以及导通结构，位于所述下部封装与所述上部封装之间，以将所述下部封装与所述上部封装彼此电连接，其中所述下部封装包括位于下部封装基板上的下部半导体芯片以及囊封所述下部半导体芯片的下部模塑层，所述下部模塑层具有位于所述导通结构与所述下部半导体芯片的侧向表面之间的对准标记，所述对准标记在水平方向上与所述导通结构及所述下部半导体芯片的所述侧向表面中的每一个间隔开。
附图说明
通过参照附图详细阐述示例性实施例，各特征将对所属领域的普通技术人员而言变得显而易见，在附图中：
图1A、图2A、图3A、图4A、图5A、及图6A说明根据某些实施例的制造半导体封装的方法的各阶段的剖视图。
图1B、图2B、图3B、图4B、图5B、及图6B说明半导体封装在分别与图1A、图2A、图3A、图4A、图5A、及图6A对应的各制造阶段的俯视平面图。
图3C及图3D说明图3A所示的部分的放大剖视图。
图3E及图3F说明图3B所示的其他实例的平面图。
图7A至图7H说明图6A所示的其他实例的剖视图。
附图标记说明
1、2、3、4、5、6、7、8、9：半导体封装
90：第一激光
92：第二激光
100：下部封装
101：下部封装基板
101a：下部封装基板的顶表面
101b：下部封装基板的底表面
103：外部端子
110：下部半导体芯片
110a：下部半导体芯片的顶表面
110b：下部半导体芯片的底表面
110s：下部半导体芯片的侧表面/最外侧表面
111a：第一下部半导体芯片/下部半导体芯片
111b：第二下部半导体芯片/下部半导体芯片
112：连接端子
114：底部填充层
116：传热层
117、212：键合线
118：无源装置
119：贯穿电极
120：下部端子
130、131：下部模塑层
130a、131a：下部模塑层的顶表面
130m：标记区
130p：下部模塑层的部分/部分
135、136：导通孔
135s：导通孔的内侧表面
200：上部封装
201：上部封装基板
201a：上部封装基板的顶表面
201b：上部封装基板的底表面
210：上部半导体芯片
213：绝缘粘着层
220：上部端子
230：上部模塑层
320：导通结构
400：标记
400f：标记的底表面
410：第一标记
420：第二标记
510：对准标记
C1：下部封装的中心点
C2:上部封装的中心点
D：平移路径/平移移动
L：旋转移动
T1：第一厚度
T2：第二厚度
XC1：下部假想线
XC2:上部假想线。
具体实施方式
[制造半导体封装的方法]
图1A、图2A、图3A、图4A、图5A、及图6A是说明根据某些实施例的制造半导体封装的方法的各阶段的剖视图。图1B、图2B、图3B、图4B、图5B、及图6B是说明半导体封装在分别由图1A、图2A、图3A、图4A、图5A、及图6A示出的各制造阶段的俯视平面图。图3C及图3D是图3A所示的部分的放大剖视图。图3E及图3F是图3B所示的其他实例的平面图。
参照图1A及图1B，可设置具有顶表面101a及底表面101b的下部封装基板101。下部封装基板101可为例如印刷电路板(printed circuit board，PCB)。可在下部封装基板101的顶表面101a上安装(例如，以倒装芯片键合(flip-chip bonding)方式安装)下部半导体芯片110，且可形成下部模塑层130以囊封下部半导体芯片110。举例来说，可通过模具底部填充(mold underfill，MUF)工艺形成环氧模塑料(epoxy molding compound，EMC)在下部封装基板101上来形成下部模塑层130。下部模塑层130可充当囊封下部半导体芯片110的模塑结构(molding structure)且还可充当填充下部封装基板101与下部半导体芯片110之间的间隙区的底部填充物。
下部模塑层130可具有厚到足以使下部模塑层130覆盖下部半导体芯片110的顶表面110a的第一厚度T1。换句话说，相对于下部封装基板101的顶表面101a而言，下部模塑层130的顶表面130a可高于下部半导体芯片110的的顶表面110a。在某些实施例中，下部半导体芯片110的顶表面110a可用作非有源表面(inactive surface)，且与其相对的底表面110b可用作有源表面(active surface)。在某些实施例中，下部半导体芯片110的顶表面110a可用作有源表面，且底表面110b可用作非有源表面。在下部半导体芯片110的顶表面110a与下部模塑层130的顶表面130a之间，下部模塑层130可具有比第一厚度T1薄的第二厚度T2。下部半导体芯片110可通过多个连接端子112(例如，焊料凸块)电连接至下部封装基板101。下部半导体芯片110可为例如存储器芯片、逻辑芯片或其任何组合中的一个。举例来说，下部半导体芯片110可为片上系统(system-on-chip，SOC)。
可进一步在下部封装基板101的顶表面101a上形成多个下部端子120(例如，焊料球)。下部端子120可被下部模塑层130完全覆盖，而因此下部端子120可以不被暴露于外部。举例来说，下部端子120可具有实质上等于或小于下部模塑层130的第一厚度T1的厚度(例如，高度)。在某些实施例中，如图1B所示，可在下部封装基板101的顶表面101a的边缘区上(例如，沿周边)形成下部端子120，以对设置在下部封装基板101的顶表面101a的中心区上的下部半导体芯片110进行侧向地封闭(例如，围绕下部半导体芯片110的周边)、或被形成为具有环形的排列。在某些实施例中，下部端子120可被排列成与下部半导体芯片110的侧表面中的至少一个平行或被排列形成至少一个列。
参照图2A及图2B，可对下部模塑层130进行图案化以形成暴露出下部端子120的多个导通孔(via holes)135(例如，每一导通孔135可暴露出对应的下部端子120)。导通孔135可被形成为具有与下部模塑层130的第一厚度T1对应的(例如，相等的)的深度。在某些实施例中，如在图2B中所示，导通孔135的形成可包括对下部模塑层130进行图案化(例如，通过利用第一激光90的钻孔工艺)以形成在平面图中观察时为圆形的或相似形状的开口。导通孔135的排列可依赖于下部端子120的排列。举例来说，导通孔135可被形成为具有侧向地封闭下部半导体芯片110的环形排列。在某些实施例中，导通孔135可被排列成与下部半导体芯片110的侧表面中的至少一个平行或被排列形成至少一个列。
导通孔135可被形成为具有大到足以完全暴露出下部端子120的尺寸或直径，且导通孔135的内侧表面135s可以不接触到下部端子120。导通孔135的内侧表面135s可在自下部模塑层130的顶表面130a朝向下部封装基板101的顶表面101a的方向上具有向下的斜坡。举例来说，当在剖视图中观察时，导通孔135可在朝向下部封装基板101的顶表面101a的方向上具有减小的水平宽度或向下的锥形结构。在某些实施例中，不同于图2A，导通孔135的内侧表面135s可垂直于下部封装基板101的顶表面101a。
参照图3A及图3B，可利用第二激光92在标记区130m(其为下部模塑层130的一部分)上形成(例如，直接地形成)标记400。因此，下部封装100可包括下部封装基板101、安装在下部封装基板101上的下部半导体芯片110以及覆盖下部半导体芯片110并具有标记400的下部模塑层130。
详细地说，可将标记区130m设置在与下部半导体芯片110相邻的导通孔135与下部半导体芯片110的侧表面110s之间。举例来说，如图3A中所示，标记区130m可被界定于下部模塑层130的位于下部半导体芯片110的最外侧表面110s与和下部半导体芯片110最邻近的导通孔135之间的一部分中。举例来说，标记区130m可位于下部模塑层130的不与下部半导体芯片110的顶表面110a重叠的一部分中。标记区130m可沿下部半导体芯片110的侧表面110s中的至少一个设置。举例来说，当在平面图(图3B)中观察时，标记区130m可被设置(例如，连续地设置)成封闭(例如，完全围绕)下部半导体芯片110的侧表面110s或具有环形形状(例如，标记区130m可被界定在位于图3B中围绕下部半导体芯片110的两个最外虚线框之间)。
如图3C所示，设置在下部半导体芯片110的顶表面110a上的下部模塑层130的部分130p可具有小于第一厚度T1的第二厚度T2。因此，假如在激光标记工艺期间朝与下部半导体芯片110重叠的下部模塑层130的部分130p照射第二激光92，则由于所述部分130p的厚度小(即，第二厚度T2的厚度小)，第二激光92可能穿过下部模塑层130的部分130p，从而损坏位于部分130p下面的下部半导体芯片110。假如降低第二激光92的强度或能量(例如，降低至低于第一激光90的强度或能量)，则因此导致产生的标记可能具有降低的可见性，从而在后续对准工艺中造成低精确度。
因此，根据实施例，选择下部模塑层130的位于下部半导体芯片110外的部分作为标记区130m，从而使标记区130m具有大于第二厚度T2的厚度(即，第一厚度T1)。由于标记区130m的厚度(即，第一厚度T1)大，因此可在不损坏下部半导体芯片110(即，抑制或防止在激光标记工艺中发生工艺故障)的条件下在下部模塑层130上提供具有充分可见性的标记400。举例来说，如图3D中所示，可利用第二激光92在标记区130m中执行激光标记工艺以形成底表面400f比下部半导体芯片110的顶表面110a低的标记400。即使在这种情形中，也可防止下部半导体芯片110受到损坏。此外，可使标记400具有较大的深度(即，进一步降低底表面400f的垂直水平高度)且因此提高标记400的可见性。
根据某些实施例，下部模塑层130的用于导通孔135的部分与用于标记400的部分可具有实质上相同的厚度(即，第一厚度T1)，且导通孔135与标记400二者可利用具有相同的强度或能量的激光来形成。举例来说，分别用于形成导通孔135及标记400的第一激光90及第二激光92可具有相同的能量及/或可从相同的激光源产生。然而，在某些实施例中，第二激光92可具有低于第一激光90的能量。
分别利用第一激光90及第二激光92形成的导通孔135及标记400可在同一工艺期间在同一设备中形成。举例来说，可利用第一激光90来形成导通孔135，且接着，可利用从与第一激光90相同的激光源产生的第二激光92在原处(即，在同一设备中)形成标记400。在某些实施例中，可利用相同的激光束、以实质上同时的方式来形成导通孔135及标记400。在某些实施例中，可形成标记400，且接着，可在与标记400相同的设备中形成导通孔135。第一激光90及第二激光92的照射时间可存在差异。举例来说，第二激光92的照射时间可短于第一激光90的照射时间。
标记400可包括第一标记410及第二标记420中的至少一个，如图3B所示。第一标记410可具有各种形状(例如，圆形、十字形、X形十字形、字母“L”形、多边形等)。第二标记420也可具有各种形状(例如，圆形、十字形、X形十字形、字母“L”形、多边形等)，但可不同于第一标记410的形状。在某些实施例中，第一标记410与第二标记420可具有相同的形状，但具有不同的大小。举例来说，第一标记410可为大的圆形，而第二标记420可为小的圆形。在某些实施例中，标记400可如图3B所示包括至少一个第一标记410及至少两个第二标记420，但实施例并不仅限于此。
标记400可被形成为与下部半导体芯片110的隅角或侧表面相邻。当在平面图中观察时，第一标记410可被形成为与下部半导体芯片110的左上隅角相邻。第二标记420可被形成为与下部半导体芯片110的两个相对的隅角相邻。举例来说，第二标记420可被形成为与下部半导体芯片110的左下隅角及右上隅角相邻。作为实例，第二标记420可位于穿过下部半导体芯片110的左下隅角及右上隅角的对角线上。
第二标记420可用以界定下部封装100的中心点C1且可用于下部封装100与叠加在其上的半导体装置之间的垂直对准(vertical alignment)。第一标记410可用于半导体装置相对于下部封装100的旋转对准(rotational alignment)。将参照图5A及图5B阐述垂直对准及旋转对准。
作为另一实例，三个第二标记420可被形成为与下部半导体芯片110的三个隅角相邻，如图3E所示。视需要，当形成标记400时，下部封装100的产品信息可标记(例如，以字母或数字形式)在下部模塑层130上。作为实例，制造商的名称(例如，“三星(SAMSUNG)”)及/或产品型号名称(例如，“猎户座(EXYNOS)”)可额外形成在标记区130m上。
作为另一实例，标记400可包括被形成为与下部半导体芯片110的两个相对的对角隅角(diagonal corners)相邻的第一标记410及第二标记420，如图3F所示。第一标记410及第二标记420可位于穿过下部半导体芯片110的两个相对的对角隅角的对角线上。第一标记410可用于半导体装置相对于下部封装100的旋转对准，且第二标记420与第一标记410一起可用以界定下部封装100的中心点C1。
参照图4A及图4B，可设置上部封装200。上部封装200可包括：上部封装基板201，具有顶表面201a及底表面201b；一或多个上部半导体芯片210，安装在上部封装基板201的顶表面201a上；上部模塑层230，被设置成囊封上部半导体芯片210；以及多个上部端子220，附着至上部封装基板201的底表面201b。
上部封装基板201可为例如印刷电路板(PCB)。上部模塑层230可包括例如环氧模塑料。上部端子220可包括例如焊料球。上部半导体芯片210可通过例如多个键合线212而电连接至上部封装基板201。上部半导体芯片210可为例如存储器芯片、逻辑芯片或其任何组合中的一个。作为实例，上部半导体芯片210可为存储器芯片。上部半导体芯片210可通过绝缘粘着层213而彼此附着及附着至上部封装基板201。当上部封装200叠加在下部封装100上时，上部端子220可以一对一的方式连接至下部端子120。
上部端子220可被形成为具有与下部端子120相同或相似的排列。举例来说，如图4B中所示，上部端子220可在上部封装基板201的底表面201b的边缘区上形成为具有环形的排列。上部封装基板201的底表面201b可被形成为具有或界定对准标记510。对准标记510可被形成为能够实现上部封装200与下部封装100之间的精确的垂直对准。举例来说，对准标记510可被设置成能够实现第一标记410与对准标记510之间的垂直对准，以确保下部封装100与上部封装200之间的垂直对准。
参照图5A及图5B，上部封装200可叠加在下部封装100上。举例来说，上部封装200可被叠加在下部封装100上使得垂直地穿过下部封装100的中心点C1的下部假想线XC1与垂直地穿过上部封装200的中心点C2的上部假想线XC2重合且使得对准标记510与第一标记410垂直地对准。
在上部封装200不与下部封装100垂直地对准的情形中，可能需要改变下部封装100与上部封装200中的一个相对于另一个的水平位置。举例来说，当上部封装200安置在下部封装100上时，下部假想线XC1可能不与上部假想线XC2重合及/或第一标记410可能不与对准标记510对准。在这种情形中，为了使下部封装100的中心点C1与上部封装200的中心点C2彼此重合，可沿平移路径(如图5B中的D所绘示)移动上部封装200。如果下部封装100的中心点C1与上部封装200的中心点C2彼此重合，则可以上部假想线XC2(如由L所绘示)为中心旋转上部封装200以使第一标记410与对准标记510重合。因此，可实现下部端子120与上部端子220之间的正确的垂直对准、防止在下部封装100与上部封装200之间发生叠加失败(stacking failure)、且因此提高叠加工艺的良率。在某些实施例中，可同时地执行上部封装200的平移移动及旋转移动(例如，D及L)以将上部封装200与下部封装100对准。
参照图6A及图6B，可对于将上部封装200叠加在下部封装100上所得的结构执行回流工艺(reflow process)，以形成将下部封装100电连接至上部封装200的多个导通结构320。举例来说，上部端子220可被安置成与下部端子120接触，且接着，可执行回流工艺以形成导通结构320，其中导通结构320中的每一个包括彼此连接的上部端子220中的一个及下部端子120中的一个。
在某些实施例中，在导通孔135的内侧表面135s与导通结构320之间可能形成空的空间。空的空间的形成可使气体或烟在回流工艺期间从图5A所示的下部端子120及上部端子220中容易地排出。外部端子103(例如，焊料球)可进一步附着至下部封装基板101的底表面101b。
作为以上工艺的结果，可制造其中设置有通过导通结构320而彼此电连接的下部封装100及上部封装200的层叠封装型半导体封装1。根据某些实施例，可形成下部模塑层130来覆盖下部封装基板101的顶表面101a的大部分，从而抑制或防止下部封装100的翘曲。半导体封装1可用作包括便携式产品(例如，移动电话)或可穿戴式产品(例如，智能手表)在内的各种电子产品的一部分。
[半导体封装的其他实例]
图7A至图7H是说明图6A所示的其他实例的剖视图。
参照图7A，半导体封装2可进一步包括底部填充层114。作为实例，下部半导体芯片110可安装在下部封装基板101上，且接着，在形成下部模塑层130之前，可设置绝缘材料(例如，热压缩非导电性膏(thermal compression non-conductive paste，TCNCP)或热压缩非导电性膜(thermal compression non-conductive film，TCNCF))来形成底部填充层114。底部填充层114可被设置成填充下部半导体芯片110与下部封装基板101之间的间隙且可保护下部封装100不受由有害外部环境(例如，热应力)造成的损坏。
参照图7B，半导体封装3可进一步包括设置在下部封装100与上部封装200之间的传热层116。传热层116可设置在下部模塑层130与上部封装基板201之间且可用以改善半导体封装3的散热特性。传热层116可包括热界面材料(thermal interface material，TIM)。在某些实施例中，除非传热层116覆盖第一标记410及/或第二标记420(例如，参见图6B)，否则传热层116的大小或形状可进行各种改变。
参照图7C，半导体封装4可包括被形成为暴露出下部半导体芯片110的顶表面110a的下部模塑层131。作为实例，下部模塑层131的形成可包括在下部封装基板101上设置模塑材料且使模塑材料不覆盖下部半导体芯片110的顶表面110a。作为另一实例，下部模塑层131的形成可包括：形成下部模塑层130以覆盖下部半导体芯片110的顶表面110a，如图1A中所示；以及研磨下部模塑层130以暴露出下部半导体芯片110的顶表面110a。下部半导体芯片110的顶表面110a可与下部模塑层131的顶表面131a共面。根据本实施例，可抑制在下部封装100与上部封装200之间形成间隙并从而减小半导体封装4的总厚度。再者，如图7C中所示，第一标记410可形成在标记区130m(图3B)(即，不与下部半导体芯片110的顶表面重叠的区)中的下部模塑层131的顶表面131a中。
参照图7D，导通结构320可以填充半导体封装5的导通孔136，且在导通结构320与导通孔136之间不存在任何间隙。举例来说，在图2A所示的阶段中，可通过局部地暴露出下部端子120的上部部分来形成导通孔136。在这种情形中，在图6A所示的回流工艺期间，可形成导通结构320来填充导通孔136。
参照图7E，半导体封装6可包括安装在下部封装基板101上的多个下部半导体芯片110。下部半导体芯片110可安置在下部封装基板101的顶表面101a上且可彼此侧向地间隔开。
参照图7F，半导体封装7可进一步包括安装在下部封装基板101上的至少一个无源装置118(例如，电容器或电感器)。无源装置118可安置在下部封装基板101的顶表面101a上且可与下部半导体芯片110侧向地间隔开。
参照图7G，半导体封装8可包括叠加在下部封装基板101上的多个下部半导体芯片(例如，第一下部半导体芯片111a及第二下部半导体芯片111b)。第一下部半导体芯片111a可包括至少一个贯穿电极119。第二下部半导体芯片111b可包括或不包括贯穿电极119。下部半导体芯片111a及下部半导体芯片111b可彼此电连接且可通过电连接至贯穿电极119的连接端子112而电连接至下部封装基板101。
参照图7H，半导体封装9可包括具有打线键合结构的下部封装100。下部封装100可包括多个键合线117，所述多个键合线117可被形成为将下部封装基板101电连接至下部半导体芯片110。下部半导体芯片110可通过绝缘粘合层113而附着至下部封装基板101。
图7A至图7H中所示的半导体封装2至半导体封装9的技术特征可彼此组合。作为实例，图7A所示的半导体封装2中的底部填充层114可设置在其他半导体封装3至半导体封装9中的至少一个中。作为另一实例，图7B所示的半导体封装3中的传热层116可设置在其他半导体封装2及半导体封装4至半导体封装9中的至少一个中。此外，除所述差异之外，半导体封装2至半导体封装9与前面参照图1A至图6B阐述的半导体封装1实质上相同。通篇中相同的参考编号指代相同的元件。
综上所述，根据某些实施例，利用相同的激光(例如，通过激光钻孔工艺)在原处执行导通孔形成工艺及激光标记工艺。在执行时不对半导体芯片造成损坏的同时，所述激光标记工艺提供具有高可见性的激光标记。由此，可提高制造方法中叠加良率，且可改善半导体封装的翘曲性质。
因此，可简化制造半导体封装的整个工艺且从而减少所述制造工艺的工艺时间。所述半导体封装制造工艺的简化可使得设备投资及制造工艺的成本降低。使用激光标记工艺可在不损坏半导体芯片的条件下使得清楚地形成激光标记成为可能并且可以改善半导体封装的翘曲性质。
已在本文中公开了示例性实施例，且尽管采用了特定用语，但所述特定用语仅在一般的及说明性的意义上使用及加以解释且并不出于限制目的。在某些情形中，如在提出本申请之前对所属领域中的普通技术人员而言将显而易见，除非另外具体地指明，否则结合具体实施例所阐述的特征、特性、及/或元件可单独地使用或与结合其他实施例所阐述的特征、特性、及/或元件组合使用。因此，所属领域中的技术人员将理解，在不背离以上权利要求书中提出的本发明的精神及范围的条件下，可对形式及细节作出各种改变。

Claims (25)

1.一种半导体封装，其特征在于，包括：
上部封装，叠加在下部封装上；以及
导通结构，位于所述下部封装与所述上部封装之间，以将所述下部封装与所述上部封装彼此电连接，
其中所述下部封装包括：
下部封装基板，
下部半导体芯片，位于所述下部封装基板上，以及
下部模塑层，囊封所述下部半导体芯片，所述下部模塑层具有位于标记区上的对准标记，所述标记区位于所述导通结构与所述下部半导体芯片之间。
2.根据权利要求1所述的半导体封装，其特征在于，所述对准标记包括第一标记及第二标记中的至少一个，所述第一标记用于将所述上部封装相对于所述下部封装进行旋转对准，且所述第二标记用于在所述下部封装的中心与所述上部封装的中心之间进行垂直对准。
3.根据权利要求2所述的半导体封装，其特征在于，所述第一标记包括与所述下部半导体芯片的至少一个隅角相邻的辨认标记。
4.根据权利要求3所述的半导体封装，其特征在于，所述上部封装包括与所述第一标记垂直对准的位置标记。
5.根据权利要求2所述的半导体封装，其特征在于，所述第二标记包括与所述下部半导体芯片的至少两个相对的隅角相邻的至少两个辨认标记。
6.根据权利要求1所述的半导体封装，其特征在于，
所述下部半导体芯片包括面对所述下部封装基板的底表面以及与所述底表面相对的顶表面，且
所述下部模塑层覆盖所述下部半导体芯片的所述顶表面。
7.根据权利要求1所述的半导体封装，其特征在于，
所述下部模塑层包括与所述下部半导体芯片的侧表面间隔开的导通孔，所述导通结构位于所述导通孔中，且
所述标记区具有与所述导通孔的深度实质上相等的厚度。
8.根据权利要求7所述的半导体封装，其特征在于，所述导通结构与所述导通孔的内侧表面间隔开。
9.根据权利要求8所述的半导体封装，其特征在于，所述导通孔的所述内侧表面具有沿远离所述下部封装基板的顶表面的方向增大的水平宽度。
10.一种半导体封装，其特征在于，包括：
下部封装，包括位于下部封装基板上的至少一个下部半导体芯片，所述下部半导体芯片被下部模塑层囊封；
上部封装，包括位于上部封装基板上的至少一个上部半导体芯片，所述上部半导体芯片被上部模塑层囊封；以及
导通结构，电连接所述下部封装至所述上部封装，
其中所述下部模塑层包括位于所述导通结构与所述下部半导体芯片之间的标记区，且
其中所述标记区包括：
旋转对准标记，使所述下部封装与所述上部封装具有相同的取向，以及
垂直对准标记，使所述下部封装的中心与所述上部封装的中心对准。
11.根据权利要求10所述的半导体封装，其特征在于，
所述旋转对准标记包括与所述下部半导体芯片的隅角中的一个相邻的辨认标记，且
所述垂直对准标记包括与所述下部半导体芯片的所述隅角中的至少两个相对的隅角相邻的至少两个辨认标记。
12.根据权利要求11所述的半导体封装，其特征在于，
所述上部封装基板包括顶表面及与所述顶表面相对的底表面，在所述顶表面上安装有所述上部半导体芯片，且
所述上部封装基板的所述底表面包括与所述旋转对准标记垂直对准的辨认标记。
13.根据权利要求10所述的半导体封装，其特征在于，所述标记区是对所述下部半导体芯片的侧表面进行封闭的所述下部模塑层的一部分。
14.根据权利要求10所述的半导体封装，其特征在于，
所述下部半导体芯片包括面对所述下部封装基板的底表面及与所述底表面相对的顶表面，且
所述下部模塑层包括处于比所述下部半导体芯片高的水平高度的顶表面。
15.根据权利要求10所述的半导体封装，其特征在于，
所述下部半导体芯片包括面对所述下部封装基板的底表面及与所述底表面相对的顶表面，且
所述下部模塑层包括与所述下部半导体芯片的顶表面共面的顶表面。
16.根据权利要求10所述的半导体封装，其特征在于，所述下部半导体芯片包括片上系统，且所述上部半导体芯片包括存储器芯片。
17.根据权利要求10所述的半导体封装，其特征在于，进一步包括底部填充层及传热层中的至少一个，所述底部填充层填充所述下部半导体芯片与所述下部封装之间的间隙，且所述传热层位于所述下部模塑层与所述上部封装基板之间。
18.根据权利要求10所述的半导体封装，其特征在于，所述导通结构位于所述下部封装基板与所述上部封装基板之间，所述导通结构与所述下部半导体芯片的侧表面间隔开以穿过所述下部模塑层。
19.根据权利要求18所述的半导体封装，其特征在于，所述下部模塑层界定容置所述导通结构的导通孔，且所述标记区位于所述导通孔与所述下部半导体芯片的所述侧表面之间。
20.一种半导体封装，包括：
下部封装，包括：
下部半导体芯片，位于下部封装基板上，以及
下部模塑层，囊封所述下部半导体芯片；以及
上部封装，垂直地叠加在所述下部封装上并经由多个导通结构电连接至所述下部封装，所述导通结构垂直地穿过所述下部模塑层，
其中所述下部模塑层包括顶表面，所述顶表面面对所述上部封装且具有至少一个辨认标记，所述辨认标记位于所述下部模塑层的一部分上，且所述下部模塑层的所述部分位于所述下部半导体芯片与所述导通结构之间以覆盖所述下部半导体芯片的侧表面。
21.一种半导体封装，其特征在于，包括：
上部封装，叠加在下部封装上；以及
导通结构，位于所述下部封装与所述上部封装之间，用于将所述下部封装与所述上部封装彼此电连接，
其中所述下部封装包括：
下部半导体芯片，位于下部封装基板上，以及
下部模塑层，囊封所述下部半导体芯片，所述下部模塑层具有位于所述导通结构与所述下部半导体芯片的侧向表面之间的对准标记，所述对准标记在水平方向上与所述导通结构及所述下部半导体芯片的所述侧向表面中的每一个间隔开。
22.根据权利要求21所述的半导体封装，其特征在于，所述对准标记位于所述下部模塑层的不与所述下部半导体芯片的顶部重叠的部分上。
23.根据权利要求21所述的半导体封装，其特征在于，所述对准标记面对所述上部封装，所述对准标记位于所述下部半导体芯片的所述侧向表面与紧邻的导通结构之间。
24.根据权利要求21所述的半导体封装，其特征在于，所述下部模塑层覆盖所述下部半导体芯片的顶表面，所述对准标记的深度等于或大于所述下部模塑层的覆盖所述下部半导体芯片的所述顶表面的部分的厚度。
25.根据权利要求21所述的半导体封装，其特征在于，界定所述对准标记的侧壁的所述下部模塑层的厚度等于所述导通结构的深度。
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