TWI411090B - 多晶片堆疊封裝結構 - Google Patents

多晶片堆疊封裝結構 Download PDF

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TWI411090B
TWI411090B TW099138064A TW99138064A TWI411090B TW I411090 B TWI411090 B TW I411090B TW 099138064 A TW099138064 A TW 099138064A TW 99138064 A TW99138064 A TW 99138064A TW I411090 B TWI411090 B TW I411090B
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wafer
package structure
semiconductor
stacked
electrical connection
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蔡芳霖
江政嘉
劉正仁
施嘉凱
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矽品精密工業股份有限公司
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Description

多晶片堆疊封裝結構
本發明是有關於一種晶片封裝結構，更詳而言之，是關於一種防止導電膠發生斷路現象的晶片封裝結構改良。
於晶片封裝製程中，晶片可藉由點膠技術而與基板完成電性連接，再由封裝膠體包覆晶片而完成封裝。於第20080303131、20090068790及20090230528號美國專利公開案中，皆已揭示之一種多晶片堆疊結構，舉例說明，請參閱第1圖及第2圖所繪示，分別係為習知多晶片堆疊結構之局部剖視圖及習知晶片封裝結構之局部俯視圖，於習知多晶片堆疊結構中，基板10中設置有複數電性連接墊11，且基板10開設有曝露出電性連接墊11之開窗12，於各晶片20上貼附有絕緣膠30，且各晶片20係以不妨礙電性連接墊11之點膠作業為原則下，堆疊於基板10上，導電膠40電性連接基板10之電性連接墊11及各晶片20之電極墊21，且導電膠40之一部分係填入於開窗12中。
惟，於習知晶片封裝結構中，由於基板10的表面不完全平整，使得介於最底層晶片20及基板10之間的絕緣膠30厚度需要較厚，(如第1圖所示)，使得最底層晶片20的電極墊21與基板10的電性連接墊11之間的高度落差過大，於施行點膠作業後，令導電膠40在此處造成頸縮的現象，或者由於毛細原理，使呈半液態之導電膠40填入於開窗12中之部分，非常容易從開窗12之鄰近電性連接墊11處，溢流至開窗12之遠離電性連接墊11處，因而產生膠寬頸縮效應，此效應令導電膠40在基板10與最底部晶片20之間處產生如烘烤後發生之斷點或斷膠情況而導致的電性斷路現象，使晶片封裝結構之導電性不良，如此，會造成產品損壞或需重新點膠之問題，令產品良率及可靠度降低。
綜上所述，如何提出一種可解決上述習知技術之缺失之多晶片堆疊封裝結構，以防止導電膠發生斷路現象，實為目前亟欲解決之技術問題。
鑒於上述習知技術之缺點，本發明之主要目的在於提供一種多晶片堆疊封裝結構，防止導電膠發生頸縮而導致電性斷路，進而提升產品良率及可靠度。
為達上述及其他目的，本發明提供一種多晶片堆疊封裝結構，係包括：晶片承載件，於該晶片承載件上設置有至少一電性連接墊；複數個半導體晶片，各該半導體晶片具有作用面及非作用面，且彼此以作用面朝上自該電性連接墊旁依序以錯位方式堆疊於該晶片承載件上，以使各該半導體晶片至少一部分之作用面係外露於堆疊其上之半導體晶片，且各該經堆疊之該半導體晶片的外露作用面上設有至少一電極墊；絕緣膠，設於該些半導體晶片之間及該與晶片承載件黏接之半導體晶片與該晶片承載件之間；以及導電膠，用以電性連接該電性連接墊及各該半導體晶片上之電極墊，以藉由該導電膠使該等半導體晶片均電性連接該晶片承載件，其中，該晶片承載件上形成有拒銲層，且該拒銲層開設有外露部分電性連接墊之開窗，以令外露之該電性連接墊的輪廓，在鄰近該半導體晶片處向遠離該半導體晶片處縮小。
在前述之多晶片堆疊封裝結構中，該晶片承載件為電路板，又各該半導體晶片彼此以作用面朝上自該電性連接墊旁依序以錯位方式堆疊於該晶片承載件上。更具體而言，該等半導體晶片彼此以階梯狀方式或鋸齒狀方式堆疊。惟，不論以何種方式堆疊，該與晶片承載件黏接之底部半導體晶片之電極墊旁之晶片承載件上係設有電性連接墊。
此外，本發明之多晶片堆疊封裝結構中，透過在晶片承載件上形成之拒銲層，開設有外露部分電性連接墊之開窗，以令外露之該電性連接墊的輪廓在鄰近該半導體晶片處向遠離該半導體晶片處縮小。舉例而言，該開窗之形狀係可為，但不限於梯形、T字形、三角形、半圓形、半橢圓形之其中之一者。
相較於習知技術，本發明之多晶片堆疊封裝結構，基於供該導電膠附著其上之該電性連接墊的輪廓，在鄰近該半導體晶片處向遠離該半導體晶片處縮小，此時，由於自然毛細原理，電性連接墊上之導電膠會依據所接觸之電性連接墊外形，限制並防止呈半液態之導電膠向遠離半導體晶片處溢流，使得膠寬緊縮效應減輕，防止導電膠在晶片承載件與半導體晶片之間處如烘烤後發生之斷點或斷膠情況而導致的斷路現象，如此，不會造成產品損壞或需進行重新點膠之問題，而能提升產品良率及可靠度。
以下是藉由特定的具體實例說明本發明之技術內容，熟悉此技藝之人士可由本說明書所揭示之內容輕易地瞭解本發明之其他優點與功效。
須知，本說明書所附圖式所繪示之結構、比例、大小等，均僅用以配合說明書所揭示之內容，以供熟悉此技藝之人士之瞭解與閱讀，並非用以限定本發明可實施之限定條件，故不具技術上之實質意義，任何結構之修飾、比例關係之改變或大小之調整，在不影響本發明所能產生之功效及所能達成之目的下，均應仍落在本發明所揭示之技術內容得能涵蓋之範圍內。
本發明提供一種多晶片堆疊封裝結構(Multi Stacked-Die Packaging Structure)，請參照第3圖及第4圖所繪示，分別係為本發明之多晶片堆疊封裝結構之局部側剖視圖及局部俯視圖，於本實施例中，該多晶片堆疊封裝結構包括晶片承載件100、複數個半導體晶片200、絕緣膠300及導電膠400。
晶片承載件100係例如為電路板，於晶片承載件100上設置有至少一電性連接墊110，其具有導電性質，又該電性連接墊110曝露於該晶片承載件100之上方空間。
半導體晶片200係例如為主動式晶片，如中央處理器晶片、快閃記憶體晶片、邏輯處理晶片；亦可為被動式晶片，如晶片式電容、晶片式電阻等，且各該半導體晶片200具有作用面及非作用面，並於該半導體晶片200的作用面上設有至少一電極墊210，又該絕緣膠300設於該些半導體晶片200之間，較佳地，該絕緣膠300預先貼附於各該半導體晶片200之非作用面，該絕緣膠300可例如為晶片接著層(Die Attach Film,DAF)，但不以此為限制，且各該半導體晶片200彼此以作用面朝上及自該電性連接墊110旁依序以錯位方式堆疊於該晶片承載件100上，以使各該半導體晶片200至少一部分之作用面係外露於堆疊其上之半導體晶片200。復進一步說明，該等半導體晶片200的平面尺寸約略相同，該與晶片承載件100黏接之半導體晶片200設置在鄰近該電性連接墊110之位置，上層之該等半導體晶片200則分別以一預先設定的距離依序偏移下層之該半導體晶片200而相互堆疊，且該等半導體晶片200不致遮蔽相鄰接晶片之電極墊210及晶片承載件100之該電性連接墊110。
故如前述，該經堆疊之各該半導體晶片200的外露作用面上具有至少一電極墊210，且該電性連接墊110設於該晶片承載件100上之位置係對應於該與晶片承載件100黏接之半導體晶片200之電極墊旁。詳言之，係於各該半導體晶片200上對應該電性連接墊110之同側處設置有至少一電極墊210，且該電極墊210曝露於相鄰該半導體晶片200之上方空間，意即上層之該半導體晶片200不致遮蔽下層之該半導體晶片的該電極墊210，此時，該電性連接墊110係設置於該晶片承載件100上未黏接該半導體晶片200之區域，該電極墊210係設置於該半導體晶片200上未堆疊其他該半導體晶片200之區域。
進一步詳細說明該絕緣膠300的設定位置及結構型態，該絕緣膠300介於該晶片承載件100及疊接在該晶片承載件100的該半導體晶片200之間，亦即，該絕緣膠300黏接於該晶片承載件100及疊接在該晶片承載件100的該半導體晶片200之間，其用以將該晶片承載件100及該底部半導體晶片200相互黏合而固定，並加以阻斷其之間的電性連接，且同時，該絕緣膠300介於任二相疊接的該半導體晶片200之間，亦即，該絕緣膠300復黏接於任二相疊接的該半導體晶片200之間，其用以將該等半導體晶片200相互黏合而固定，並加以阻斷其之間的電性連接。
此外，由於該晶片承載件100之表面不完全平整，令介於該晶片承載件100及該底部半導體晶片200之間的該絕緣膠300，其厚度需較厚，例如，25μm，但不以此數值為限定，而介於任二相疊接的該半導體晶片200之間的絕緣膠300厚度相對上則可較薄，例如，10μm，但不以此數值為限定，此時，介於該晶片承載件100及疊接在該晶片承載件100上的該半導體晶片200之間的絕緣膠300厚度大於任二相疊接的該半導體晶片200之間的絕緣膠300厚度。
導電膠400係以點膠方式而電性連接電性連接墊110及各該半導體晶片200上之電極墊210，以藉由該導電膠400使該等半導體晶片200均電性連接該晶片承載件100，其中，供該導電膠400附著其上之該電性連接墊110的輪廓，在鄰近該半導體晶片200處向遠離該半導體晶片200處縮小，如第4圖所示。
在本實施例中，供該導電膠400附著其上之該電性連接墊110的輪廓，在鄰近該半導體晶片200處向遠離該半導體晶片200處縮小之特徵，係透過在晶片承載件100上形成有拒銲層130，且該拒銲層130開設有外露部分電性連接墊110之開窗140，以令外露之該電性連接墊110的輪廓，在鄰近該半導體晶片200處向遠離該半導體晶片200處縮小。舉例而言，該開窗140之形狀係可如第5圖所示之梯形、T字形、三角形、半圓形、半橢圓形之其中之一者，但不以此些形狀為限。又，當開設有複數個開窗140時，依據需求條件，此些開窗140之形狀可為相同或不同，當形狀不同時，可加速辨識電性連接墊110之數目及位置。
此外，如第3圖所示，本發明之多晶片堆疊封裝結構復可包括絕緣塗層600。該絕緣塗層600塗佈於該等半導體晶片200或該晶片承載件100之外表，令整體結構對外界之絕緣性更佳，即於電氣上更為安全，該絕緣塗層600可為如聚對二甲苯(Parylene)之材質，且因具有固形性質，使得堆疊結構的強度較佳，並且，該絕緣塗層600可例如以雷射加工方式，而開設有複數窗孔610，又該等窗孔610分別對應於該開窗140及該等電極墊210位置，使得該開窗140及該等電極墊210不致被該絕緣塗層600所覆蓋。
請參照第6圖及第圖所繪示，分別係本發明之多晶片堆疊封裝結構的其他實施例。
如第6圖所示，該多晶片堆疊封裝結構係包括至少三個半導體晶片200，各該半導體晶片200彼此以作用面朝上自該電性連接墊110旁依序以錯位方式堆疊於該晶片承載件100上。具體而言，該等半導體晶片200彼此以階梯狀方式堆疊，因此，形成單邊懸空之階梯狀晶片堆疊結構。
如第7圖所示，該多晶片堆疊封裝結構係包括四個半導體晶片200，其中，該等半導體晶片200彼此以鋸齒狀方式堆疊，但供該導電膠400附著其上之該電性連接墊110的輪廓，在鄰近該半導體晶片200處向遠離該半導體晶片200處縮小，使得膠寬緊縮效應減輕，防止導電膠在晶片承載件與半導體晶片之間處如烘烤後發生之斷點或斷膠情況而導致的斷路現象。
此外，如第6及7圖所示，本發明之多晶片堆疊封裝結構復包括封裝樹脂500，覆蓋該晶片承載件100、半導體晶片200、絕緣膠300及導電膠400，俾以該封裝樹脂500具有的保護該多晶片堆疊封裝結構不受外界環境之破壞，提升安全性，其中，其覆蓋方式可藉由封裝模壓方式。
綜上所述，本發明之多晶片堆疊封裝結構係設計供該導電膠附著其上之該電性連接墊的輪廓，在鄰近該半導體晶片處向遠離該半導體晶片處縮小，此時，由於自然毛細原理，電性連接墊上之導電膠會依據所接觸之電性連接墊外形，限制並防止呈半液態之導電膠向遠離半導體晶片處溢流，使得膠寬緊縮效應減輕，防止導電膠在晶片承載件與半導體晶片之間處如烘烤後發生之斷點或斷膠情況而導致的斷路現象，如此，不會造成產品損壞或需進行重新點膠之問題，而能提升產品良率及可靠度。
上述實施例僅例示性說明本發明之原理及其功效，而非用於限制本發明。任何熟習此項技藝之人士均可在不違背本發明之精神及範疇下，對上述實施例進行修飾與改變。因此，本發明之權利保護範圍，應如後述之申請專利範圍所列。
10．．．基板
11．．．電性連接墊
12．．．開窗
20．．．晶片
21．．．電極墊
30．．．絕緣膠
40．．．導電膠
100．．．晶片承載件
110．．．電性連接墊
130．．．拒銲層
140．．．開窗
200．．．半導體晶片
210．．．電極墊
300．．．絕緣膠
400．．．導電膠
500．．．封裝樹脂
600．．．絕緣塗層
610．．．窗孔
第1圖係為習知多晶片堆疊結構之局部側剖視圖；
第2圖係第1圖習知多晶片堆疊結構之局部俯視圖；
第3圖係為本發明之多晶片堆疊封裝結構之局部剖視圖；
第4圖係第3圖之多晶片堆疊封裝結構之局部俯視圖其中，第4圖係省略視需要而塗佈地絕緣塗層；
第5圖係為本發明多晶片堆疊封裝結構之外露之電性連接墊輪廓示意圖；
第6圖係為本發明之階梯狀多晶片堆疊封裝結構之示意圖；以及
第7圖係為本發明之鋸齒狀多晶片堆疊封裝結構之示意圖。
100．．．晶片承載件
110．．．電性連接墊
130．．．拒銲層
140．．．開窗
200．．．半導體晶片
210．．．電極墊
400．．．導電膠

Claims (10)

  1. 一種多晶片堆疊封裝結構，係包括：晶片承載件，於該晶片承載件上設置有至少一電性連接墊；複數個半導體晶片，各該半導體晶片具有作用面及非作用面，且彼此以作用面朝上自該電性連接墊旁依序以錯位方式堆疊於該晶片承載件上，以使各該半導體晶片至少一部分之作用面係外露於堆疊其上之半導體晶片，且各該經堆疊之該半導體晶片的外露作用面上設有至少一電極墊；絕緣膠，設於該些半導體晶片之間及該與晶片承載件黏接之半導體晶片與該晶片承載件之間；以及導電膠，用以電性連接該電性連接墊及各該半導體晶片上之電極墊，以藉由該導電膠使該等半導體晶片均電性連接該晶片承載件，其中，該晶片承載件上形成有拒銲層，且該拒銲層開設有外露部分電性連接墊之開窗，以令外露之該電性連接墊的輪廓，在鄰近該半導體晶片處向遠離該半導體晶片處縮小。
  2. 如申請專利範圍第1項所述之多晶片堆疊封裝結構，其中，該晶片承載件為電路板。
  3. 如申請專利範圍第1項所述之多晶片堆疊封裝結構，其中，該等半導體晶片彼此以階梯狀方式堆疊。
  4. 如申請專利範圍第1項所述之多晶片堆疊封裝結構，其中，該等半導體晶片彼此以鋸齒狀方式堆疊。
  5. 如申請專利範圍第1項所述之多晶片堆疊封裝結構，其中，該電性連接墊設於該晶片承載件上之位置係對應於該與晶片承載件黏接之半導體晶片之電極墊旁。
  6. 如申請專利範圍第1項所述之多晶片堆疊封裝結構，其中，介於該晶片承載件及疊接在該晶片承載件上的該半導體晶片之間的絕緣膠厚度大於任二相疊接的該半導體晶片之間的絕緣膠厚度。
  7. 如申請專利範圍第1項所述之多晶片堆疊封裝結構，其中，該開窗之形狀係為梯形、T字形、三角形、半圓形、半橢圓形之其中之一者。
  8. 如申請專利範圍第1項所述之多晶片堆疊封裝結構，復包括絕緣塗層，塗佈於該晶片承載件或該等半導體晶片之外表。
  9. 如申請專利範圍第8項所述之多晶片堆疊封裝結構，其中，該絕緣塗層開設有複數窗孔，該等窗孔分別對應於該開窗及該等電極墊。
  10. 如申請專利範圍第1項所述之多晶片堆疊封裝結構，復包括封裝樹脂，覆蓋該晶片承載件、半導體晶片、絕緣膠及導電膠。
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